1 files changed, 110 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2509-drm-amd-display-enable-abm-on-dcn2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2509-drm-amd-display-enable-abm-on-dcn2.patch
new file mode 100644
index 00000000..9a686437
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2509-drm-amd-display-enable-abm-on-dcn2.patch
@@ -0,0 +1,110 @@
+From 85e7d8956758d1636682183327bcdd8abda11de5 Mon Sep 17 00:00:00 2001
+From: Josip Pavic <Josip.Pavic@amd.com>
+Date: Thu, 4 Apr 2019 13:44:27 -0400
+Subject: [PATCH 2509/2940] drm/amd/display: enable abm on dcn2
+
+[Why]
+ABM is currently not enabled on DCN2.
+
+[How]
+Update the register name list for DCN2 and un-comment the code that
+creates the abm object.
+
+Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h  | 20 +++++++++++++++++++
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 14 ++++++-------
+ 2 files changed, 27 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+index ff9436966041..7ba7e6f722f6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+@@ -67,6 +67,22 @@
+ 	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+ 	NBIO_SR(BIOS_SCRATCH_2)
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++#define ABM_DCN20_REG_LIST() \
++	ABM_COMMON_REG_LIST_DCE_BASE(), \
++	SR(DC_ABM1_HG_SAMPLE_RATE), \
++	SR(DC_ABM1_LS_SAMPLE_RATE), \
++	SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
++	SR(DC_ABM1_HG_MISC_CTRL), \
++	SR(DC_ABM1_IPCSC_COEFF_SEL), \
++	SR(BL1_PWM_CURRENT_ABM_LEVEL), \
++	SR(BL1_PWM_TARGET_ABM_LEVEL), \
++	SR(BL1_PWM_USER_LEVEL), \
++	SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
++	SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
++	NBIO_SR(BIOS_SCRATCH_2)
++#endif
++
+ #define ABM_SF(reg_name, field_name, post_fix)\
+ 	.field_name = reg_name ## __ ## field_name ## post_fix
+ 
+@@ -147,6 +163,10 @@
+ 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
++#endif
++
+ #define ABM_REG_FIELD_LIST(type) \
+ 	type ABM1_HG_NUM_OF_BINS_SEL; \
+ 	type ABM1_HG_VMAX_SEL; \
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2d6f9c4de893..0a11d1098a7e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -271,19 +271,19 @@ static const struct dce_dmcu_shift dmcu_shift = {
+ static const struct dce_dmcu_mask dmcu_mask = {
+ 		DMCU_MASK_SH_LIST_DCN10(_MASK)
+ };
+-/*
++
+ static const struct dce_abm_registers abm_regs = {
+-		ABM_DCN10_REG_LIST(0)
++		ABM_DCN20_REG_LIST()
+ };
+ 
+ static const struct dce_abm_shift abm_shift = {
+-		ABM_MASK_SH_LIST_DCN10(__SHIFT)
++		ABM_MASK_SH_LIST_DCN20(__SHIFT)
+ };
+ 
+ static const struct dce_abm_mask abm_mask = {
+-		ABM_MASK_SH_LIST_DCN10(_MASK)
++		ABM_MASK_SH_LIST_DCN20(_MASK)
+ };
+-*/
++
+ #define audio_regs(id)\
+ [id] = {\
+ 		AUD_COMMON_REG_LIST(id)\
+@@ -2811,7 +2811,7 @@ static bool construct(
+ 		goto create_fail;
+ 	}
+ 
+-	/*pool->base.abm = dce_abm_create(ctx,
++	pool->base.abm = dce_abm_create(ctx,
+ 			&abm_regs,
+ 			&abm_shift,
+ 			&abm_mask);
+@@ -2819,7 +2819,7 @@ static bool construct(
+ 		dm_error("DC: failed to create abm!\n");
+ 		BREAK_TO_DEBUGGER();
+ 		goto create_fail;
+-	}*/
++	}
+ 
+ 	pool->base.pp_smu = dcn20_pp_smu_create(ctx);
+ 
+-- 
+2.17.1
+