diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2486-drm-amd-display-fix-fpga-fclk-programming.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2486-drm-amd-display-fix-fpga-fclk-programming.patch | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2486-drm-amd-display-fix-fpga-fclk-programming.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2486-drm-amd-display-fix-fpga-fclk-programming.patch new file mode 100644 index 00000000..13d8dbee --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2486-drm-amd-display-fix-fpga-fclk-programming.patch @@ -0,0 +1,52 @@ +From c12c30e7857df4ec4053caea8618d7e83b494e95 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Thu, 21 Mar 2019 15:24:53 -0400 +Subject: [PATCH 2486/2940] drm/amd/display: fix fpga fclk programming + +We shouldnt need overhead on top of dppclk when setting fclk. + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +index 34402dffd2ca..c1511c9edd48 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +@@ -249,6 +249,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, + bool safe_to_lower) + { + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; ++ /* Min fclk = 1GHz since all the extra scemi logic seems to run off of it */ ++ int fclk_adj = new_clocks->fclk_khz > 1000000 ? new_clocks->fclk_khz : 1000000; + + if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { + clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; +@@ -275,9 +277,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, + clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; + } + +- /* Add 250MHz as safety margin */ +- if (should_set_clock(safe_to_lower, new_clocks->fclk_khz + 250000, clk_mgr->clks.fclk_khz)) { +- clk_mgr->clks.fclk_khz = new_clocks->fclk_khz + 250000; ++ if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { ++ clk_mgr->clks.fclk_khz = fclk_adj; + } + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { +@@ -289,6 +290,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, + */ + if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) + clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; ++ if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) ++ clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; + + dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); + } +-- +2.17.1 + |