diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2481-drm-amd-display-Properly-set-u-clock.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2481-drm-amd-display-Properly-set-u-clock.patch | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2481-drm-amd-display-Properly-set-u-clock.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2481-drm-amd-display-Properly-set-u-clock.patch new file mode 100644 index 00000000..50525b40 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2481-drm-amd-display-Properly-set-u-clock.patch @@ -0,0 +1,36 @@ +From 1de6265ba83176376a4be2863694dd35a48ccda7 Mon Sep 17 00:00:00 2001 +From: Aidan Wood <Aidan.Wood@amd.com> +Date: Fri, 22 Mar 2019 14:45:12 -0400 +Subject: [PATCH 2481/2940] drm/amd/display: Properly set u clock + +[Why] +u clk set request was being sent in units of mts, when it needed to be +in units of Mhz + +[How] +add a division by 16 to convert from mts to Mhz + +Signed-off-by: Aidan Wood <Aidan.Wood@amd.com> +Reviewed-by: Jun Lei <Jun.Lei@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 6bc4b3f3301f..7aa2859b35fc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -2132,7 +2132,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, + context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; + context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; + context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; +- context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000; ++ context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; + context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; + context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; + context->bw_ctx.bw.dcn.clk.p_state_change_support = +-- +2.17.1 + |