diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2440-drm-amd-display-Add-DCN2-DPP.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2440-drm-amd-display-Add-DCN2-DPP.patch | 2418 |
1 files changed, 2418 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2440-drm-amd-display-Add-DCN2-DPP.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2440-drm-amd-display-Add-DCN2-DPP.patch new file mode 100644 index 00000000..d34ffe90 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2440-drm-amd-display-Add-DCN2-DPP.patch @@ -0,0 +1,2418 @@ +From eb53574377f55dced6dd08d9d1d082ad43137db4 Mon Sep 17 00:00:00 2001 +From: Harry Wentland <harry.wentland@amd.com> +Date: Fri, 22 Feb 2019 15:50:50 -0500 +Subject: [PATCH 2440/2940] drm/amd/display: Add DCN2 DPP + +Add support to program the DCN2 DPP (Multiple pipe and plane combine) + +HW Blocks: + + +--------+ + | DPP | + +--------+ + | + v + +--------+ + | MPC | + +--------+ + | + v + +-------+ + | OPP | + +-------+ + | + v + +--------+ + | OPTC | + +--------+ + | + v + +--------+ +--------+ + | DIO | | DCCG | + +--------+ +--------+ + +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 10 + + .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 5 + + .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 + + .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 8 + + .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 493 +++++++++ + .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 698 ++++++++++++ + .../drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 990 ++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 53 + + 8 files changed, 2261 insertions(+) + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h + create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +index 6f4b24756323..b95ec73fcae3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +@@ -290,7 +290,12 @@ void dpp1_cnv_setup ( + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ enum dc_color_space input_color_space, ++ struct cnv_alpha_2bit_lut *alpha_2bit_lut) ++#else + enum dc_color_space input_color_space) ++#endif + { + uint32_t pixel_format; + uint32_t alpha_en; +@@ -523,6 +528,11 @@ static const struct dpp_funcs dcn10_dpp_funcs = { + .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, + .dpp_dppclk_control = dpp1_dppclk_control, + .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ .dpp_program_blnd_lut = NULL, ++ .dpp_program_shaper_lut = NULL, ++ .dpp_program_3dlut = NULL ++#endif + }; + + static struct dpp_caps dcn10_dpp_cap = { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +index 282e22f9b175..8a5517eebb7c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +@@ -1486,7 +1486,12 @@ void dpp1_cnv_setup ( + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ enum dc_color_space input_color_space, ++ struct cnv_alpha_2bit_lut *alpha_2bit_lut); ++#else + enum dc_color_space input_color_space); ++#endif + + void dpp1_full_bypass(struct dpp *dpp_base); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +index 882bcc5a40f6..aa0c7a7d13a0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +@@ -731,6 +731,10 @@ void dpp1_full_bypass(struct dpp *dpp_base) + /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */ + if (dpp->tf_mask->CM_BYPASS_EN) + REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ else ++ REG_SET(CM_CONTROL, 0, CM_BYPASS, 1); ++#endif + + /* Setting degamma bypass for now */ + REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +index ce21a290bf3e..d67e0abeee93 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +@@ -218,6 +218,14 @@ static void dpp1_dscl_set_lb( + INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ + LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ + } ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ else { ++ /* DSCL caps: pixel data processed in float format */ ++ REG_SET_2(LB_DATA_FORMAT, 0, ++ INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ ++ LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ ++ } ++#endif + + REG_SET_2(LB_MEMORY_CTRL, 0, + MEMORY_CONFIG, mem_size_config, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +new file mode 100644 +index 000000000000..b706190e16c1 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +@@ -0,0 +1,493 @@ ++/* ++ * Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#include "dm_services.h" ++ ++#include "core_types.h" ++ ++#include "reg_helper.h" ++#include "dcn20_dpp.h" ++#include "basics/conversion.h" ++ ++#define NUM_PHASES 64 ++#define HORZ_MAX_TAPS 8 ++#define VERT_MAX_TAPS 8 ++ ++#define BLACK_OFFSET_RGB_Y 0x0 ++#define BLACK_OFFSET_CBCR 0x8000 ++ ++#define REG(reg)\ ++ dpp->tf_regs->reg ++ ++#define CTX \ ++ dpp->base.ctx ++ ++#undef FN ++#define FN(reg_name, field_name) \ ++ dpp->tf_shift->field_name, dpp->tf_mask->field_name ++ ++void dpp20_read_state(struct dpp *dpp_base, ++ struct dcn_dpp_state *s) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_GET(DPP_CONTROL, ++ DPP_CLOCK_ENABLE, &s->is_enabled); ++ REG_GET(CM_DGAM_CONTROL, ++ CM_DGAM_LUT_MODE, &s->dgam_lut_mode); ++ // BGAM has no ROM, and definition is different, can't reuse same dump ++ //REG_GET(CM_BLNDGAM_CONTROL, ++ // CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode); ++ REG_GET(CM_GAMUT_REMAP_CONTROL, ++ CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); ++ if (s->gamut_remap_mode) { ++ s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); ++ s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); ++ s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); ++ s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); ++ s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); ++ s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); ++ } ++} ++ ++void dpp2_dummy_program_input_lut( ++ struct dpp *dpp_base, ++ const struct dc_gamma *gamma) ++{} ++ ++static void dpp2_cnv_setup ( ++ struct dpp *dpp_base, ++ enum surface_pixel_format format, ++ enum expansion_mode mode, ++ struct dc_csc_transform input_csc_color_matrix, ++ enum dc_color_space input_color_space, ++ struct cnv_alpha_2bit_lut *alpha_2bit_lut) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ uint32_t pixel_format = 0; ++ uint32_t alpha_en = 1; ++ enum dc_color_space color_space = COLOR_SPACE_SRGB; ++ enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS; ++ bool force_disable_cursor = false; ++ struct out_csc_color_matrix tbl_entry; ++ uint32_t is_2bit = 0; ++ int i = 0; ++ ++ REG_SET_2(FORMAT_CONTROL, 0, ++ CNVC_BYPASS, 0, ++ FORMAT_EXPANSION_MODE, mode); ++ ++ //hardcode default ++ //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14 ++ //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled ++ //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled ++ //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled ++ REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); ++ REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); ++ REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); ++ REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); ++ ++ switch (format) { ++ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: ++ pixel_format = 1; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_RGB565: ++ pixel_format = 3; ++ alpha_en = 0; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: ++ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: ++ pixel_format = 8; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: ++ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: ++ pixel_format = 10; ++ is_2bit = 1; ++ break; ++ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: ++ force_disable_cursor = false; ++ pixel_format = 65; ++ color_space = COLOR_SPACE_YCBCR709; ++ select = INPUT_CSC_SELECT_ICSC; ++ break; ++ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: ++ force_disable_cursor = true; ++ pixel_format = 64; ++ color_space = COLOR_SPACE_YCBCR709; ++ select = INPUT_CSC_SELECT_ICSC; ++ break; ++ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: ++ force_disable_cursor = true; ++ pixel_format = 67; ++ color_space = COLOR_SPACE_YCBCR709; ++ select = INPUT_CSC_SELECT_ICSC; ++ break; ++ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: ++ force_disable_cursor = true; ++ pixel_format = 66; ++ color_space = COLOR_SPACE_YCBCR709; ++ select = INPUT_CSC_SELECT_ICSC; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: ++ pixel_format = 22; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: ++ pixel_format = 24; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: ++ pixel_format = 25; ++ break; ++ case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: ++ pixel_format = 12; ++ color_space = COLOR_SPACE_YCBCR709; ++ select = INPUT_CSC_SELECT_ICSC; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: ++ pixel_format = 112; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: ++ pixel_format = 113; ++ break; ++ case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: ++ pixel_format = 114; ++ color_space = COLOR_SPACE_YCBCR709; ++ select = INPUT_CSC_SELECT_ICSC; ++ is_2bit = 1; ++ break; ++ case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: ++ pixel_format = 115; ++ color_space = COLOR_SPACE_YCBCR709; ++ select = INPUT_CSC_SELECT_ICSC; ++ is_2bit = 1; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: ++ pixel_format = 118; ++ break; ++ case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: ++ pixel_format = 119; ++ break; ++ default: ++ break; ++ } ++ ++ if (is_2bit == 1 && alpha_2bit_lut != NULL) { ++ REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); ++ REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); ++ REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); ++ REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); ++ } ++ ++ REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, ++ CNVC_SURFACE_PIXEL_FORMAT, pixel_format); ++ REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); ++ ++ // if input adjustments exist, program icsc with those values ++ if (input_csc_color_matrix.enable_adjustment ++ == true) { ++ for (i = 0; i < 12; i++) ++ tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; ++ ++ tbl_entry.color_space = input_color_space; ++ ++ if (color_space >= COLOR_SPACE_YCBCR601) ++ select = INPUT_CSC_SELECT_ICSC; ++ else ++ select = INPUT_CSC_SELECT_BYPASS; ++ ++ dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); ++ } else ++ dpp1_program_input_csc(dpp_base, color_space, select, NULL); ++ ++ if (force_disable_cursor) { ++ REG_UPDATE(CURSOR_CONTROL, ++ CURSOR_ENABLE, 0); ++ REG_UPDATE(CURSOR0_CONTROL, ++ CUR0_ENABLE, 0); ++ ++ } ++ ++} ++ ++void dpp2_cnv_set_bias_scale( ++ struct dpp *dpp_base, ++ struct dc_bias_and_scale *bias_and_scale) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red); ++ REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green); ++ REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue); ++ REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red); ++ REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green); ++ REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue); ++} ++ ++/*compute the maximum number of lines that we can fit in the line buffer*/ ++void dscl2_calc_lb_num_partitions( ++ const struct scaler_data *scl_data, ++ enum lb_memory_config lb_config, ++ int *num_part_y, ++ int *num_part_c) ++{ ++ int line_size = scl_data->viewport.width < scl_data->recout.width ? ++ scl_data->viewport.width : scl_data->recout.width; ++ int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? ++ scl_data->viewport_c.width : scl_data->recout.width; ++ int memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ ++ int memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ ++ int memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ ++ int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a; ++ ++ if (lb_config == LB_MEMORY_CONFIG_1) { ++ lb_memory_size = 970; ++ lb_memory_size_c = 970; ++ lb_memory_size_a = 970; ++ } else if (lb_config == LB_MEMORY_CONFIG_2) { ++ lb_memory_size = 1290; ++ lb_memory_size_c = 1290; ++ lb_memory_size_a = 1290; ++ } else if (lb_config == LB_MEMORY_CONFIG_3) { ++ /* 420 mode: using 3rd mem from Y, Cr and Cb */ ++ lb_memory_size = 970 + 1290 + 484 + 484 + 484; ++ lb_memory_size_c = 970 + 1290; ++ lb_memory_size_a = 970 + 1290 + 484; ++ } else { ++ lb_memory_size = 970 + 1290 + 484; ++ lb_memory_size_c = 970 + 1290 + 484; ++ lb_memory_size_a = 970 + 1290 + 484; ++ } ++ *num_part_y = lb_memory_size / memory_line_size_y; ++ *num_part_c = lb_memory_size_c / memory_line_size_c; ++ num_partitions_a = lb_memory_size_a / memory_line_size_a; ++ ++ if (scl_data->lb_params.alpha_en ++ && (num_partitions_a < *num_part_y)) ++ *num_part_y = num_partitions_a; ++ ++ if (*num_part_y > 64) ++ *num_part_y = 64; ++ if (*num_part_c > 64) ++ *num_part_c = 64; ++} ++ ++void dpp2_cnv_set_alpha_keyer( ++ struct dpp *dpp_base, ++ struct cnv_color_keyer_params *color_keyer) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en); ++ ++ REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode); ++ ++ REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low); ++ REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high); ++ ++ REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low); ++ REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high); ++ ++ REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low); ++ REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high); ++ ++ REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low); ++ REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high); ++} ++ ++void dpp2_set_cursor_attributes( ++ struct dpp *dpp_base, ++ enum dc_cursor_color_format color_format) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ int cur_rom_en = 0; ++ ++ if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || ++ color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) ++ cur_rom_en = 1; ++ ++ REG_UPDATE_3(CURSOR0_CONTROL, ++ CUR0_MODE, color_format, ++ CUR0_EXPANSION_MODE, 0, ++ CUR0_ROM_EN, cur_rom_en); ++ ++ if (color_format == CURSOR_MODE_MONO) { ++ /* todo: clarify what to program these to */ ++ REG_UPDATE(CURSOR0_COLOR0, ++ CUR0_COLOR0, 0x00000000); ++ REG_UPDATE(CURSOR0_COLOR1, ++ CUR0_COLOR1, 0xFFFFFFFF); ++ } ++} ++ ++#define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19)) ++ ++bool dpp2_get_optimal_number_of_taps( ++ struct dpp *dpp, ++ struct scaler_data *scl_data, ++ const struct scaling_taps *in_taps) ++{ ++ uint32_t pixel_width; ++ ++ if (scl_data->viewport.width > scl_data->recout.width) ++ pixel_width = scl_data->recout.width; ++ else ++ pixel_width = scl_data->viewport.width; ++ ++ /* Some ASICs does not support FP16 scaling, so we reject modes require this*/ ++ if (scl_data->viewport.width != scl_data->h_active && ++ scl_data->viewport.height != scl_data->v_active && ++ dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && ++ scl_data->format == PIXEL_FORMAT_FP16) ++ return false; ++ ++ if (scl_data->viewport.width > scl_data->h_active && ++ dpp->ctx->dc->debug.max_downscale_src_width != 0 && ++ scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) ++ return false; ++ ++ /* TODO: add lb check */ ++ ++ /* No support for programming ratio of 8, drop to 7.99999.. */ ++ if (scl_data->ratios.horz.value == (8ll << 32)) ++ scl_data->ratios.horz.value--; ++ if (scl_data->ratios.vert.value == (8ll << 32)) ++ scl_data->ratios.vert.value--; ++ if (scl_data->ratios.horz_c.value == (8ll << 32)) ++ scl_data->ratios.horz_c.value--; ++ if (scl_data->ratios.vert_c.value == (8ll << 32)) ++ scl_data->ratios.vert_c.value--; ++ ++ /* Set default taps if none are provided */ ++ if (in_taps->h_taps == 0) { ++ if (dc_fixpt_ceil(scl_data->ratios.horz) > 4) ++ scl_data->taps.h_taps = 8; ++ else ++ scl_data->taps.h_taps = 4; ++ } else ++ scl_data->taps.h_taps = in_taps->h_taps; ++ if (in_taps->v_taps == 0) { ++ if (dc_fixpt_ceil(scl_data->ratios.vert) > 4) ++ scl_data->taps.v_taps = 8; ++ else ++ scl_data->taps.v_taps = 4; ++ } else ++ scl_data->taps.v_taps = in_taps->v_taps; ++ if (in_taps->v_taps_c == 0) { ++ if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 4) ++ scl_data->taps.v_taps_c = 4; ++ else ++ scl_data->taps.v_taps_c = 2; ++ } else ++ scl_data->taps.v_taps_c = in_taps->v_taps_c; ++ if (in_taps->h_taps_c == 0) { ++ if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 4) ++ scl_data->taps.h_taps_c = 4; ++ else ++ scl_data->taps.h_taps_c = 2; ++ } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) ++ /* Only 1 and even h_taps_c are supported by hw */ ++ scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; ++ else ++ scl_data->taps.h_taps_c = in_taps->h_taps_c; ++ ++ if (!dpp->ctx->dc->debug.always_scale) { ++ if (IDENTITY_RATIO(scl_data->ratios.horz)) ++ scl_data->taps.h_taps = 1; ++ if (IDENTITY_RATIO(scl_data->ratios.vert)) ++ scl_data->taps.v_taps = 1; ++ if (IDENTITY_RATIO(scl_data->ratios.horz_c)) ++ scl_data->taps.h_taps_c = 1; ++ if (IDENTITY_RATIO(scl_data->ratios.vert_c)) ++ scl_data->taps.v_taps_c = 1; ++ } ++ ++ return true; ++} ++ ++void oppn20_dummy_program_regamma_pwl( ++ struct dpp *dpp, ++ const struct pwl_params *params, ++ enum opp_regamma mode) ++{} ++ ++static struct dpp_funcs dcn20_dpp_funcs = { ++ .dpp_read_state = dpp20_read_state, ++ .dpp_reset = dpp_reset, ++ .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, ++ .dpp_get_optimal_number_of_taps = dpp2_get_optimal_number_of_taps, ++ .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap, ++ .dpp_set_csc_adjustment = NULL, ++ .dpp_set_csc_default = NULL, ++ .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl, ++ .dpp_set_degamma = dpp2_set_degamma, ++ .dpp_program_input_lut = dpp2_dummy_program_input_lut, ++ .dpp_full_bypass = dpp1_full_bypass, ++ .dpp_setup = dpp2_cnv_setup, ++ .dpp_program_degamma_pwl = dpp2_set_degamma_pwl, ++ .dpp_program_blnd_lut = dpp20_program_blnd_lut, ++ .dpp_program_shaper_lut = dpp20_program_shaper, ++ .dpp_program_3dlut = dpp20_program_3dlut, ++ .dpp_program_bias_and_scale = NULL, ++ .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, ++ .set_cursor_attributes = dpp2_set_cursor_attributes, ++ .set_cursor_position = dpp1_set_cursor_position, ++ .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, ++ .dpp_dppclk_control = dpp1_dppclk_control, ++ .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier, ++}; ++ ++static struct dpp_caps dcn20_dpp_cap = { ++ .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, ++ .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, ++}; ++ ++bool dpp2_construct( ++ struct dcn20_dpp *dpp, ++ struct dc_context *ctx, ++ uint32_t inst, ++ const struct dcn2_dpp_registers *tf_regs, ++ const struct dcn2_dpp_shift *tf_shift, ++ const struct dcn2_dpp_mask *tf_mask) ++{ ++ dpp->base.ctx = ctx; ++ ++ dpp->base.inst = inst; ++ dpp->base.funcs = &dcn20_dpp_funcs; ++ dpp->base.caps = &dcn20_dpp_cap; ++ ++ dpp->tf_regs = tf_regs; ++ dpp->tf_shift = tf_shift; ++ dpp->tf_mask = tf_mask; ++ ++ dpp->lb_pixel_depth_supported = ++ LB_PIXEL_DEPTH_18BPP | ++ LB_PIXEL_DEPTH_24BPP | ++ LB_PIXEL_DEPTH_30BPP; ++ ++ dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; ++ dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ ++ ++ return true; ++} ++ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h +new file mode 100644 +index 000000000000..59b67ed57c19 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h +@@ -0,0 +1,698 @@ ++/* Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#ifndef __DCN20_DPP_H__ ++#define __DCN20_DPP_H__ ++ ++#include "dcn10/dcn10_dpp.h" ++ ++#define TO_DCN20_DPP(dpp)\ ++ container_of(dpp, struct dcn20_dpp, base) ++ ++#define TF_REG_LIST_DCN20(id) \ ++ TF_REG_LIST_DCN(id), \ ++ SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \ ++ SRI(CM_BLNDGAM_CONTROL, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_END_CNTL2_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_END_CNTL1_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_END_CNTL2_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_0_1, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_2_3, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_4_5, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_6_7, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_8_9, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_10_11, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_12_13, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_14_15, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_16_17, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_18_19, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_20_21, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_22_23, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_24_25, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_26_27, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_28_29, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_30_31, CM, id), \ ++ SRI(CM_BLNDGAM_RAMB_REGION_32_33, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_END_CNTL2_G, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_END_CNTL1_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_END_CNTL2_R, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_0_1, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_2_3, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_4_5, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_6_7, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_8_9, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_10_11, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_12_13, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_14_15, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_16_17, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_18_19, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_20_21, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_22_23, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_24_25, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_26_27, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_28_29, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_30_31, CM, id), \ ++ SRI(CM_BLNDGAM_RAMA_REGION_32_33, CM, id), \ ++ SRI(CM_BLNDGAM_LUT_INDEX, CM, id), \ ++ SRI(CM_BLNDGAM_LUT_DATA, CM, id), \ ++ SRI(CM_3DLUT_MODE, CM, id), \ ++ SRI(CM_3DLUT_INDEX, CM, id), \ ++ SRI(CM_3DLUT_DATA, CM, id), \ ++ SRI(CM_3DLUT_DATA_30BIT, CM, id), \ ++ SRI(CM_3DLUT_READ_WRITE_CONTROL, CM, id), \ ++ SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \ ++ SRI(CM_SHAPER_CONTROL, CM, id), \ ++ SRI(CM_SHAPER_RAMB_START_CNTL_B, CM, id), \ ++ SRI(CM_SHAPER_RAMB_START_CNTL_G, CM, id), \ ++ SRI(CM_SHAPER_RAMB_START_CNTL_R, CM, id), \ ++ SRI(CM_SHAPER_RAMB_END_CNTL_B, CM, id), \ ++ SRI(CM_SHAPER_RAMB_END_CNTL_G, CM, id), \ ++ SRI(CM_SHAPER_RAMB_END_CNTL_R, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_0_1, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_2_3, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_4_5, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_6_7, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_8_9, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_10_11, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_12_13, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_14_15, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_16_17, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_18_19, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_20_21, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_22_23, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_24_25, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_26_27, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_28_29, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_30_31, CM, id), \ ++ SRI(CM_SHAPER_RAMB_REGION_32_33, CM, id), \ ++ SRI(CM_SHAPER_RAMA_START_CNTL_B, CM, id), \ ++ SRI(CM_SHAPER_RAMA_START_CNTL_G, CM, id), \ ++ SRI(CM_SHAPER_RAMA_START_CNTL_R, CM, id), \ ++ SRI(CM_SHAPER_RAMA_END_CNTL_B, CM, id), \ ++ SRI(CM_SHAPER_RAMA_END_CNTL_G, CM, id), \ ++ SRI(CM_SHAPER_RAMA_END_CNTL_R, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_0_1, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_2_3, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_4_5, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_6_7, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_8_9, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_10_11, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_12_13, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_14_15, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_16_17, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_18_19, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_20_21, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_22_23, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_24_25, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_26_27, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \ ++ SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \ ++ SRI(CM_SHAPER_LUT_INDEX, CM, id), \ ++ SRI(CURSOR_CONTROL, CURSOR0_, id), \ ++ SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \ ++ SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \ ++ SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \ ++ SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \ ++ SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \ ++ SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \ ++ SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \ ++ SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ ++ SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ ++ SRI(COLOR_KEYER_RED, CNVC_CFG, id), \ ++ SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \ ++ SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \ ++ SRI(CM_SHAPER_LUT_DATA, CM, id), \ ++ SRI(CURSOR_CONTROL, CURSOR0_, id) ++ ++#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ ++ TF_REG_LIST_SH_MASK_DCN(mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \ ++ TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \ ++ TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_INDEX, CM_3DLUT_INDEX, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA1, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_DATA_30BIT, CM_3DLUT_DATA_30BIT, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_CONFIG_STATUS, mask_sh), \ ++ TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \ ++ TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh), \ ++ TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \ ++ TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \ ++ TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ ++ TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ ++ TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ ++ TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ ++ TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ ++ TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ ++ TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ ++ TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \ ++ TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \ ++ TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \ ++ TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \ ++ TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \ ++ TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \ ++ TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \ ++ TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \ ++ TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \ ++ TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \ ++ TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \ ++ TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ ++ TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ ++ TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ ++ TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh) ++ ++#define TF_REG_FIELD_LIST_DCN2_0(type) \ ++ TF_REG_FIELD_LIST(type) \ ++ type CM_BLNDGAM_LUT_DATA; \ ++ type FORMAT_CNV16; \ ++ type CNVC_BYPASS_MSB_ALIGN; \ ++ type CLAMP_POSITIVE; \ ++ type CLAMP_POSITIVE_C; \ ++ type ALPHA_2BIT_LUT0; \ ++ type ALPHA_2BIT_LUT1; \ ++ type ALPHA_2BIT_LUT2; \ ++ type ALPHA_2BIT_LUT3; \ ++ type FCNV_FP_BIAS_R; \ ++ type FCNV_FP_BIAS_G; \ ++ type FCNV_FP_BIAS_B; \ ++ type FCNV_FP_SCALE_R; \ ++ type FCNV_FP_SCALE_G; \ ++ type FCNV_FP_SCALE_B; \ ++ type COLOR_KEYER_EN; \ ++ type COLOR_KEYER_MODE; \ ++ type COLOR_KEYER_ALPHA_LOW; \ ++ type COLOR_KEYER_ALPHA_HIGH; \ ++ type COLOR_KEYER_RED_LOW; \ ++ type COLOR_KEYER_RED_HIGH; \ ++ type COLOR_KEYER_GREEN_LOW; \ ++ type COLOR_KEYER_GREEN_HIGH; \ ++ type COLOR_KEYER_BLUE_LOW; \ ++ type COLOR_KEYER_BLUE_HIGH; \ ++ type CUR0_PIX_INV_MODE; \ ++ type CUR0_PIXEL_ALPHA_MOD_EN; \ ++ type CUR0_ROM_EN ++ ++struct dcn2_dpp_shift { ++ TF_REG_FIELD_LIST_DCN2_0(uint8_t); ++}; ++ ++struct dcn2_dpp_mask { ++ TF_REG_FIELD_LIST_DCN2_0(uint32_t); ++}; ++ ++#define DPP_DCN2_REG_VARIABLE_LIST \ ++ DPP_COMMON_REG_VARIABLE_LIST \ ++ uint32_t CM_BLNDGAM_LUT_DATA; \ ++ uint32_t ALPHA_2BIT_LUT; \ ++ uint32_t FCNV_FP_BIAS_R; \ ++ uint32_t FCNV_FP_BIAS_G; \ ++ uint32_t FCNV_FP_BIAS_B; \ ++ uint32_t FCNV_FP_SCALE_R; \ ++ uint32_t FCNV_FP_SCALE_G; \ ++ uint32_t FCNV_FP_SCALE_B; \ ++ uint32_t COLOR_KEYER_CONTROL; \ ++ uint32_t COLOR_KEYER_ALPHA; \ ++ uint32_t COLOR_KEYER_RED; \ ++ uint32_t COLOR_KEYER_GREEN; \ ++ uint32_t COLOR_KEYER_BLUE ++ ++struct dcn2_dpp_registers { ++ DPP_DCN2_REG_VARIABLE_LIST; ++}; ++ ++struct dcn20_dpp { ++ struct dpp base; ++ ++ const struct dcn2_dpp_registers *tf_regs; ++ const struct dcn2_dpp_shift *tf_shift; ++ const struct dcn2_dpp_mask *tf_mask; ++ ++ const uint16_t *filter_v; ++ const uint16_t *filter_h; ++ const uint16_t *filter_v_c; ++ const uint16_t *filter_h_c; ++ int lb_pixel_depth_supported; ++ int lb_memory_size; ++ int lb_bits_per_entry; ++ bool is_write_to_ram_a_safe; ++ struct scaler_data scl_data; ++ struct pwl_params pwl_data; ++}; ++ ++void dpp20_read_state(struct dpp *dpp_base, ++ struct dcn_dpp_state *s); ++ ++void dpp2_set_degamma_pwl( ++ struct dpp *dpp_base, ++ const struct pwl_params *params); ++ ++void dpp2_set_degamma( ++ struct dpp *dpp_base, ++ enum ipp_degamma_mode mode); ++ ++bool dpp20_program_blnd_lut( ++ struct dpp *dpp_base, const struct pwl_params *params); ++ ++bool dpp20_program_shaper( ++ struct dpp *dpp_base, ++ const struct pwl_params *params); ++ ++bool dpp20_program_3dlut( ++ struct dpp *dpp_base, ++ struct tetrahedral_params *params); ++ ++void dpp2_cnv_set_alpha_keyer( ++ struct dpp *dpp_base, ++ struct cnv_color_keyer_params *color_keyer); ++ ++void dscl2_calc_lb_num_partitions( ++ const struct scaler_data *scl_data, ++ enum lb_memory_config lb_config, ++ int *num_part_y, ++ int *num_part_c); ++ ++void dpp2_set_cursor_attributes( ++ struct dpp *dpp_base, ++ enum dc_cursor_color_format color_format); ++ ++void dpp2_dummy_program_input_lut( ++ struct dpp *dpp_base, ++ const struct dc_gamma *gamma); ++ ++void oppn20_dummy_program_regamma_pwl( ++ struct dpp *dpp, ++ const struct pwl_params *params, ++ enum opp_regamma mode); ++ ++void dpp2_set_hdr_multiplier( ++ struct dpp *dpp_base, ++ uint32_t multiplier); ++ ++bool dpp2_get_optimal_number_of_taps( ++ struct dpp *dpp, ++ struct scaler_data *scl_data, ++ const struct scaling_taps *in_taps); ++ ++bool dpp2_construct(struct dcn20_dpp *dpp2, ++ struct dc_context *ctx, ++ uint32_t inst, ++ const struct dcn2_dpp_registers *tf_regs, ++ const struct dcn2_dpp_shift *tf_shift, ++ const struct dcn2_dpp_mask *tf_mask); ++ ++#endif /* __DC_HWSS_DCN20_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c +new file mode 100644 +index 000000000000..e28b8e7bedf5 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c +@@ -0,0 +1,990 @@ ++/* ++ * Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++#include "dm_services.h" ++ ++#include "core_types.h" ++ ++#include "reg_helper.h" ++#include "dcn20_dpp.h" ++#include "basics/conversion.h" ++ ++#include "dcn10/dcn10_cm_common.h" ++ ++#define REG(reg)\ ++ dpp->tf_regs->reg ++ ++#define CTX \ ++ dpp->base.ctx ++ ++#undef FN ++#define FN(reg_name, field_name) \ ++ dpp->tf_shift->field_name, dpp->tf_mask->field_name ++ ++ ++ ++ ++ ++static void dpp2_enable_cm_block( ++ struct dpp *dpp_base) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE(CM_CONTROL, CM_BYPASS, 0); ++} ++ ++ ++static bool dpp2_degamma_ram_inuse( ++ struct dpp *dpp_base, ++ bool *ram_a_inuse) ++{ ++ bool ret = false; ++ uint32_t status_reg = 0; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_GET(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, ++ &status_reg); ++ ++ if (status_reg == 3) { ++ *ram_a_inuse = true; ++ ret = true; ++ } else if (status_reg == 4) { ++ *ram_a_inuse = false; ++ ret = true; ++ } ++ return ret; ++} ++ ++static void dpp2_program_degamma_lut( ++ struct dpp *dpp_base, ++ const struct pwl_result_data *rgb, ++ uint32_t num, ++ bool is_ram_a) ++{ ++ uint32_t i; ++ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, ++ CM_DGAM_LUT_WRITE_EN_MASK, 7); ++ REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, ++ is_ram_a == true ? 0:1); ++ ++ REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); ++ for (i = 0 ; i < num; i++) { ++ REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); ++ REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); ++ REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); ++ ++ REG_SET(CM_DGAM_LUT_DATA, 0, ++ CM_DGAM_LUT_DATA, rgb[i].delta_red_reg); ++ REG_SET(CM_DGAM_LUT_DATA, 0, ++ CM_DGAM_LUT_DATA, rgb[i].delta_green_reg); ++ REG_SET(CM_DGAM_LUT_DATA, 0, ++ CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg); ++ ++ } ++ ++} ++ ++void dpp2_set_degamma_pwl( ++ struct dpp *dpp_base, ++ const struct pwl_params *params) ++{ ++ bool is_ram_a = true; ++ ++ dpp1_power_on_degamma_lut(dpp_base, true); ++ dpp2_enable_cm_block(dpp_base); ++ dpp2_degamma_ram_inuse(dpp_base, &is_ram_a); ++ if (is_ram_a == true) ++ dpp1_program_degamma_lutb_settings(dpp_base, params); ++ else ++ dpp1_program_degamma_luta_settings(dpp_base, params); ++ ++ dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); ++ dpp1_degamma_ram_select(dpp_base, !is_ram_a); ++} ++ ++void dpp2_set_degamma( ++ struct dpp *dpp_base, ++ enum ipp_degamma_mode mode) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ dpp2_enable_cm_block(dpp_base); ++ ++ switch (mode) { ++ case IPP_DEGAMMA_MODE_BYPASS: ++ /* Setting de gamma bypass for now */ ++ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); ++ break; ++ case IPP_DEGAMMA_MODE_HW_sRGB: ++ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); ++ break; ++ case IPP_DEGAMMA_MODE_HW_xvYCC: ++ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); ++ break; ++ default: ++ BREAK_TO_DEBUGGER(); ++ break; ++ } ++} ++ ++static void dpp20_power_on_blnd_lut( ++ struct dpp *dpp_base, ++ bool power_on) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_SET(CM_MEM_PWR_CTRL, 0, ++ BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0:1); ++ ++} ++ ++static void dpp20_configure_blnd_lut( ++ struct dpp *dpp_base, ++ bool is_ram_a) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK, ++ CM_BLNDGAM_LUT_WRITE_EN_MASK, 7); ++ REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK, ++ CM_BLNDGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); ++ REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); ++} ++ ++static void dpp20_program_blnd_pwl( ++ struct dpp *dpp_base, ++ const struct pwl_result_data *rgb, ++ uint32_t num) ++{ ++ uint32_t i; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ for (i = 0 ; i < num; i++) { ++ REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); ++ REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); ++ REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); ++ ++ REG_SET(CM_BLNDGAM_LUT_DATA, 0, ++ CM_BLNDGAM_LUT_DATA, rgb[i].delta_red_reg); ++ REG_SET(CM_BLNDGAM_LUT_DATA, 0, ++ CM_BLNDGAM_LUT_DATA, rgb[i].delta_green_reg); ++ REG_SET(CM_BLNDGAM_LUT_DATA, 0, ++ CM_BLNDGAM_LUT_DATA, rgb[i].delta_blue_reg); ++ ++ } ++ ++} ++ ++static void dcn20_dpp_cm_get_reg_field( ++ struct dcn20_dpp *dpp, ++ struct xfer_func_reg *reg) ++{ ++ reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; ++ reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; ++ reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; ++ reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; ++ reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; ++ reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; ++ reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; ++ reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; ++ ++ reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; ++ reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; ++ reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; ++ reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; ++ reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; ++ reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; ++ reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; ++ reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; ++ reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; ++ reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; ++ reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; ++ reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; ++} ++ ++/*program blnd lut RAM A*/ ++static void dpp20_program_blnd_luta_settings( ++ struct dpp *dpp_base, ++ const struct pwl_params *params) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ struct xfer_func_reg gam_regs; ++ ++ dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); ++ ++ gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); ++ gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); ++ gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); ++ gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_B); ++ gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_G); ++ gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R); ++ gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); ++ gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); ++ gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); ++ gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); ++ gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); ++ gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); ++ gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); ++ gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); ++ ++ cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); ++} ++ ++/*program blnd lut RAM B*/ ++static void dpp20_program_blnd_lutb_settings( ++ struct dpp *dpp_base, ++ const struct pwl_params *params) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ struct xfer_func_reg gam_regs; ++ ++ dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); ++ ++ gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); ++ gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); ++ gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); ++ gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_B); ++ gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_G); ++ gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R); ++ gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); ++ gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); ++ gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); ++ gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); ++ gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); ++ gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); ++ gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); ++ gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); ++ ++ cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); ++} ++ ++static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base) ++{ ++ enum dc_lut_mode mode; ++ uint32_t state_mode; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, ++ CM_BLNDGAM_CONFIG_STATUS, &state_mode); ++ ++ switch (state_mode) { ++ case 0: ++ mode = LUT_BYPASS; ++ break; ++ case 1: ++ mode = LUT_RAM_A; ++ break; ++ case 2: ++ mode = LUT_RAM_B; ++ break; ++ default: ++ mode = LUT_BYPASS; ++ break; ++ } ++ return mode; ++} ++ ++bool dpp20_program_blnd_lut( ++ struct dpp *dpp_base, const struct pwl_params *params) ++{ ++ enum dc_lut_mode current_mode; ++ enum dc_lut_mode next_mode; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ if (params == NULL) { ++ REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, 0); ++ return false; ++ } ++ current_mode = dpp20_get_blndgam_current(dpp_base); ++ if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) ++ next_mode = LUT_RAM_B; ++ else ++ next_mode = LUT_RAM_A; ++ ++ dpp20_power_on_blnd_lut(dpp_base, true); ++ dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); ++ ++ if (next_mode == LUT_RAM_A) ++ dpp20_program_blnd_luta_settings(dpp_base, params); ++ else ++ dpp20_program_blnd_lutb_settings(dpp_base, params); ++ ++ dpp20_program_blnd_pwl( ++ dpp_base, params->rgb_resulted, params->hw_points_num); ++ ++ REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, ++ next_mode == LUT_RAM_A ? 1:2); ++ ++ return true; ++} ++ ++ ++static void dpp20_program_shaper_lut( ++ struct dpp *dpp_base, ++ const struct pwl_result_data *rgb, ++ uint32_t num) ++{ ++ uint32_t i, red, green, blue; ++ uint32_t red_delta, green_delta, blue_delta; ++ uint32_t red_value, green_value, blue_value; ++ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ for (i = 0 ; i < num; i++) { ++ ++ red = rgb[i].red_reg; ++ green = rgb[i].green_reg; ++ blue = rgb[i].blue_reg; ++ ++ red_delta = rgb[i].delta_red_reg; ++ green_delta = rgb[i].delta_green_reg; ++ blue_delta = rgb[i].delta_blue_reg; ++ ++ red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); ++ green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); ++ blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); ++ ++ REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); ++ REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); ++ REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); ++ } ++ ++} ++ ++static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base) ++{ ++ enum dc_lut_mode mode; ++ uint32_t state_mode; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK, ++ CM_SHAPER_CONFIG_STATUS, &state_mode); ++ ++ switch (state_mode) { ++ case 0: ++ mode = LUT_BYPASS; ++ break; ++ case 1: ++ mode = LUT_RAM_A; ++ break; ++ case 2: ++ mode = LUT_RAM_B; ++ break; ++ default: ++ mode = LUT_BYPASS; ++ break; ++ } ++ return mode; ++} ++ ++static void dpp20_configure_shaper_lut( ++ struct dpp *dpp_base, ++ bool is_ram_a) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, ++ CM_SHAPER_LUT_WRITE_EN_MASK, 7); ++ REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, ++ CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); ++ REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); ++} ++ ++/*program shaper RAM A*/ ++ ++static void dpp20_program_shaper_luta_settings( ++ struct dpp *dpp_base, ++ const struct pwl_params *params) ++{ ++ const struct gamma_curve *curve; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, ++ CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, ++ CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); ++ REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, ++ CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, ++ CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0); ++ REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, ++ CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, ++ CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0); ++ ++ REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, ++ CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, ++ CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); ++ ++ REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, ++ CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, ++ CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); ++ ++ REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, ++ CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, ++ CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); ++ ++ curve = params->arr_curve_points; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, ++ CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, ++ CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, ++ CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, ++ CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, ++ CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, ++ CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, ++ CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, ++ CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, ++ CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, ++ CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0, ++ CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0, ++ CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0, ++ CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0, ++ CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0, ++ CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0, ++ CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0, ++ CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); ++} ++ ++/*program shaper RAM B*/ ++static void dpp20_program_shaper_lutb_settings( ++ struct dpp *dpp_base, ++ const struct pwl_params *params) ++{ ++ const struct gamma_curve *curve; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, ++ CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, ++ CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); ++ REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, ++ CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, ++ CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0); ++ REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, ++ CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, ++ CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0); ++ ++ REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, ++ CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, ++ CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); ++ ++ REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, ++ CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, ++ CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); ++ ++ REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, ++ CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, ++ CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); ++ ++ curve = params->arr_curve_points; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, ++ CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, ++ CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, ++ CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, ++ CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0, ++ CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0, ++ CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0, ++ CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0, ++ CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0, ++ CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0, ++ CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0, ++ CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0, ++ CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0, ++ CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0, ++ CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0, ++ CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0, ++ CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); ++ ++ curve += 2; ++ REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0, ++ CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, ++ CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, ++ CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, ++ CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); ++ ++} ++ ++ ++bool dpp20_program_shaper( ++ struct dpp *dpp_base, ++ const struct pwl_params *params) ++{ ++ enum dc_lut_mode current_mode; ++ enum dc_lut_mode next_mode; ++ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ if (params == NULL) { ++ REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); ++ return false; ++ } ++ current_mode = dpp20_get_shaper_current(dpp_base); ++ ++ if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) ++ next_mode = LUT_RAM_B; ++ else ++ next_mode = LUT_RAM_A; ++ ++ dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A ? true:false); ++ ++ if (next_mode == LUT_RAM_A) ++ dpp20_program_shaper_luta_settings(dpp_base, params); ++ else ++ dpp20_program_shaper_lutb_settings(dpp_base, params); ++ ++ dpp20_program_shaper_lut( ++ dpp_base, params->rgb_resulted, params->hw_points_num); ++ ++ REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); ++ ++ return true; ++ ++} ++ ++static enum dc_lut_mode get3dlut_config( ++ struct dpp *dpp_base, ++ bool *is_17x17x17, ++ bool *is_12bits_color_channel) ++{ ++ uint32_t i_mode, i_enable_10bits, lut_size; ++ enum dc_lut_mode mode; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL, ++ CM_3DLUT_CONFIG_STATUS, &i_mode, ++ CM_3DLUT_30BIT_EN, &i_enable_10bits); ++ ++ switch (i_mode) { ++ case 0: ++ mode = LUT_BYPASS; ++ break; ++ case 1: ++ mode = LUT_RAM_A; ++ break; ++ case 2: ++ mode = LUT_RAM_B; ++ break; ++ default: ++ mode = LUT_BYPASS; ++ break; ++ } ++ if (i_enable_10bits > 0) ++ *is_12bits_color_channel = false; ++ else ++ *is_12bits_color_channel = true; ++ ++ REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); ++ ++ if (lut_size == 0) ++ *is_17x17x17 = true; ++ else ++ *is_17x17x17 = false; ++ ++ return mode; ++} ++/* ++ * select ramA or ramB, or bypass ++ * select color channel size 10 or 12 bits ++ * select 3dlut size 17x17x17 or 9x9x9 ++ */ ++static void dpp20_set_3dlut_mode( ++ struct dpp *dpp_base, ++ enum dc_lut_mode mode, ++ bool is_color_channel_12bits, ++ bool is_lut_size17x17x17) ++{ ++ uint32_t lut_mode; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ if (mode == LUT_BYPASS) ++ lut_mode = 0; ++ else if (mode == LUT_RAM_A) ++ lut_mode = 1; ++ else ++ lut_mode = 2; ++ ++ REG_UPDATE_2(CM_3DLUT_MODE, ++ CM_3DLUT_MODE, lut_mode, ++ CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); ++} ++ ++static void dpp20_select_3dlut_ram( ++ struct dpp *dpp_base, ++ enum dc_lut_mode mode, ++ bool is_color_channel_12bits) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL, ++ CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, ++ CM_3DLUT_30BIT_EN, ++ is_color_channel_12bits == true ? 0:1); ++} ++ ++ ++ ++static void dpp20_set3dlut_ram12( ++ struct dpp *dpp_base, ++ const struct dc_rgb *lut, ++ uint32_t entries) ++{ ++ uint32_t i, red, green, blue, red1, green1, blue1; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ for (i = 0 ; i < entries; i += 2) { ++ red = lut[i].red<<4; ++ green = lut[i].green<<4; ++ blue = lut[i].blue<<4; ++ red1 = lut[i+1].red<<4; ++ green1 = lut[i+1].green<<4; ++ blue1 = lut[i+1].blue<<4; ++ ++ REG_SET_2(CM_3DLUT_DATA, 0, ++ CM_3DLUT_DATA0, red, ++ CM_3DLUT_DATA1, red1); ++ ++ REG_SET_2(CM_3DLUT_DATA, 0, ++ CM_3DLUT_DATA0, green, ++ CM_3DLUT_DATA1, green1); ++ ++ REG_SET_2(CM_3DLUT_DATA, 0, ++ CM_3DLUT_DATA0, blue, ++ CM_3DLUT_DATA1, blue1); ++ ++ } ++} ++ ++/* ++ * load selected lut with 10 bits color channels ++ */ ++static void dpp20_set3dlut_ram10( ++ struct dpp *dpp_base, ++ const struct dc_rgb *lut, ++ uint32_t entries) ++{ ++ uint32_t i, red, green, blue, value; ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ for (i = 0; i < entries; i++) { ++ red = lut[i].red; ++ green = lut[i].green; ++ blue = lut[i].blue; ++ ++ value = (red<<20) | (green<<10) | blue; ++ ++ REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); ++ } ++ ++} ++ ++ ++static void dpp20_select_3dlut_ram_mask( ++ struct dpp *dpp_base, ++ uint32_t ram_selection_mask) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, ++ ram_selection_mask); ++ REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); ++} ++ ++bool dpp20_program_3dlut( ++ struct dpp *dpp_base, ++ struct tetrahedral_params *params) ++{ ++ enum dc_lut_mode mode; ++ bool is_17x17x17; ++ bool is_12bits_color_channel; ++ struct dc_rgb *lut0; ++ struct dc_rgb *lut1; ++ struct dc_rgb *lut2; ++ struct dc_rgb *lut3; ++ int lut_size0; ++ int lut_size; ++ ++ if (params == NULL) { ++ dpp20_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); ++ return false; ++ } ++ mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); ++ ++ if (mode == LUT_BYPASS || mode == LUT_RAM_B) ++ mode = LUT_RAM_A; ++ else ++ mode = LUT_RAM_B; ++ ++ is_17x17x17 = !params->use_tetrahedral_9; ++ is_12bits_color_channel = params->use_12bits; ++ if (is_17x17x17) { ++ lut0 = params->tetrahedral_17.lut0; ++ lut1 = params->tetrahedral_17.lut1; ++ lut2 = params->tetrahedral_17.lut2; ++ lut3 = params->tetrahedral_17.lut3; ++ lut_size0 = sizeof(params->tetrahedral_17.lut0)/ ++ sizeof(params->tetrahedral_17.lut0[0]); ++ lut_size = sizeof(params->tetrahedral_17.lut1)/ ++ sizeof(params->tetrahedral_17.lut1[0]); ++ } else { ++ lut0 = params->tetrahedral_9.lut0; ++ lut1 = params->tetrahedral_9.lut1; ++ lut2 = params->tetrahedral_9.lut2; ++ lut3 = params->tetrahedral_9.lut3; ++ lut_size0 = sizeof(params->tetrahedral_9.lut0)/ ++ sizeof(params->tetrahedral_9.lut0[0]); ++ lut_size = sizeof(params->tetrahedral_9.lut1)/ ++ sizeof(params->tetrahedral_9.lut1[0]); ++ } ++ ++ dpp20_select_3dlut_ram(dpp_base, mode, ++ is_12bits_color_channel); ++ dpp20_select_3dlut_ram_mask(dpp_base, 0x1); ++ if (is_12bits_color_channel) ++ dpp20_set3dlut_ram12(dpp_base, lut0, lut_size0); ++ else ++ dpp20_set3dlut_ram10(dpp_base, lut0, lut_size0); ++ ++ dpp20_select_3dlut_ram_mask(dpp_base, 0x2); ++ if (is_12bits_color_channel) ++ dpp20_set3dlut_ram12(dpp_base, lut1, lut_size); ++ else ++ dpp20_set3dlut_ram10(dpp_base, lut1, lut_size); ++ ++ dpp20_select_3dlut_ram_mask(dpp_base, 0x4); ++ if (is_12bits_color_channel) ++ dpp20_set3dlut_ram12(dpp_base, lut2, lut_size); ++ else ++ dpp20_set3dlut_ram10(dpp_base, lut2, lut_size); ++ ++ dpp20_select_3dlut_ram_mask(dpp_base, 0x8); ++ if (is_12bits_color_channel) ++ dpp20_set3dlut_ram12(dpp_base, lut3, lut_size); ++ else ++ dpp20_set3dlut_ram10(dpp_base, lut3, lut_size); ++ ++ ++ dpp20_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, ++ is_17x17x17); ++ ++ return true; ++} ++ ++void dpp2_set_hdr_multiplier( ++ struct dpp *dpp_base, ++ uint32_t multiplier) ++{ ++ struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); ++ ++ REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier); ++} +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +index b55c5a2e56e2..60c671fcf186 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +@@ -36,7 +36,13 @@ struct dpp { + struct dpp_caps *caps; + struct pwl_params regamma_params; + struct pwl_params degamma_params; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ struct dpp_cursor_attributes cur_attr; ++#endif + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ struct pwl_params shaper_params; ++#endif + }; + + struct dpp_input_csc_matrix { +@@ -49,6 +55,34 @@ struct dpp_grph_csc_adjustment { + enum graphics_gamut_adjust_type gamut_adjust_type; + }; + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++struct cnv_color_keyer_params { ++ int color_keyer_en; ++ int color_keyer_mode; ++ int color_keyer_alpha_low; ++ int color_keyer_alpha_high; ++ int color_keyer_red_low; ++ int color_keyer_red_high; ++ int color_keyer_green_low; ++ int color_keyer_green_high; ++ int color_keyer_blue_low; ++ int color_keyer_blue_high; ++}; ++ ++/* new for dcn2: set the 8bit alpha values based on the 2 bit alpha ++ *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0 default: 0b00000000 ++ *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1 default: 0b01010101 ++ *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2 default: 0b10101010 ++ *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3 default: 0b11111111 ++ */ ++struct cnv_alpha_2bit_lut { ++ int lut0; ++ int lut1; ++ int lut2; ++ int lut3; ++}; ++#endif ++ + struct dcn_dpp_state { + uint32_t is_enabled; + uint32_t igam_lut_mode; +@@ -155,7 +189,12 @@ struct dpp_funcs { + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++ enum dc_color_space input_color_space, ++ struct cnv_alpha_2bit_lut *alpha_2bit_lut); ++#else + enum dc_color_space input_color_space); ++#endif + + void (*dpp_full_bypass)(struct dpp *dpp_base); + +@@ -184,6 +223,20 @@ struct dpp_funcs { + bool dppclk_div, + bool enable); + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ bool (*dpp_program_blnd_lut)( ++ struct dpp *dpp, ++ const struct pwl_params *params); ++ bool (*dpp_program_shaper_lut)( ++ struct dpp *dpp, ++ const struct pwl_params *params); ++ bool (*dpp_program_3dlut)( ++ struct dpp *dpp, ++ struct tetrahedral_params *params); ++ void (*dpp_cnv_set_alpha_keyer)( ++ struct dpp *dpp_base, ++ struct cnv_color_keyer_params *color_keyer); ++#endif + }; + + +-- +2.17.1 + |