diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2431-drm-amd-display-Add-GPIO-support-for-DCN2.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2431-drm-amd-display-Add-GPIO-support-for-DCN2.patch | 919 |
1 files changed, 919 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2431-drm-amd-display-Add-GPIO-support-for-DCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2431-drm-amd-display-Add-GPIO-support-for-DCN2.patch new file mode 100644 index 00000000..7410d277 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2431-drm-amd-display-Add-GPIO-support-for-DCN2.patch @@ -0,0 +1,919 @@ +From b3b58e5a7548e6b3bb1f16825866250cd3be3c74 Mon Sep 17 00:00:00 2001 +From: Harry Wentland <harry.wentland@amd.com> +Date: Fri, 22 Feb 2019 09:45:07 -0500 +Subject: [PATCH 2431/2940] drm/amd/display: Add GPIO support for DCN2 + +Adding support to program GPIO HW block of DCN2 + +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 + + .../display/dc/gpio/dcn20/hw_factory_dcn20.c | 212 ++++++++++ + .../display/dc/gpio/dcn20/hw_factory_dcn20.h | 33 ++ + .../dc/gpio/dcn20/hw_translate_dcn20.c | 382 ++++++++++++++++++ + .../dc/gpio/dcn20/hw_translate_dcn20.h | 35 ++ + .../gpu/drm/amd/display/dc/gpio/ddc_regs.h | 53 +++ + drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 15 + + .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 + + .../drm/amd/display/dc/gpio/hw_translate.c | 9 + + 9 files changed, 759 insertions(+) + create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c + create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h + create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c + create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h + +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile +index 562ee189d780..c3d92878875d 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile +@@ -69,6 +69,17 @@ AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10)) + AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10) + endif + ++############################################################################### ++# DCN 2 ++############################################################################### ++ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++GPIO_DCN20 = hw_translate_dcn20.o hw_factory_dcn20.o ++ ++AMD_DAL_GPIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn20/,$(GPIO_DCN20)) ++ ++AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN20) ++endif ++ + ############################################################################### + # Diagnostics on FPGA + ############################################################################### +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c +new file mode 100644 +index 000000000000..abd76d855375 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c +@@ -0,0 +1,212 @@ ++/* ++ * Copyright 2013-15 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#include "dm_services.h" ++#include "include/gpio_types.h" ++#include "../hw_factory.h" ++ ++ ++#include "../hw_gpio.h" ++#include "../hw_ddc.h" ++#include "../hw_hpd.h" ++ ++#include "hw_factory_dcn20.h" ++ ++ ++#include "dcn/dcn_2_0_0_offset.h" ++#include "dcn/dcn_2_0_0_sh_mask.h" ++#include "navi10_ip_offset.h" ++ ++ ++#include "reg_helper.h" ++#include "../hpd_regs.h" ++/* begin ********************* ++ * macros to expend register list macro defined in HW object header file */ ++ ++/* DCN */ ++#define block HPD ++#define reg_num 0 ++ ++#undef BASE_INNER ++#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ++ ++#define BASE(seg) BASE_INNER(seg) ++ ++ ++ ++#define REG(reg_name)\ ++ BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name ++ ++#define SF_HPD(reg_name, field_name, post_fix)\ ++ .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix ++ ++#define REGI(reg_name, block, id)\ ++ BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ ++ mm ## block ## id ## _ ## reg_name ++ ++#define SF(reg_name, field_name, post_fix)\ ++ .field_name = reg_name ## __ ## field_name ## post_fix ++ ++/* macros to expend register list macro defined in HW object header file ++ * end *********************/ ++ ++ ++ ++#define hpd_regs(id) \ ++{\ ++ HPD_REG_LIST(id)\ ++} ++ ++static const struct hpd_registers hpd_regs[] = { ++ hpd_regs(0), ++ hpd_regs(1), ++ hpd_regs(2), ++ hpd_regs(3), ++ hpd_regs(4), ++ hpd_regs(5), ++}; ++ ++static const struct hpd_sh_mask hpd_shift = { ++ HPD_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct hpd_sh_mask hpd_mask = { ++ HPD_MASK_SH_LIST(_MASK) ++}; ++ ++#include "../ddc_regs.h" ++ ++ /* set field name */ ++#define SF_DDC(reg_name, field_name, post_fix)\ ++ .field_name = reg_name ## __ ## field_name ## post_fix ++ ++static const struct ddc_registers ddc_data_regs_dcn[] = { ++ ddc_data_regs_dcn2(1), ++ ddc_data_regs_dcn2(2), ++ ddc_data_regs_dcn2(3), ++ ddc_data_regs_dcn2(4), ++ ddc_data_regs_dcn2(5), ++ ddc_data_regs_dcn2(6), ++}; ++ ++static const struct ddc_registers ddc_clk_regs_dcn[] = { ++ ddc_clk_regs_dcn2(1), ++ ddc_clk_regs_dcn2(2), ++ ddc_clk_regs_dcn2(3), ++ ddc_clk_regs_dcn2(4), ++ ddc_clk_regs_dcn2(5), ++ ddc_clk_regs_dcn2(6), ++}; ++ ++static const struct ddc_sh_mask ddc_shift[] = { ++ DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), ++ DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), ++ DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), ++ DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), ++ DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), ++ DDC_MASK_SH_LIST_DCN2(__SHIFT, 6) ++}; ++ ++static const struct ddc_sh_mask ddc_mask[] = { ++ DDC_MASK_SH_LIST_DCN2(_MASK, 1), ++ DDC_MASK_SH_LIST_DCN2(_MASK, 2), ++ DDC_MASK_SH_LIST_DCN2(_MASK, 3), ++ DDC_MASK_SH_LIST_DCN2(_MASK, 4), ++ DDC_MASK_SH_LIST_DCN2(_MASK, 5), ++ DDC_MASK_SH_LIST_DCN2(_MASK, 6) ++}; ++ ++static void define_ddc_registers( ++ struct hw_gpio_pin *pin, ++ uint32_t en) ++{ ++ struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); ++ ++ switch (pin->id) { ++ case GPIO_ID_DDC_DATA: ++ ddc->regs = &ddc_data_regs_dcn[en]; ++ ddc->base.regs = &ddc_data_regs_dcn[en].gpio; ++ break; ++ case GPIO_ID_DDC_CLOCK: ++ ddc->regs = &ddc_clk_regs_dcn[en]; ++ ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; ++ break; ++ default: ++ ASSERT_CRITICAL(false); ++ return; ++ } ++ ++ ddc->shifts = &ddc_shift[en]; ++ ddc->masks = &ddc_mask[en]; ++ ++} ++ ++static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) ++{ ++ struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); ++ ++ hpd->regs = &hpd_regs[en]; ++ hpd->shifts = &hpd_shift; ++ hpd->masks = &hpd_mask; ++ hpd->base.regs = &hpd_regs[en].gpio; ++} ++ ++ ++/* fucntion table */ ++static const struct hw_factory_funcs funcs = { ++ .create_ddc_data = dal_hw_ddc_create, ++ .create_ddc_clock = dal_hw_ddc_create, ++ .create_generic = NULL, ++ .create_hpd = dal_hw_hpd_create, ++ .create_sync = NULL, ++ .create_gsl = NULL, ++ .define_hpd_registers = define_hpd_registers, ++ .define_ddc_registers = define_ddc_registers ++}; ++/* ++ * dal_hw_factory_dcn10_init ++ * ++ * @brief ++ * Initialize HW factory function pointers and pin info ++ * ++ * @param ++ * struct hw_factory *factory - [out] struct of function pointers ++ */ ++void dal_hw_factory_dcn20_init(struct hw_factory *factory) ++{ ++ /*TODO check ASIC CAPs*/ ++ factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; ++ factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; ++ factory->number_of_pins[GPIO_ID_GENERIC] = 4; ++ factory->number_of_pins[GPIO_ID_HPD] = 6; ++ factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; ++ factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; ++ factory->number_of_pins[GPIO_ID_SYNC] = 0; ++ factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ ++ ++ factory->funcs = &funcs; ++} ++ ++#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h +new file mode 100644 +index 000000000000..43a4ce7aa3bf +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h +@@ -0,0 +1,33 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#ifndef __DAL_HW_FACTORY_DCN20_H__ ++#define __DAL_HW_FACTORY_DCN20_H__ ++ ++/* Initialize HW factory function pointers and pin info */ ++void dal_hw_factory_dcn20_init(struct hw_factory *factory); ++ ++#endif /* __DAL_HW_FACTORY_DCN20_H__ */ ++#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c +new file mode 100644 +index 000000000000..b393cc13298a +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c +@@ -0,0 +1,382 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++ ++/* ++ * Pre-requisites: headers required by header of this unit ++ */ ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#include "hw_translate_dcn20.h" ++ ++#include "dm_services.h" ++#include "include/gpio_types.h" ++#include "../hw_translate.h" ++ ++#include "dcn/dcn_1_0_offset.h" ++#include "dcn/dcn_1_0_sh_mask.h" ++#include "soc15_hw_ip.h" ++#include "vega10_ip_offset.h" ++ ++ ++ ++/* begin ********************* ++ * macros to expend register list macro defined in HW object header file */ ++ ++/* DCN */ ++#define block HPD ++#define reg_num 0 ++ ++#undef BASE_INNER ++#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg ++ ++#define BASE(seg) BASE_INNER(seg) ++ ++#undef REG ++#define REG(reg_name)\ ++ BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name ++#define SF_HPD(reg_name, field_name, post_fix)\ ++ .field_name = reg_name ## __ ## field_name ## post_fix ++ ++ ++/* macros to expend register list macro defined in HW object header file ++ * end *********************/ ++ ++ ++static bool offset_to_id( ++ uint32_t offset, ++ uint32_t mask, ++ enum gpio_id *id, ++ uint32_t *en) ++{ ++ switch (offset) { ++ /* GENERIC */ ++ case REG(DC_GENERICA): ++ *id = GPIO_ID_GENERIC; ++ switch (mask) { ++ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: ++ *en = GPIO_GENERIC_A; ++ return true; ++ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK: ++ *en = GPIO_GENERIC_B; ++ return true; ++ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK: ++ *en = GPIO_GENERIC_C; ++ return true; ++ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK: ++ *en = GPIO_GENERIC_D; ++ return true; ++ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK: ++ *en = GPIO_GENERIC_E; ++ return true; ++ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK: ++ *en = GPIO_GENERIC_F; ++ return true; ++ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK: ++ *en = GPIO_GENERIC_G; ++ return true; ++ default: ++ ASSERT_CRITICAL(false); ++ return false; ++ } ++ break; ++ /* HPD */ ++ case REG(DC_GPIO_HPD_A): ++ *id = GPIO_ID_HPD; ++ switch (mask) { ++ case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK: ++ *en = GPIO_HPD_1; ++ return true; ++ case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK: ++ *en = GPIO_HPD_2; ++ return true; ++ case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK: ++ *en = GPIO_HPD_3; ++ return true; ++ case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK: ++ *en = GPIO_HPD_4; ++ return true; ++ case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK: ++ *en = GPIO_HPD_5; ++ return true; ++ case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK: ++ *en = GPIO_HPD_6; ++ return true; ++ default: ++ ASSERT_CRITICAL(false); ++ return false; ++ } ++ break; ++ /* REG(DC_GPIO_GENLK_MASK */ ++ case REG(DC_GPIO_GENLK_A): ++ *id = GPIO_ID_GSL; ++ switch (mask) { ++ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK: ++ *en = GPIO_GSL_GENLOCK_CLOCK; ++ return true; ++ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK: ++ *en = GPIO_GSL_GENLOCK_VSYNC; ++ return true; ++ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK: ++ *en = GPIO_GSL_SWAPLOCK_A; ++ return true; ++ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK: ++ *en = GPIO_GSL_SWAPLOCK_B; ++ return true; ++ default: ++ ASSERT_CRITICAL(false); ++ return false; ++ } ++ break; ++ /* DDC */ ++ /* we don't care about the GPIO_ID for DDC ++ * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK ++ * directly in the create method */ ++ case REG(DC_GPIO_DDC1_A): ++ *en = GPIO_DDC_LINE_DDC1; ++ return true; ++ case REG(DC_GPIO_DDC2_A): ++ *en = GPIO_DDC_LINE_DDC2; ++ return true; ++ case REG(DC_GPIO_DDC3_A): ++ *en = GPIO_DDC_LINE_DDC3; ++ return true; ++ case REG(DC_GPIO_DDC4_A): ++ *en = GPIO_DDC_LINE_DDC4; ++ return true; ++ case REG(DC_GPIO_DDC5_A): ++ *en = GPIO_DDC_LINE_DDC5; ++ return true; ++ case REG(DC_GPIO_DDC6_A): ++ *en = GPIO_DDC_LINE_DDC6; ++ return true; ++ case REG(DC_GPIO_DDCVGA_A): ++ *en = GPIO_DDC_LINE_DDC_VGA; ++ return true; ++ ++// case REG(DC_GPIO_I2CPAD_A): not exit ++// case REG(DC_GPIO_PWRSEQ_A): ++// case REG(DC_GPIO_PAD_STRENGTH_1): ++// case REG(DC_GPIO_PAD_STRENGTH_2): ++// case REG(DC_GPIO_DEBUG): ++ /* UNEXPECTED */ ++ default: ++// case REG(DC_GPIO_SYNCA_A): not exist ++ ASSERT_CRITICAL(false); ++ return false; ++ } ++} ++ ++static bool id_to_offset( ++ enum gpio_id id, ++ uint32_t en, ++ struct gpio_pin_info *info) ++{ ++ bool result = true; ++ ++ switch (id) { ++ case GPIO_ID_DDC_DATA: ++ info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; ++ switch (en) { ++ case GPIO_DDC_LINE_DDC1: ++ info->offset = REG(DC_GPIO_DDC1_A); ++ break; ++ case GPIO_DDC_LINE_DDC2: ++ info->offset = REG(DC_GPIO_DDC2_A); ++ break; ++ case GPIO_DDC_LINE_DDC3: ++ info->offset = REG(DC_GPIO_DDC3_A); ++ break; ++ case GPIO_DDC_LINE_DDC4: ++ info->offset = REG(DC_GPIO_DDC4_A); ++ break; ++ case GPIO_DDC_LINE_DDC5: ++ info->offset = REG(DC_GPIO_DDC5_A); ++ break; ++ case GPIO_DDC_LINE_DDC6: ++ info->offset = REG(DC_GPIO_DDC6_A); ++ break; ++ case GPIO_DDC_LINE_DDC_VGA: ++ info->offset = REG(DC_GPIO_DDCVGA_A); ++ break; ++ case GPIO_DDC_LINE_I2C_PAD: ++ default: ++ ASSERT_CRITICAL(false); ++ result = false; ++ } ++ break; ++ case GPIO_ID_DDC_CLOCK: ++ info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; ++ switch (en) { ++ case GPIO_DDC_LINE_DDC1: ++ info->offset = REG(DC_GPIO_DDC1_A); ++ break; ++ case GPIO_DDC_LINE_DDC2: ++ info->offset = REG(DC_GPIO_DDC2_A); ++ break; ++ case GPIO_DDC_LINE_DDC3: ++ info->offset = REG(DC_GPIO_DDC3_A); ++ break; ++ case GPIO_DDC_LINE_DDC4: ++ info->offset = REG(DC_GPIO_DDC4_A); ++ break; ++ case GPIO_DDC_LINE_DDC5: ++ info->offset = REG(DC_GPIO_DDC5_A); ++ break; ++ case GPIO_DDC_LINE_DDC6: ++ info->offset = REG(DC_GPIO_DDC6_A); ++ break; ++ case GPIO_DDC_LINE_DDC_VGA: ++ info->offset = REG(DC_GPIO_DDCVGA_A); ++ break; ++ case GPIO_DDC_LINE_I2C_PAD: ++ default: ++ ASSERT_CRITICAL(false); ++ result = false; ++ } ++ break; ++ case GPIO_ID_GENERIC: ++ info->offset = REG(DC_GPIO_GENERIC_A); ++ switch (en) { ++ case GPIO_GENERIC_A: ++ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; ++ break; ++ case GPIO_GENERIC_B: ++ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; ++ break; ++ case GPIO_GENERIC_C: ++ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; ++ break; ++ case GPIO_GENERIC_D: ++ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; ++ break; ++ case GPIO_GENERIC_E: ++ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; ++ break; ++ case GPIO_GENERIC_F: ++ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; ++ break; ++ case GPIO_GENERIC_G: ++ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; ++ break; ++ default: ++ ASSERT_CRITICAL(false); ++ result = false; ++ } ++ break; ++ case GPIO_ID_HPD: ++ info->offset = REG(DC_GPIO_HPD_A); ++ switch (en) { ++ case GPIO_HPD_1: ++ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; ++ break; ++ case GPIO_HPD_2: ++ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; ++ break; ++ case GPIO_HPD_3: ++ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; ++ break; ++ case GPIO_HPD_4: ++ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; ++ break; ++ case GPIO_HPD_5: ++ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; ++ break; ++ case GPIO_HPD_6: ++ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; ++ break; ++ default: ++ ASSERT_CRITICAL(false); ++ result = false; ++ } ++ break; ++ case GPIO_ID_GSL: ++ switch (en) { ++ case GPIO_GSL_GENLOCK_CLOCK: ++ /*not implmented*/ ++ ASSERT_CRITICAL(false); ++ result = false; ++ break; ++ case GPIO_GSL_GENLOCK_VSYNC: ++ /*not implmented*/ ++ ASSERT_CRITICAL(false); ++ result = false; ++ break; ++ case GPIO_GSL_SWAPLOCK_A: ++ /*not implmented*/ ++ ASSERT_CRITICAL(false); ++ result = false; ++ break; ++ case GPIO_GSL_SWAPLOCK_B: ++ /*not implmented*/ ++ ASSERT_CRITICAL(false); ++ result = false; ++ ++ break; ++ default: ++ ASSERT_CRITICAL(false); ++ result = false; ++ } ++ break; ++ case GPIO_ID_SYNC: ++ case GPIO_ID_VIP_PAD: ++ default: ++ ASSERT_CRITICAL(false); ++ result = false; ++ } ++ ++ if (result) { ++ info->offset_y = info->offset + 2; ++ info->offset_en = info->offset + 1; ++ info->offset_mask = info->offset - 1; ++ ++ info->mask_y = info->mask; ++ info->mask_en = info->mask; ++ info->mask_mask = info->mask; ++ } ++ ++ return result; ++} ++ ++/* function table */ ++static const struct hw_translate_funcs funcs = { ++ .offset_to_id = offset_to_id, ++ .id_to_offset = id_to_offset, ++}; ++ ++/* ++ * dal_hw_translate_dcn10_init ++ * ++ * @brief ++ * Initialize Hw translate function pointers. ++ * ++ * @param ++ * struct hw_translate *tr - [out] struct of function pointers ++ * ++ */ ++void dal_hw_translate_dcn20_init(struct hw_translate *tr) ++{ ++ tr->funcs = &funcs; ++} ++ ++#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h +new file mode 100644 +index 000000000000..01f52c7bed86 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h +@@ -0,0 +1,35 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: AMD ++ * ++ */ ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#ifndef __DAL_HW_TRANSLATE_DCN20_H__ ++#define __DAL_HW_TRANSLATE_DCN20_H__ ++ ++struct hw_translate; ++ ++/* Initialize Hw translate function pointers */ ++void dal_hw_translate_dcn20_init(struct hw_translate *tr); ++ ++#endif /* __DAL_HW_TRANSLATE_DCN20_H__ */ ++#endif +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h +index bf40725f982f..f91e85b04956 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h ++++ b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h +@@ -48,6 +48,14 @@ + DDC_GPIO_REG_LIST(cd,id),\ + .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ #define DDC_REG_LIST_DCN2(cd, id) \ ++ DDC_GPIO_REG_LIST(cd, id),\ ++ .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ ++ .phy_aux_cntl = REG(PHY_AUX_CNTL), \ ++ .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) ++#endif ++ + #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\ + .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ + .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ +@@ -82,6 +90,13 @@ + DDC_GPIO_I2C_REG_LIST(cd),\ + .ddc_setup = 0 + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#define DDC_I2C_REG_LIST_DCN2(cd) \ ++ DDC_GPIO_I2C_REG_LIST(cd),\ ++ .ddc_setup = 0,\ ++ .phy_aux_cntl = REG(PHY_AUX_CNTL), \ ++ .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) ++#endif + #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ + SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ + SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ +@@ -95,10 +110,22 @@ + SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ + SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \ ++ {DDC_MASK_SH_LIST_COMMON(mask_sh),\ ++ 0,\ ++ 0,\ ++ (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\ ++ (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)} ++#endif + + struct ddc_registers { + struct gpio_registers gpio; + uint32_t ddc_setup; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ uint32_t phy_aux_cntl; ++ uint32_t dc_gpio_aux_ctrl_5; ++#endif + }; + + struct ddc_sh_mask { +@@ -113,6 +140,11 @@ struct ddc_sh_mask { + /* i2cpad_mask */ + uint32_t DC_GPIO_SDA_PD_DIS; + uint32_t DC_GPIO_SCL_PD_DIS; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ //phy_aux_cntl ++ uint32_t AUX_PAD_RXSEL; ++ uint32_t DDC_PAD_I2CMODE; ++#endif + }; + + +@@ -148,6 +180,27 @@ struct ddc_sh_mask { + {\ + DDC_I2C_REG_LIST(SCL)\ + } ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#define ddc_data_regs_dcn2(id) \ ++{\ ++ DDC_REG_LIST_DCN2(DATA, id)\ ++} ++ ++#define ddc_clk_regs_dcn2(id) \ ++{\ ++ DDC_REG_LIST_DCN2(CLK, id)\ ++} ++ ++#define ddc_i2c_data_regs_dcn2 \ ++{\ ++ DDC_I2C_REG_LIST_DCN2(SDA)\ ++} ++ ++#define ddc_i2c_clk_regs_dcn2 \ ++{\ ++ DDC_REG_LIST_DCN2(SCL)\ ++} ++#endif + + + #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +index 310f48965b27..49a99248e7f6 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +@@ -144,6 +144,15 @@ static enum gpio_result set_config( + AUX_PAD1_MODE, 0); + } + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { ++ REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1); ++ } ++ //set DC_IO_aux_rxsel = 2'b01 ++ if (ddc->regs->phy_aux_cntl != 0) { ++ REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1); ++ } ++#endif + return GPIO_RESULT_OK; + case GPIO_DDC_CONFIG_TYPE_MODE_AUX: + /* set the AUX pad mode */ +@@ -151,6 +160,12 @@ static enum gpio_result set_config( + REG_SET(gpio.MASK_reg, regval, + AUX_PAD1_MODE, 1); + } ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { ++ REG_UPDATE(dc_gpio_aux_ctrl_5, ++ DDC_PAD_I2CMODE, 0); ++ } ++#endif + + return GPIO_RESULT_OK; + case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +index a610fae16280..f90205bfbe76 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +@@ -46,6 +46,9 @@ + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/hw_factory_dcn10.h" + #endif ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#include "dcn20/hw_factory_dcn20.h" ++#endif + + #include "diagnostics/hw_factory_diag.h" + +@@ -89,6 +92,12 @@ bool dal_hw_factory_init( + return true; + #endif + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ case DCN_VERSION_2_0: ++ dal_hw_factory_dcn20_init(factory); ++ return true; ++#endif ++ + default: + ASSERT_CRITICAL(false); + return false; +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +index 1f9833dc8cfe..c35fe201d335 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +@@ -46,6 +46,9 @@ + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/hw_translate_dcn10.h" + #endif ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#include "dcn20/hw_translate_dcn20.h" ++#endif + + #include "diagnostics/hw_translate_diag.h" + +@@ -86,6 +89,12 @@ bool dal_hw_translate_init( + return true; + #endif + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ case DCN_VERSION_2_0: ++ dal_hw_translate_dcn20_init(translate); ++ return true; ++#endif ++ + default: + BREAK_TO_DEBUGGER(); + return false; +-- +2.17.1 + |