diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2430-drm-amd-display-add-AUX-and-I2C-for-DCN2.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2430-drm-amd-display-add-AUX-and-I2C-for-DCN2.patch | 143 |
1 files changed, 143 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2430-drm-amd-display-add-AUX-and-I2C-for-DCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2430-drm-amd-display-add-AUX-and-I2C-for-DCN2.patch new file mode 100644 index 00000000..434e1fea --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2430-drm-amd-display-add-AUX-and-I2C-for-DCN2.patch @@ -0,0 +1,143 @@ +From ad13f69256727e751977dc09d89cfb0fee17e1ed Mon Sep 17 00:00:00 2001 +From: Harry Wentland <harry.wentland@amd.com> +Date: Tue, 7 May 2019 14:47:35 -0500 +Subject: [PATCH 2430/2940] drm/amd/display: add AUX and I2C for DCN2 + +Adding support to program DCN2 AUX and I2C HW. + +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 10 ++++++ + .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 32 +++++++++++++++++++ + .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 22 +++++++++++++ + 3 files changed, 64 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +index ce6a26d189b0..ed7fec8fe253 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +@@ -29,6 +29,16 @@ + #include "i2caux_interface.h" + #include "inc/hw/aux_engine.h" + ++#ifdef CONFIG_DRM_AMD_DC_DCN2_0 ++#define AUX_COMMON_REG_LIST0(id)\ ++ SRI(AUX_CONTROL, DP_AUX, id), \ ++ SRI(AUX_ARB_CONTROL, DP_AUX, id), \ ++ SRI(AUX_SW_DATA, DP_AUX, id), \ ++ SRI(AUX_SW_CONTROL, DP_AUX, id), \ ++ SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ ++ SRI(AUX_SW_STATUS, DP_AUX, id) ++#endif ++ + #define AUX_COMMON_REG_LIST(id)\ + SRI(AUX_CONTROL, DP_AUX, id), \ + SRI(AUX_ARB_CONTROL, DP_AUX, id), \ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +index 7f2460caa2a6..d658b862430a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +@@ -303,6 +303,10 @@ static bool setup_engine( + struct dce_i2c_hw *dce_i2c_hw) + { + uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ uint32_t reset_length = 0; ++#endif ++ + /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ + REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); + +@@ -323,6 +327,14 @@ static bool setup_engine( + REG_UPDATE_N(SETUP, 2, + FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, + FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ } else { ++ reset_length = dce_i2c_hw->send_reset_length; ++ REG_UPDATE_N(SETUP, 3, ++ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, ++ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length, ++ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); ++#endif + } + /* Program HW priority + * set to High - interrupt software I2C at any time +@@ -698,3 +710,23 @@ void dcn1_i2c_hw_construct( + dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN; + } + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++void dcn2_i2c_hw_construct( ++ struct dce_i2c_hw *dce_i2c_hw, ++ struct dc_context *ctx, ++ uint32_t engine_id, ++ const struct dce_i2c_registers *regs, ++ const struct dce_i2c_shift *shifts, ++ const struct dce_i2c_mask *masks) ++{ ++ dcn1_i2c_hw_construct(dce_i2c_hw, ++ ctx, ++ engine_id, ++ regs, ++ shifts, ++ masks); ++ dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9; ++ if (ctx->dc->debug.scl_reset_length10) ++ dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10; ++} ++#endif +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h +index a633632f625b..cb0234e5d597 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h +@@ -177,6 +177,9 @@ struct dce_i2c_shift { + uint8_t DC_I2C_INDEX; + uint8_t DC_I2C_INDEX_WRITE; + uint8_t XTAL_REF_DIV; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH; ++#endif + uint8_t DC_I2C_REG_RW_CNTL_STATUS; + }; + +@@ -217,9 +220,18 @@ struct dce_i2c_mask { + uint32_t DC_I2C_INDEX; + uint32_t DC_I2C_INDEX_WRITE; + uint32_t XTAL_REF_DIV; ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++ uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH; ++#endif + uint32_t DC_I2C_REG_RW_CNTL_STATUS; + }; + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++#define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\ ++ I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\ ++ I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh) ++#endif ++ + struct dce_i2c_registers { + uint32_t SETUP; + uint32_t SPEED; +@@ -300,6 +312,16 @@ void dcn1_i2c_hw_construct( + const struct dce_i2c_shift *shifts, + const struct dce_i2c_mask *masks); + ++#if defined(CONFIG_DRM_AMD_DC_DCN2_0) ++void dcn2_i2c_hw_construct( ++ struct dce_i2c_hw *dce_i2c_hw, ++ struct dc_context *ctx, ++ uint32_t engine_id, ++ const struct dce_i2c_registers *regs, ++ const struct dce_i2c_shift *shifts, ++ const struct dce_i2c_mask *masks); ++#endif ++ + bool dce_i2c_submit_command_hw( + struct resource_pool *pool, + struct ddc *ddc, +-- +2.17.1 + |