diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2413-drm-amdgpu-VCN-implement-indirect-DPG-SRAM-mode.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2413-drm-amdgpu-VCN-implement-indirect-DPG-SRAM-mode.patch | 149 |
1 files changed, 149 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2413-drm-amdgpu-VCN-implement-indirect-DPG-SRAM-mode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2413-drm-amdgpu-VCN-implement-indirect-DPG-SRAM-mode.patch new file mode 100644 index 00000000..68875831 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2413-drm-amdgpu-VCN-implement-indirect-DPG-SRAM-mode.patch @@ -0,0 +1,149 @@ +From d71a109426a619f09caed96cb1f7916b88cae03f Mon Sep 17 00:00:00 2001 +From: Leo Liu <leo.liu@amd.com> +Date: Mon, 27 May 2019 10:46:25 -0400 +Subject: [PATCH 2413/2940] drm/amdgpu/VCN: implement indirect DPG SRAM mode + +SRAM will be programmed by PSP + +Signed-off-by: Leo Liu <leo.liu@amd.com> +Reviewed-by: James Zhu <James.Zhu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 3 ++ + drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 69 ++++++++++++++++++------- + 2 files changed, 53 insertions(+), 19 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +index 762cffeaf301..99f14fcc1460 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +@@ -111,6 +111,9 @@ + (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \ + mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \ + offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \ ++ } else { \ ++ *adev->vcn.dpg_sram_curr_addr++ = offset; \ ++ *adev->vcn.dpg_sram_curr_addr++ = value; \ + } \ + } while (0) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +index bef20704e2b9..77f4c631afa0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +@@ -28,6 +28,7 @@ + #include "soc15.h" + #include "soc15d.h" + #include "amdgpu_pm.h" ++#include "amdgpu_psp.h" + + #include "vcn/vcn_2_0_0_offset.h" + #include "vcn/vcn_2_0_0_sh_mask.h" +@@ -407,14 +408,23 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec + + /* cache window 0: fw */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { +- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), +- (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); +- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), +- (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); +- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +- UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); ++ if (!indirect) { ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), ++ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), ++ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); ++ } else { ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); ++ } + offset = 0; + } else { + WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +@@ -429,18 +439,31 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec + AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); + } + +- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +- UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); ++ if (!indirect) ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); ++ else ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); + + /* cache window 1: stack */ +- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), +- lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); +- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), +- upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); +- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( +- UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); ++ if (!indirect) { ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), ++ lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), ++ upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); ++ } else { ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); ++ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( ++ UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); ++ } + WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( + UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); + +@@ -911,6 +934,9 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) + tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); + ++ if (indirect) ++ adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr; ++ + /* enable clock gating */ + vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect); + +@@ -982,6 +1008,11 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) + UVD, 0, mmUVD_MASTINT_EN), + UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); + ++ if (indirect) ++ psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr, ++ (uint32_t)((uint64_t)adev->vcn.dpg_sram_curr_addr - ++ (uint64_t)adev->vcn.dpg_sram_cpu_addr)); ++ + /* force RBC into idle state */ + rb_bufsz = order_base_2(ring->ring_size); + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); +@@ -1027,7 +1058,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev) + amdgpu_dpm_enable_uvd(adev, true); + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { +- r = vcn_v2_0_start_dpg_mode(adev, 0); ++ r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); + if (r) + return r; + goto jpeg; +-- +2.17.1 + |