diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2297-drm-amd-powerplay-move-Watermarks_t-uses-into-asic-l.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2297-drm-amd-powerplay-move-Watermarks_t-uses-into-asic-l.patch | 209 |
1 files changed, 209 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2297-drm-amd-powerplay-move-Watermarks_t-uses-into-asic-l.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2297-drm-amd-powerplay-move-Watermarks_t-uses-into-asic-l.patch new file mode 100644 index 00000000..c2f80f62 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2297-drm-amd-powerplay-move-Watermarks_t-uses-into-asic-l.patch @@ -0,0 +1,209 @@ +From f39ea3c7e92446755bb17021f1a7804114e61dc0 Mon Sep 17 00:00:00 2001 +From: Huang Rui <ray.huang@amd.com> +Date: Sun, 31 Mar 2019 15:15:49 +0800 +Subject: [PATCH 2297/2940] drm/amd/powerplay: move Watermarks_t uses into asic + level + +This patch moves the rest of Watermarks_t uses into asic level. It's to avoid +the conflicts with different asic. + +Signed-off-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Kevin Wang <kevin1.wang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++ + drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 63 +------------------ + drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 61 ++++++++++++++++++ + 3 files changed, 67 insertions(+), 61 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index 7fa03eca4a08..469b2c9e6805 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -575,6 +575,8 @@ struct pptable_funcs { + int (*get_current_activity_percent)(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value); ++ int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, ++ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); + }; + + struct smu_funcs +@@ -863,6 +865,8 @@ struct smu_funcs + ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL) + #define smu_get_ppfeature_status(smu, buf) \ + ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL) ++#define smu_set_watermarks_table(smu, tab, clock_ranges) \ ++ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0) + + extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, + uint16_t *size, uint8_t *frev, uint8_t *crev, +diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +index 103e8bc3a7b9..4620bd578bcd 100644 +--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c ++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +@@ -1401,65 +1401,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu, + return ret; + } + +-static int smu_v11_0_set_watermarks_table(struct smu_context *smu, +- Watermarks_t *table, struct +- dm_pp_wm_sets_with_clock_ranges_soc15 +- *clock_ranges) +-{ +- int i; +- +- if (!table || !clock_ranges) +- return -EINVAL; +- +- if (clock_ranges->num_wm_dmif_sets > 4 || +- clock_ranges->num_wm_mcif_sets > 4) +- return -EINVAL; +- +- for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { +- table->WatermarkRow[1][i].MinClock = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / +- 1000)); +- table->WatermarkRow[1][i].MaxClock = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / +- 1000)); +- table->WatermarkRow[1][i].MinUclk = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / +- 1000)); +- table->WatermarkRow[1][i].MaxUclk = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / +- 1000)); +- table->WatermarkRow[1][i].WmSetting = (uint8_t) +- clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; +- } +- +- for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) { +- table->WatermarkRow[0][i].MinClock = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / +- 1000)); +- table->WatermarkRow[0][i].MaxClock = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / +- 1000)); +- table->WatermarkRow[0][i].MinUclk = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz / +- 1000)); +- table->WatermarkRow[0][i].MaxUclk = +- cpu_to_le16((uint16_t) +- (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / +- 1000)); +- table->WatermarkRow[0][i].WmSetting = (uint8_t) +- clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; +- } +- +- return 0; +-} +- + static int + smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct + dm_pp_wm_sets_with_clock_ranges_soc15 +@@ -1467,12 +1408,12 @@ smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct + { + int ret = 0; + struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS]; +- Watermarks_t *table = watermarks->cpu_addr; ++ void *table = watermarks->cpu_addr; + + if (!smu->disable_watermark && + smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && + smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { +- smu_v11_0_set_watermarks_table(smu, table, clock_ranges); ++ smu_set_watermarks_table(smu, table, clock_ranges); + smu->watermarks_bitmap |= WATERMARKS_EXIST; + smu->watermarks_bitmap &= ~WATERMARKS_LOADED; + } +diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +index 75c86c4b2ece..ba0175ae247a 100644 +--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c ++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +@@ -3035,6 +3035,66 @@ static int vega20_get_current_activity_percent(struct smu_context *smu, + return 0; + } + ++static int vega20_set_watermarks_table(struct smu_context *smu, ++ void *watermarks, struct ++ dm_pp_wm_sets_with_clock_ranges_soc15 ++ *clock_ranges) ++{ ++ int i; ++ Watermarks_t *table = watermarks; ++ ++ if (!table || !clock_ranges) ++ return -EINVAL; ++ ++ if (clock_ranges->num_wm_dmif_sets > 4 || ++ clock_ranges->num_wm_mcif_sets > 4) ++ return -EINVAL; ++ ++ for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { ++ table->WatermarkRow[1][i].MinClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[1][i].MaxClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[1][i].MinUclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[1][i].MaxUclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[1][i].WmSetting = (uint8_t) ++ clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; ++ } ++ ++ for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) { ++ table->WatermarkRow[0][i].MinClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[0][i].MaxClock = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[0][i].MinUclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[0][i].MaxUclk = ++ cpu_to_le16((uint16_t) ++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / ++ 1000)); ++ table->WatermarkRow[0][i].WmSetting = (uint8_t) ++ clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; ++ } ++ ++ return 0; ++} ++ + static const struct pptable_funcs vega20_ppt_funcs = { + .tables_init = vega20_tables_init, + .alloc_dpm_context = vega20_allocate_dpm_context, +@@ -3082,6 +3142,7 @@ static const struct pptable_funcs vega20_ppt_funcs = { + .get_fan_speed_percent = vega20_get_fan_speed_percent, + .get_gpu_power= vega20_get_gpu_power, + .get_current_activity_percent = vega20_get_current_activity_percent, ++ .set_watermarks_table = vega20_set_watermarks_table, + }; + + void vega20_set_ppt_funcs(struct smu_context *smu) +-- +2.17.1 + |