diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2259-drm-amd-powerplay-introduce-the-navi10-pptable-imple.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2259-drm-amd-powerplay-introduce-the-navi10-pptable-imple.patch | 380 |
1 files changed, 380 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2259-drm-amd-powerplay-introduce-the-navi10-pptable-imple.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2259-drm-amd-powerplay-introduce-the-navi10-pptable-imple.patch new file mode 100644 index 00000000..4934b6ad --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2259-drm-amd-powerplay-introduce-the-navi10-pptable-imple.patch @@ -0,0 +1,380 @@ +From 266b11db63e3a9d985fa9f8c963fd3ba2f338da3 Mon Sep 17 00:00:00 2001 +From: Huang Rui <ray.huang@amd.com> +Date: Thu, 31 Jan 2019 19:46:26 +0800 +Subject: [PATCH 2259/2940] drm/amd/powerplay: introduce the navi10 pptable + implementation + +This patch introduces the navi10 pptable implementation, so far it is already +has firmware loading, pptable side loading, writing back to smc, and feature +mask enabling. + +Signed-off-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/Makefile | 2 +- + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 303 +++++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 28 ++ + 3 files changed, 332 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/navi10_ppt.c + create mode 100644 drivers/gpu/drm/amd/powerplay/navi10_ppt.h + +diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile +index ec87b3430d12..727c5cff231c 100644 +--- a/drivers/gpu/drm/amd/powerplay/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/Makefile +@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$( + + include $(AMD_POWERPLAY) + +-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o ++POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o navi10_ppt.o + + AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +new file mode 100644 +index 000000000000..283b655a17df +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +@@ -0,0 +1,303 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#include "pp_debug.h" ++#include <linux/firmware.h> ++#include "amdgpu.h" ++#include "amdgpu_smu.h" ++#include "atomfirmware.h" ++#include "amdgpu_atomfirmware.h" ++#include "smu_v11_0.h" ++#include "smu_11_0_driver_if.h" ++#include "soc15_common.h" ++#include "atom.h" ++#include "navi10_ppt.h" ++#include "smu_v11_0_pptable.h" ++#include "smu_v11_0_ppsmc.h" ++ ++#define MSG_MAP(msg, index) \ ++ [SMU_MSG_##msg] = index ++ ++static int navi10_message_map[SMU_MSG_MAX_COUNT] = { ++ MSG_MAP(TestMessage, PPSMC_MSG_TestMessage), ++ MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion), ++ MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion), ++ MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow), ++ MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh), ++ MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures), ++ MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures), ++ MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow), ++ MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh), ++ MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow), ++ MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh), ++ MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow), ++ MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh), ++ MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask), ++ MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit), ++ MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh), ++ MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow), ++ MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh), ++ MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow), ++ MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram), ++ MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu), ++ MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable), ++ MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable), ++ MSG_MAP(RunBtc, PPSMC_MSG_RunBtc), ++ MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco), ++ MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq), ++ MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq), ++ MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq), ++ MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq), ++ MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq), ++ MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq), ++ MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex), ++ MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig), ++ MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode), ++ MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh), ++ MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow), ++ MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters), ++ MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk), ++ MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt), ++ MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource), ++ MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch), ++ MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps), ++ MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload), ++ MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh), ++ MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow), ++ MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize), ++ MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt), ++ MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays), ++ MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh), ++ MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow), ++ MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff), ++ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff), ++ MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit), ++ MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq), ++ MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData), ++ MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco), ++ MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset), ++ MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown), ++}; ++ ++static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index) ++{ ++ if (index > SMU_MSG_MAX_COUNT || index > PPSMC_Message_Count) ++ return -EINVAL; ++ return navi10_message_map[index]; ++ ++} ++ ++static int ++navi10_get_unallowed_feature_mask(struct smu_context *smu, ++ uint32_t *feature_mask, uint32_t num) ++{ ++ if (num > 2) ++ return -EINVAL; ++ ++ feature_mask[0] = 0x0C677844; ++ feature_mask[1] = 0xFFFFFF28; /* bit32~bit63 is Unsupported */ ++ ++ return 0; ++} ++ ++static int navi10_check_powerplay_table(struct smu_context *smu) ++{ ++ return 0; ++} ++ ++static int navi10_append_powerplay_table(struct smu_context *smu) ++{ ++ struct smu_table_context *table_context = &smu->smu_table; ++ PPTable_t *smc_pptable = table_context->driver_pptable; ++ struct atom_smc_dpm_info_v4_5 *smc_dpm_table; ++ int index, ret; ++ ++ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, ++ smc_dpm_info); ++ ++ ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL, ++ (uint8_t **)&smc_dpm_table); ++ if (ret) ++ return ret; ++ ++ memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, ++ sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS); ++ ++ /* SVI2 Board Parameters */ ++ smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx; ++ smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc; ++ smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping; ++ smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping; ++ smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping; ++ smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping; ++ smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask; ++ smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask; ++ smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent; ++ smc_pptable->Padding8_V = smc_dpm_table->Padding8_V; ++ ++ /* Telemetry Settings */ ++ smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent; ++ smc_pptable->GfxOffset = smc_dpm_table->GfxOffset; ++ smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx; ++ smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent; ++ smc_pptable->SocOffset = smc_dpm_table->SocOffset; ++ smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc; ++ smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent; ++ smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset; ++ smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0; ++ smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent; ++ smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset; ++ smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1; ++ ++ /* GPIO Settings */ ++ smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio; ++ smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity; ++ smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio; ++ smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity; ++ smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio; ++ smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity; ++ smc_pptable->GthrGpio = smc_dpm_table->GthrGpio; ++ smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity; ++ ++ /* LED Display Settings */ ++ smc_pptable->LedPin0 = smc_dpm_table->LedPin0; ++ smc_pptable->LedPin1 = smc_dpm_table->LedPin1; ++ smc_pptable->LedPin2 = smc_dpm_table->LedPin2; ++ smc_pptable->padding8_4 = smc_dpm_table->padding8_4; ++ ++ /* GFXCLK PLL Spread Spectrum */ ++ smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled; ++ smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent; ++ smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq; ++ ++ /* GFXCLK DFLL Spread Spectrum */ ++ smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled; ++ smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent; ++ smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq; ++ ++ /* UCLK Spread Spectrum */ ++ smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled; ++ smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent; ++ smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq; ++ ++ /* SOCCLK Spread Spectrum */ ++ smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled; ++ smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent; ++ smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq; ++ ++ /* Total board power */ ++ smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower; ++ smc_pptable->BoardPadding = smc_dpm_table->BoardPadding; ++ ++ /* Mvdd Svi2 Div Ratio Setting */ ++ smc_pptable->MvddRatio = smc_dpm_table->MvddRatio; ++ ++ return 0; ++} ++ ++static int navi10_store_powerplay_table(struct smu_context *smu) ++{ ++ struct smu_11_0_powerplay_table *powerplay_table = NULL; ++ struct smu_table_context *table_context = &smu->smu_table; ++ ++ if (!table_context->power_play_table) ++ return -EINVAL; ++ ++ powerplay_table = table_context->power_play_table; ++ ++ memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, ++ sizeof(PPTable_t)); ++ ++ return 0; ++} ++ ++static int navi10_allocate_dpm_context(struct smu_context *smu) ++{ ++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm; ++ ++ if (smu_dpm->dpm_context) ++ return -EINVAL; ++ ++ smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), ++ GFP_KERNEL); ++ if (!smu_dpm->dpm_context) ++ return -ENOMEM; ++ ++ smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); ++ ++ return 0; ++} ++ ++static int navi10_set_default_dpm_table(struct smu_context *smu) ++{ ++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm; ++ struct smu_table_context *table_context = &smu->smu_table; ++ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; ++ PPTable_t *driver_ppt = NULL; ++ ++ driver_ppt = table_context->driver_pptable; ++ ++ dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0]; ++ dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0]; ++ dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0]; ++ dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0]; ++ dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0]; ++ dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0]; ++ dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0]; ++ dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0]; ++ dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1]; ++ ++ dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0]; ++ dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1]; ++ ++ return 0; ++} ++ ++static const struct pptable_funcs navi10_ppt_funcs = { ++ .alloc_dpm_context = navi10_allocate_dpm_context, ++ .store_powerplay_table = navi10_store_powerplay_table, ++ .check_powerplay_table = navi10_check_powerplay_table, ++ .append_powerplay_table = navi10_append_powerplay_table, ++ .get_smu_msg_index = navi10_get_smu_msg_index, ++ .get_unallowed_feature_mask = navi10_get_unallowed_feature_mask, ++ .set_default_dpm_table = navi10_set_default_dpm_table, ++}; ++ ++void navi10_set_ppt_funcs(struct smu_context *smu) ++{ ++ smu->ppt_funcs = &navi10_ppt_funcs; ++} +diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h +new file mode 100644 +index 000000000000..957288e22f47 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h +@@ -0,0 +1,28 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __NAVI10_PPT_H__ ++#define __NAVI10_PPT_H__ ++ ++extern void navi10_set_ppt_funcs(struct smu_context *smu); ++ ++#endif +-- +2.17.1 + |