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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2252-drm-amdgpu-add-navi10-common-ip-block-v3.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2252-drm-amdgpu-add-navi10-common-ip-block-v3.patch937
1 files changed, 937 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2252-drm-amdgpu-add-navi10-common-ip-block-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2252-drm-amdgpu-add-navi10-common-ip-block-v3.patch
new file mode 100644
index 00000000..87fa1b8d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2252-drm-amdgpu-add-navi10-common-ip-block-v3.patch
@@ -0,0 +1,937 @@
+From a34020d409323b67e528d8e83dca1cc09c2085dc Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 4 Mar 2019 14:07:37 +0800
+Subject: [PATCH 2252/2940] drm/amdgpu: add navi10 common ip block (v3)
+
+This adds the core SOC code for navi asics.
+
+v1: add place holder and initial basic function (Ray)
+v2: add new introduced functions to avoid reference
+ NULL pointer (Hawking)
+v3L squash in updates (Alex)
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
+ drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c | 66 ++
+ drivers/gpu/drm/amd/amdgpu/nv.c | 777 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/nv.h | 33 +
+ 4 files changed, 877 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/nv.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/nv.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 511f4d5bcb48..d9fe65786054 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -63,7 +63,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
+
+ amdgpu-y += \
+ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
+- vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o
++ vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o
+
+ # add DF block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+new file mode 100644
+index 000000000000..8cd4568c07ee
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+@@ -0,0 +1,66 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "nv.h"
++
++#include "soc15_common.h"
++#include "soc15_hw_ip.h"
++#include "navi10_ip_offset.h"
++
++int navi10_reg_base_init(struct amdgpu_device *adev)
++{
++ int r, i;
++
++ if (amdgpu_discovery) {
++ r = amdgpu_discovery_reg_base_init(adev);
++ if (r) {
++ DRM_WARN("failed to init reg base from ip discovery table, "
++ "fallback to legacy init method\n");
++ goto legacy_init;
++ }
++
++ return 0;
++ }
++
++legacy_init:
++ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
++ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
++ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
++ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
++ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
++ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
++ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
++ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
++ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
++ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
++ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
++ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
++ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
++ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
++ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
++ }
++
++ return 0;
++}
++
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+new file mode 100644
+index 000000000000..a0d19b9d329c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -0,0 +1,777 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include <linux/firmware.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_atombios.h"
++#include "amdgpu_ih.h"
++#include "amdgpu_uvd.h"
++#include "amdgpu_vce.h"
++#include "amdgpu_ucode.h"
++#include "amdgpu_psp.h"
++#include "atom.h"
++#include "amd_pcie.h"
++
++#include "gc/gc_10_1_0_offset.h"
++#include "gc/gc_10_1_0_sh_mask.h"
++#include "hdp/hdp_5_0_0_offset.h"
++#include "hdp/hdp_5_0_0_sh_mask.h"
++
++#include "soc15.h"
++#include "soc15_common.h"
++#include "gmc_v10_0.h"
++#include "gfxhub_v2_0.h"
++#include "mmhub_v2_0.h"
++#include "nv.h"
++#include "navi10_ih.h"
++#include "gfx_v10_0.h"
++#include "sdma_v5_0.h"
++#include "vcn_v2_0.h"
++#include "dce_virtual.h"
++#include "mes_v10_1.h"
++
++static const struct amd_ip_funcs nv_common_ip_funcs;
++
++/*
++ * Indirect registers accessor
++ */
++static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
++{
++ unsigned long flags, address, data;
++ u32 r;
++ address = adev->nbio_funcs->get_pcie_index_offset(adev);
++ data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++ WREG32(address, reg);
++ (void)RREG32(address);
++ r = RREG32(data);
++ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++ return r;
++}
++
++static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++ unsigned long flags, address, data;
++
++ address = adev->nbio_funcs->get_pcie_index_offset(adev);
++ data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++ WREG32(address, reg);
++ (void)RREG32(address);
++ WREG32(data, v);
++ (void)RREG32(data);
++ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++}
++
++static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
++{
++ unsigned long flags, address, data;
++ u32 r;
++
++ address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
++ data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
++
++ spin_lock_irqsave(&adev->didt_idx_lock, flags);
++ WREG32(address, (reg));
++ r = RREG32(data);
++ spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
++ return r;
++}
++
++static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
++{
++ unsigned long flags, address, data;
++
++ address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
++ data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
++
++ spin_lock_irqsave(&adev->didt_idx_lock, flags);
++ WREG32(address, (reg));
++ WREG32(data, (v));
++ spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
++}
++
++static u32 nv_get_config_memsize(struct amdgpu_device *adev)
++{
++ return adev->nbio_funcs->get_memsize(adev);
++}
++
++static u32 nv_get_xclk(struct amdgpu_device *adev)
++{
++ return adev->clock.spll.reference_freq / 4;
++}
++
++
++void nv_grbm_select(struct amdgpu_device *adev,
++ u32 me, u32 pipe, u32 queue, u32 vmid)
++{
++ u32 grbm_gfx_cntl = 0;
++ grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
++ grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
++ grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
++ grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
++
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
++}
++
++static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
++{
++ /* todo */
++}
++
++static bool nv_read_disabled_bios(struct amdgpu_device *adev)
++{
++ /* todo */
++ return false;
++}
++
++static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
++ u8 *bios, u32 length_bytes)
++{
++ /* TODO: will implement it when SMU header is available */
++ return false;
++}
++
++static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
++ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
++ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
++ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
++ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
++ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
++ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
++#if 0 /* TODO: will set it when SDMA header is available */
++ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
++ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
++#endif
++ { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
++ { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
++};
++
++static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
++ u32 sh_num, u32 reg_offset)
++{
++ uint32_t val;
++
++ mutex_lock(&adev->grbm_idx_mutex);
++ if (se_num != 0xffffffff || sh_num != 0xffffffff)
++ amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
++
++ val = RREG32(reg_offset);
++
++ if (se_num != 0xffffffff || sh_num != 0xffffffff)
++ amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
++ mutex_unlock(&adev->grbm_idx_mutex);
++ return val;
++}
++
++static uint32_t nv_get_register_value(struct amdgpu_device *adev,
++ bool indexed, u32 se_num,
++ u32 sh_num, u32 reg_offset)
++{
++ if (indexed) {
++ return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
++ } else {
++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
++ return adev->gfx.config.gb_addr_config;
++ return RREG32(reg_offset);
++ }
++}
++
++static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
++ u32 sh_num, u32 reg_offset, u32 *value)
++{
++ uint32_t i;
++ struct soc15_allowed_register_entry *en;
++
++ *value = 0;
++ for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
++ en = &nv_allowed_read_registers[i];
++ if (reg_offset !=
++ (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
++ continue;
++
++ *value = nv_get_register_value(adev,
++ nv_allowed_read_registers[i].grbm_indexed,
++ se_num, sh_num, reg_offset);
++ return 0;
++ }
++ return -EINVAL;
++}
++
++#if 0
++static void nv_gpu_pci_config_reset(struct amdgpu_device *adev)
++{
++ u32 i;
++
++ dev_info(adev->dev, "GPU pci config reset\n");
++
++ /* disable BM */
++ pci_clear_master(adev->pdev);
++ /* reset */
++ amdgpu_pci_config_reset(adev);
++
++ udelay(100);
++
++ /* wait for asic to come out of reset */
++ for (i = 0; i < adev->usec_timeout; i++) {
++ u32 memsize = nbio_v2_3_get_memsize(adev);
++ if (memsize != 0xffffffff)
++ break;
++ udelay(1);
++ }
++
++}
++#endif
++
++static int nv_asic_reset(struct amdgpu_device *adev)
++{
++
++ /* FIXME: it doesn't work since vega10 */
++#if 0
++ amdgpu_atombios_scratch_regs_engine_hung(adev, true);
++
++ nv_gpu_pci_config_reset(adev);
++
++ amdgpu_atombios_scratch_regs_engine_hung(adev, false);
++#endif
++
++ return 0;
++}
++
++static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
++{
++ /* todo */
++ return 0;
++}
++
++static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
++{
++ /* todo */
++ return 0;
++}
++
++static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
++{
++ if (pci_is_root_bus(adev->pdev->bus))
++ return;
++
++ if (amdgpu_pcie_gen2 == 0)
++ return;
++
++ if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
++ return;
++
++ /* todo */
++}
++
++static void nv_program_aspm(struct amdgpu_device *adev)
++{
++
++ if (amdgpu_aspm == 0)
++ return;
++
++ /* todo */
++}
++
++static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
++ bool enable)
++{
++ adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
++ adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
++}
++
++static const struct amdgpu_ip_block_version nv_common_ip_block =
++{
++ .type = AMD_IP_BLOCK_TYPE_COMMON,
++ .major = 1,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &nv_common_ip_funcs,
++};
++
++int nv_set_ip_blocks(struct amdgpu_device *adev)
++{
++ /* Set IP register base before any HW register access */
++ switch (adev->asic_type) {
++ case CHIP_NAVI10:
++ navi10_reg_base_init(adev);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ adev->nbio_funcs = &nbio_v2_3_funcs;
++
++ adev->nbio_funcs->detect_hw_virt(adev);
++
++ switch (adev->asic_type) {
++ case CHIP_NAVI10:
++ amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
++ amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
++ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
++ is_support_sw_smu(adev))
++ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
++ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
++ amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
++ is_support_sw_smu(adev))
++ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
++ if (adev->enable_mes)
++ amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
++{
++ return adev->nbio_funcs->get_rev_id(adev);
++}
++
++static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
++{
++ adev->nbio_funcs->hdp_flush(adev, ring);
++}
++
++static void nv_invalidate_hdp(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring)
++{
++ if (!ring || !ring->funcs->emit_wreg) {
++ WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
++ } else {
++ amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
++ HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
++ }
++}
++
++static bool nv_need_full_reset(struct amdgpu_device *adev)
++{
++ return true;
++}
++
++static void nv_get_pcie_usage(struct amdgpu_device *adev,
++ uint64_t *count0,
++ uint64_t *count1)
++{
++ /*TODO*/
++}
++
++static bool nv_need_reset_on_init(struct amdgpu_device *adev)
++{
++#if 0
++ u32 sol_reg;
++
++ if (adev->flags & AMD_IS_APU)
++ return false;
++
++ /* Check sOS sign of life register to confirm sys driver and sOS
++ * are already been loaded.
++ */
++ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
++ if (sol_reg)
++ return true;
++#endif
++ /* TODO: re-enable it when mode1 reset is functional */
++ return false;
++}
++
++static void nv_init_doorbell_index(struct amdgpu_device *adev)
++{
++ adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
++ adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
++ adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
++ adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
++ adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
++ adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
++ adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
++ adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
++ adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
++ adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
++ adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
++ adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
++ adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
++ adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
++ adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
++ adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
++ adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
++ adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
++ adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
++ adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
++ adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
++ adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
++
++ adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
++ adev->doorbell_index.sdma_doorbell_range = 20;
++}
++
++static const struct amdgpu_asic_funcs nv_asic_funcs =
++{
++ .read_disabled_bios = &nv_read_disabled_bios,
++ .read_bios_from_rom = &nv_read_bios_from_rom,
++ .read_register = &nv_read_register,
++ .reset = &nv_asic_reset,
++ .set_vga_state = &nv_vga_set_state,
++ .get_xclk = &nv_get_xclk,
++ .set_uvd_clocks = &nv_set_uvd_clocks,
++ .set_vce_clocks = &nv_set_vce_clocks,
++ .get_config_memsize = &nv_get_config_memsize,
++ .flush_hdp = &nv_flush_hdp,
++ .invalidate_hdp = &nv_invalidate_hdp,
++ .init_doorbell_index = &nv_init_doorbell_index,
++ .need_full_reset = &nv_need_full_reset,
++ .get_pcie_usage = &nv_get_pcie_usage,
++ .need_reset_on_init = &nv_need_reset_on_init,
++};
++
++static int nv_common_early_init(void *handle)
++{
++ bool psp_enabled = false;
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ adev->smc_rreg = NULL;
++ adev->smc_wreg = NULL;
++ adev->pcie_rreg = &nv_pcie_rreg;
++ adev->pcie_wreg = &nv_pcie_wreg;
++
++ /* TODO: will add them during VCN v2 implementation */
++ adev->uvd_ctx_rreg = NULL;
++ adev->uvd_ctx_wreg = NULL;
++
++ adev->didt_rreg = &nv_didt_rreg;
++ adev->didt_wreg = &nv_didt_wreg;
++
++ adev->asic_funcs = &nv_asic_funcs;
++
++ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
++ (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
++ psp_enabled = true;
++
++ adev->rev_id = nv_get_rev_id(adev);
++ adev->external_rev_id = 0xff;
++ switch (adev->asic_type) {
++ case CHIP_NAVI10:
++ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
++ AMD_CG_SUPPORT_GFX_MGLS |
++ AMD_CG_SUPPORT_GFX_RLC_LS |
++ AMD_CG_SUPPORT_GFX_CP_LS |
++ AMD_CG_SUPPORT_GFX_CGLS |
++ AMD_CG_SUPPORT_GFX_CGCG |
++ AMD_CG_SUPPORT_IH_CG |
++ AMD_CG_SUPPORT_HDP_MGCG |
++ AMD_CG_SUPPORT_HDP_LS |
++ AMD_CG_SUPPORT_SDMA_MGCG |
++ AMD_CG_SUPPORT_SDMA_LS |
++ AMD_CG_SUPPORT_MC_MGCG |
++ AMD_CG_SUPPORT_MC_LS |
++ AMD_CG_SUPPORT_ATHUB_MGCG |
++ AMD_CG_SUPPORT_ATHUB_LS |
++ AMD_CG_SUPPORT_VCN_MGCG |
++ AMD_CG_SUPPORT_BIF_MGCG |
++ AMD_CG_SUPPORT_BIF_LS;
++ adev->pg_flags = 0;
++ adev->external_rev_id = adev->rev_id + 0x1;
++ break;
++ default:
++ /* FIXME: not supported yet */
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int nv_common_late_init(void *handle)
++{
++ return 0;
++}
++
++static int nv_common_sw_init(void *handle)
++{
++ return 0;
++}
++
++static int nv_common_sw_fini(void *handle)
++{
++ return 0;
++}
++
++static int nv_common_hw_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ /* enable pcie gen2/3 link */
++ nv_pcie_gen3_enable(adev);
++ /* enable aspm */
++ nv_program_aspm(adev);
++ /* setup nbio registers */
++ adev->nbio_funcs->init_registers(adev);
++ /* enable the doorbell aperture */
++ nv_enable_doorbell_aperture(adev, true);
++
++ return 0;
++}
++
++static int nv_common_hw_fini(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ /* disable the doorbell aperture */
++ nv_enable_doorbell_aperture(adev, false);
++
++ return 0;
++}
++
++static int nv_common_suspend(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ return nv_common_hw_fini(adev);
++}
++
++static int nv_common_resume(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ return nv_common_hw_init(adev);
++}
++
++static bool nv_common_is_idle(void *handle)
++{
++ return true;
++}
++
++static int nv_common_wait_for_idle(void *handle)
++{
++ return 0;
++}
++
++static int nv_common_soft_reset(void *handle)
++{
++ return 0;
++}
++
++static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
++ bool enable)
++{
++ uint32_t hdp_clk_cntl, hdp_clk_cntl1;
++ uint32_t hdp_mem_pwr_cntl;
++
++ if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
++ AMD_CG_SUPPORT_HDP_DS |
++ AMD_CG_SUPPORT_HDP_SD)))
++ return;
++
++ hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
++ hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
++
++ /* Before doing clock/power mode switch,
++ * forced on IPH & RC clock */
++ hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
++ IPH_MEM_CLK_SOFT_OVERRIDE, 1);
++ hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
++ RC_MEM_CLK_SOFT_OVERRIDE, 1);
++ WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
++
++ /* HDP 5.0 doesn't support dynamic power mode switch,
++ * disable clock and power gating before any changing */
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ IPH_MEM_POWER_CTRL_EN, 0);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ IPH_MEM_POWER_LS_EN, 0);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ IPH_MEM_POWER_DS_EN, 0);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ IPH_MEM_POWER_SD_EN, 0);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ RC_MEM_POWER_CTRL_EN, 0);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ RC_MEM_POWER_LS_EN, 0);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ RC_MEM_POWER_DS_EN, 0);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
++ RC_MEM_POWER_SD_EN, 0);
++ WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
++
++ /* only one clock gating mode (LS/DS/SD) can be enabled */
++ if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
++ HDP_MEM_POWER_CTRL,
++ IPH_MEM_POWER_LS_EN, enable);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
++ HDP_MEM_POWER_CTRL,
++ RC_MEM_POWER_LS_EN, enable);
++ } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
++ HDP_MEM_POWER_CTRL,
++ IPH_MEM_POWER_DS_EN, enable);
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
++ HDP_MEM_POWER_CTRL,
++ RC_MEM_POWER_DS_EN, enable);
++ } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
++ HDP_MEM_POWER_CTRL,
++ IPH_MEM_POWER_SD_EN, enable);
++ /* RC should not use shut down mode, fallback to ds */
++ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
++ HDP_MEM_POWER_CTRL,
++ RC_MEM_POWER_DS_EN, enable);
++ }
++
++ WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
++
++ /* restore IPH & RC clock override after clock/power mode changing */
++ WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
++}
++
++static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
++ bool enable)
++{
++ uint32_t hdp_clk_cntl;
++
++ if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
++ return;
++
++ hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
++
++ if (enable) {
++ hdp_clk_cntl &=
++ ~(uint32_t)
++ (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
++ } else {
++ hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
++ }
++
++ WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
++}
++
++static int nv_common_set_clockgating_state(void *handle,
++ enum amd_clockgating_state state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ if (amdgpu_sriov_vf(adev))
++ return 0;
++
++ switch (adev->asic_type) {
++ case CHIP_NAVI10:
++ adev->nbio_funcs->update_medium_grain_clock_gating(adev,
++ state == AMD_CG_STATE_GATE ? true : false);
++ adev->nbio_funcs->update_medium_grain_light_sleep(adev,
++ state == AMD_CG_STATE_GATE ? true : false);
++ nv_update_hdp_mem_power_gating(adev,
++ state == AMD_CG_STATE_GATE ? true : false);
++ nv_update_hdp_clock_gating(adev,
++ state == AMD_CG_STATE_GATE ? true : false);
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++static int nv_common_set_powergating_state(void *handle,
++ enum amd_powergating_state state)
++{
++ /* TODO */
++ return 0;
++}
++
++static void nv_common_get_clockgating_state(void *handle, u32 *flags)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ uint32_t tmp;
++
++ if (amdgpu_sriov_vf(adev))
++ *flags = 0;
++
++ adev->nbio_funcs->get_clockgating_state(adev, flags);
++
++ /* AMD_CG_SUPPORT_HDP_MGCG */
++ tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
++ if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
++ HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
++ *flags |= AMD_CG_SUPPORT_HDP_MGCG;
++
++ /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
++ tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
++ if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
++ *flags |= AMD_CG_SUPPORT_HDP_LS;
++ else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
++ *flags |= AMD_CG_SUPPORT_HDP_DS;
++ else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
++ *flags |= AMD_CG_SUPPORT_HDP_SD;
++
++ return;
++}
++
++static const struct amd_ip_funcs nv_common_ip_funcs = {
++ .name = "nv_common",
++ .early_init = nv_common_early_init,
++ .late_init = nv_common_late_init,
++ .sw_init = nv_common_sw_init,
++ .sw_fini = nv_common_sw_fini,
++ .hw_init = nv_common_hw_init,
++ .hw_fini = nv_common_hw_fini,
++ .suspend = nv_common_suspend,
++ .resume = nv_common_resume,
++ .is_idle = nv_common_is_idle,
++ .wait_for_idle = nv_common_wait_for_idle,
++ .soft_reset = nv_common_soft_reset,
++ .set_clockgating_state = nv_common_set_clockgating_state,
++ .set_powergating_state = nv_common_set_powergating_state,
++ .get_clockgating_state= nv_common_get_clockgating_state,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
+new file mode 100644
+index 000000000000..639c54933cc5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/nv.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __NV_H__
++#define __NV_H__
++
++#include "nbio_v2_3.h"
++
++void nv_grbm_select(struct amdgpu_device *adev,
++ u32 me, u32 pipe, u32 queue, u32 vmid);
++int nv_set_ip_blocks(struct amdgpu_device *adev);
++int navi10_reg_base_init(struct amdgpu_device *adev);
++#endif
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 12:40:04 +0000