diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2182-drm-amdgpu-add-mmhub-v2-block-for-navi10-v4.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2182-drm-amdgpu-add-mmhub-v2-block-for-navi10-v4.patch | 528 |
1 files changed, 528 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2182-drm-amdgpu-add-mmhub-v2-block-for-navi10-v4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2182-drm-amdgpu-add-mmhub-v2-block-for-navi10-v4.patch new file mode 100644 index 00000000..cb6f3f74 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2182-drm-amdgpu-add-mmhub-v2-block-for-navi10-v4.patch @@ -0,0 +1,528 @@ +From b9bf68f2501490f8091f5fc7bff0d0516811cee6 Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Mon, 4 Mar 2019 13:49:28 +0800 +Subject: [PATCH 2182/2940] drm/amdgpu: add mmhub v2 block for navi10 (v4) + +v1: add place holder and initial functions (Ray) +v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking) +v3: switch to use amdgpu_gmc_pd_addr (Hawking) +v4: squash in updates (Alex) + +Signed-off-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- + drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 442 ++++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h | 35 ++ + 3 files changed, 478 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c + create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 42fce324066b..3d61185b9426 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -75,7 +75,7 @@ amdgpu-y += \ + gmc_v7_0.o \ + gmc_v8_0.o \ + gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \ +- gfxhub_v2_0.o ++ gfxhub_v2_0.o mmhub_v2_0.o + + # add IH block + amdgpu-y += \ +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +new file mode 100644 +index 000000000000..f65b9c827970 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +@@ -0,0 +1,442 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#include "amdgpu.h" ++#include "mmhub_v2_0.h" ++ ++#include "mmhub/mmhub_2_0_0_offset.h" ++#include "mmhub/mmhub_2_0_0_sh_mask.h" ++#include "mmhub/mmhub_2_0_0_default.h" ++#include "navi10_enum.h" ++ ++#include "soc15_common.h" ++ ++static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev) ++{ ++ uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo); ++ ++ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, ++ lower_32_bits(value)); ++ ++ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, ++ upper_32_bits(value)); ++} ++ ++static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) ++{ ++ mmhub_v2_0_init_gart_pt_regs(adev); ++ ++ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, ++ (u32)(adev->gmc.gart_start >> 12)); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, ++ (u32)(adev->gmc.gart_start >> 44)); ++ ++ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, ++ (u32)(adev->gmc.gart_end >> 12)); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, ++ (u32)(adev->gmc.gart_end >> 44)); ++} ++ ++static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) ++{ ++ uint64_t value; ++ uint32_t tmp; ++ ++ /* Disable AGP. */ ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); ++ ++ /* Program the system aperture low logical page number. */ ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, ++ adev->gmc.vram_start >> 18); ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, ++ adev->gmc.vram_end >> 18); ++ ++ /* Set default page address. */ ++ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + ++ adev->vm_manager.vram_base_offset; ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, ++ (u32)(value >> 12)); ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, ++ (u32)(value >> 44)); ++ ++ /* Program "protection fault". */ ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, ++ (u32)(adev->dummy_page_addr >> 12)); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, ++ (u32)((u64)adev->dummy_page_addr >> 44)); ++ ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, ++ ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); ++} ++ ++static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) ++{ ++ uint32_t tmp; ++ ++ /* Setup TLB control */ ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); ++ ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ++ ENABLE_ADVANCED_DRIVER_MODEL, 1); ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ++ SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ++ MTYPE, MTYPE_UC); /* UC, uncached */ ++ ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); ++} ++ ++static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) ++{ ++ uint32_t tmp; ++ ++ /* Setup L2 cache */ ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); ++ /* XXX for emulation, Refer to closed source code.*/ ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, ++ 0); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); ++ ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); ++ ++ tmp = mmMMVM_L2_CNTL3_DEFAULT; ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); ++ ++ tmp = mmMMVM_L2_CNTL4_DEFAULT; ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp); ++} ++ ++static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) ++{ ++ uint32_t tmp; ++ ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); ++} ++ ++static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) ++{ ++ WREG32_SOC15(MMHUB, 0, ++ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, ++ 0xFFFFFFFF); ++ WREG32_SOC15(MMHUB, 0, ++ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, ++ 0x0000000F); ++ ++ WREG32_SOC15(MMHUB, 0, ++ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); ++ WREG32_SOC15(MMHUB, 0, ++ mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); ++ ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, ++ 0); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, ++ 0); ++} ++ ++static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) ++{ ++ int i; ++ uint32_t tmp; ++ ++ for (i = 0; i <= 14; i++) { ++ tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, ++ adev->vm_manager.num_level); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, ++ 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ PAGE_TABLE_BLOCK_SIZE, ++ adev->vm_manager.block_size - 9); ++ /* Send no-retry XNACK on fault to suppress VM fault storm. */ ++ tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ++ RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp); ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, ++ lower_32_bits(adev->vm_manager.max_pfn - 1)); ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, ++ upper_32_bits(adev->vm_manager.max_pfn - 1)); ++ } ++} ++ ++static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev) ++{ ++ unsigned i; ++ ++ for (i = 0; i < 18; ++i) { ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, ++ 2 * i, 0xffffffff); ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, ++ 2 * i, 0x1f); ++ } ++} ++ ++int mmhub_v2_0_gart_enable(struct amdgpu_device *adev) ++{ ++ if (amdgpu_sriov_vf(adev)) { ++ /* ++ * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are ++ * VF copy registers so vbios post doesn't program them, for ++ * SRIOV driver need to program them ++ */ ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE, ++ adev->gmc.vram_start >> 24); ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP, ++ adev->gmc.vram_end >> 24); ++ } ++ ++ /* GART Enable. */ ++ mmhub_v2_0_init_gart_aperture_regs(adev); ++ mmhub_v2_0_init_system_aperture_regs(adev); ++ mmhub_v2_0_init_tlb_regs(adev); ++ mmhub_v2_0_init_cache_regs(adev); ++ ++ mmhub_v2_0_enable_system_domain(adev); ++ mmhub_v2_0_disable_identity_aperture(adev); ++ mmhub_v2_0_setup_vmid_config(adev); ++ mmhub_v2_0_program_invalidation(adev); ++ ++ return 0; ++} ++ ++void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) ++{ ++ u32 tmp; ++ u32 i; ++ ++ /* Disable all tables */ ++ for (i = 0; i < 16; i++) ++ WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, i, 0); ++ ++ /* Setup TLB control */ ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); ++ tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ++ ENABLE_ADVANCED_DRIVER_MODEL, 0); ++ WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); ++ ++ /* Setup L2 cache */ ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0); ++} ++ ++/** ++ * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling ++ * ++ * @adev: amdgpu_device pointer ++ * @value: true redirects VM faults to the default page ++ */ ++void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) ++{ ++ u32 tmp; ++ tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, ++ value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); ++ if (!value) { ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ CRASH_ON_NO_RETRY_FAULT, 1); ++ tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, ++ CRASH_ON_RETRY_FAULT, 1); ++ } ++ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp); ++} ++ ++void mmhub_v2_0_init(struct amdgpu_device *adev) ++{ ++ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; ++ ++ hub->ctx0_ptb_addr_lo32 = ++ SOC15_REG_OFFSET(MMHUB, 0, ++ mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); ++ hub->ctx0_ptb_addr_hi32 = ++ SOC15_REG_OFFSET(MMHUB, 0, ++ mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); ++ hub->vm_inv_eng0_req = ++ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); ++ hub->vm_inv_eng0_ack = ++ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK); ++ hub->vm_context0_cntl = ++ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); ++ hub->vm_l2_pro_fault_status = ++ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS); ++ hub->vm_l2_pro_fault_cntl = ++ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); ++ ++} ++ ++static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, ++ bool enable) ++{ ++ uint32_t def, data, def1, data1; ++ ++ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); ++ ++ def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); ++ ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { ++ data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; ++ ++ data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); ++ ++ } else { ++ data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; ++ ++ data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); ++ } ++ ++ if (def != data) ++ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); ++ ++ if (def1 != data1) ++ WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); ++} ++ ++static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, ++ bool enable) ++{ ++ uint32_t def, data; ++ ++ def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); ++ ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) ++ data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; ++ else ++ data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; ++ ++ if (def != data) ++ WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data); ++} ++ ++int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, ++ enum amd_clockgating_state state) ++{ ++ if (amdgpu_sriov_vf(adev)) ++ return 0; ++ ++ switch (adev->asic_type) { ++ case CHIP_NAVI10: ++ mmhub_v2_0_update_medium_grain_clock_gating(adev, ++ state == AMD_CG_STATE_GATE ? true : false); ++ mmhub_v2_0_update_medium_grain_light_sleep(adev, ++ state == AMD_CG_STATE_GATE ? true : false); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) ++{ ++ int data, data1; ++ ++ if (amdgpu_sriov_vf(adev)) ++ *flags = 0; ++ ++ data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); ++ ++ data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); ++ ++ /* AMD_CG_SUPPORT_MC_MGCG */ ++ if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) && ++ !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | ++ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) ++ *flags |= AMD_CG_SUPPORT_MC_MGCG; ++ ++ /* AMD_CG_SUPPORT_MC_LS */ ++ if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) ++ *flags |= AMD_CG_SUPPORT_MC_LS; ++} +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h +new file mode 100644 +index 000000000000..db16f3ece218 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h +@@ -0,0 +1,35 @@ ++/* ++ * Copyright 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __MMHUB_V2_0_H__ ++#define __MMHUB_V2_0_H__ ++ ++int mmhub_v2_0_gart_enable(struct amdgpu_device *adev); ++void mmhub_v2_0_gart_disable(struct amdgpu_device *adev); ++void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, ++ bool value); ++void mmhub_v2_0_init(struct amdgpu_device *adev); ++int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, ++ enum amd_clockgating_state state); ++void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags); ++ ++#endif +-- +2.17.1 + |