diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2137-drm-amdgpu-add-OSS-5.0-register-headers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2137-drm-amdgpu-add-OSS-5.0-register-headers.patch | 1687 |
1 files changed, 1687 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2137-drm-amdgpu-add-OSS-5.0-register-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2137-drm-amdgpu-add-OSS-5.0-register-headers.patch new file mode 100644 index 00000000..eaa8d84b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2137-drm-amdgpu-add-OSS-5.0-register-headers.patch @@ -0,0 +1,1687 @@ +From 9b2b2e3f38b356bf4faffc29d2657641f2bffde3 Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Sun, 3 Mar 2019 11:30:47 +0800 +Subject: [PATCH 2137/2940] drm/amdgpu: add OSS 5.0 register headers + +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../asic_reg/oss/osssys_5_0_0_offset.h | 353 +++++ + .../asic_reg/oss/osssys_5_0_0_sh_mask.h | 1305 +++++++++++++++++ + 2 files changed, 1658 insertions(+) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h +new file mode 100644 +index 000000000000..408500fc882a +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h +@@ -0,0 +1,353 @@ ++/* ++ * Copyright (C) 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _osssys_5_0_0_OFFSET_HEADER ++#define _osssys_5_0_0_OFFSET_HEADER ++ ++ ++ ++// addressBlock: osssys_osssysdec ++// base address: 0x4280 ++#define mmIH_VMID_0_LUT 0x0000 ++#define mmIH_VMID_0_LUT_BASE_IDX 0 ++#define mmIH_VMID_1_LUT 0x0001 ++#define mmIH_VMID_1_LUT_BASE_IDX 0 ++#define mmIH_VMID_2_LUT 0x0002 ++#define mmIH_VMID_2_LUT_BASE_IDX 0 ++#define mmIH_VMID_3_LUT 0x0003 ++#define mmIH_VMID_3_LUT_BASE_IDX 0 ++#define mmIH_VMID_4_LUT 0x0004 ++#define mmIH_VMID_4_LUT_BASE_IDX 0 ++#define mmIH_VMID_5_LUT 0x0005 ++#define mmIH_VMID_5_LUT_BASE_IDX 0 ++#define mmIH_VMID_6_LUT 0x0006 ++#define mmIH_VMID_6_LUT_BASE_IDX 0 ++#define mmIH_VMID_7_LUT 0x0007 ++#define mmIH_VMID_7_LUT_BASE_IDX 0 ++#define mmIH_VMID_8_LUT 0x0008 ++#define mmIH_VMID_8_LUT_BASE_IDX 0 ++#define mmIH_VMID_9_LUT 0x0009 ++#define mmIH_VMID_9_LUT_BASE_IDX 0 ++#define mmIH_VMID_10_LUT 0x000a ++#define mmIH_VMID_10_LUT_BASE_IDX 0 ++#define mmIH_VMID_11_LUT 0x000b ++#define mmIH_VMID_11_LUT_BASE_IDX 0 ++#define mmIH_VMID_12_LUT 0x000c ++#define mmIH_VMID_12_LUT_BASE_IDX 0 ++#define mmIH_VMID_13_LUT 0x000d ++#define mmIH_VMID_13_LUT_BASE_IDX 0 ++#define mmIH_VMID_14_LUT 0x000e ++#define mmIH_VMID_14_LUT_BASE_IDX 0 ++#define mmIH_VMID_15_LUT 0x000f ++#define mmIH_VMID_15_LUT_BASE_IDX 0 ++#define mmIH_VMID_0_LUT_MM 0x0010 ++#define mmIH_VMID_0_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_1_LUT_MM 0x0011 ++#define mmIH_VMID_1_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_2_LUT_MM 0x0012 ++#define mmIH_VMID_2_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_3_LUT_MM 0x0013 ++#define mmIH_VMID_3_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_4_LUT_MM 0x0014 ++#define mmIH_VMID_4_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_5_LUT_MM 0x0015 ++#define mmIH_VMID_5_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_6_LUT_MM 0x0016 ++#define mmIH_VMID_6_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_7_LUT_MM 0x0017 ++#define mmIH_VMID_7_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_8_LUT_MM 0x0018 ++#define mmIH_VMID_8_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_9_LUT_MM 0x0019 ++#define mmIH_VMID_9_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_10_LUT_MM 0x001a ++#define mmIH_VMID_10_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_11_LUT_MM 0x001b ++#define mmIH_VMID_11_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_12_LUT_MM 0x001c ++#define mmIH_VMID_12_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_13_LUT_MM 0x001d ++#define mmIH_VMID_13_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_14_LUT_MM 0x001e ++#define mmIH_VMID_14_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_15_LUT_MM 0x001f ++#define mmIH_VMID_15_LUT_MM_BASE_IDX 0 ++#define mmIH_COOKIE_0 0x0020 ++#define mmIH_COOKIE_0_BASE_IDX 0 ++#define mmIH_COOKIE_1 0x0021 ++#define mmIH_COOKIE_1_BASE_IDX 0 ++#define mmIH_COOKIE_2 0x0022 ++#define mmIH_COOKIE_2_BASE_IDX 0 ++#define mmIH_COOKIE_3 0x0023 ++#define mmIH_COOKIE_3_BASE_IDX 0 ++#define mmIH_COOKIE_4 0x0024 ++#define mmIH_COOKIE_4_BASE_IDX 0 ++#define mmIH_COOKIE_5 0x0025 ++#define mmIH_COOKIE_5_BASE_IDX 0 ++#define mmIH_COOKIE_6 0x0026 ++#define mmIH_COOKIE_6_BASE_IDX 0 ++#define mmIH_COOKIE_7 0x0027 ++#define mmIH_COOKIE_7_BASE_IDX 0 ++#define mmIH_REGISTER_LAST_PART0 0x003f ++#define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_0 0x0040 ++#define mmSEM_REQ_INPUT_0_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_1 0x0041 ++#define mmSEM_REQ_INPUT_1_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_2 0x0042 ++#define mmSEM_REQ_INPUT_2_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_3 0x0043 ++#define mmSEM_REQ_INPUT_3_BASE_IDX 0 ++#define mmSEM_REGISTER_LAST_PART0 0x007f ++#define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 ++#define mmIH_RB_CNTL 0x0080 ++#define mmIH_RB_CNTL_BASE_IDX 0 ++#define mmIH_RB_BASE 0x0081 ++#define mmIH_RB_BASE_BASE_IDX 0 ++#define mmIH_RB_BASE_HI 0x0082 ++#define mmIH_RB_BASE_HI_BASE_IDX 0 ++#define mmIH_RB_RPTR 0x0083 ++#define mmIH_RB_RPTR_BASE_IDX 0 ++#define mmIH_RB_WPTR 0x0084 ++#define mmIH_RB_WPTR_BASE_IDX 0 ++#define mmIH_RB_WPTR_ADDR_HI 0x0085 ++#define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 ++#define mmIH_RB_WPTR_ADDR_LO 0x0086 ++#define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 ++#define mmIH_DOORBELL_RPTR 0x0087 ++#define mmIH_DOORBELL_RPTR_BASE_IDX 0 ++#define mmIH_RB_CNTL_RING1 0x008c ++#define mmIH_RB_CNTL_RING1_BASE_IDX 0 ++#define mmIH_RB_BASE_RING1 0x008d ++#define mmIH_RB_BASE_RING1_BASE_IDX 0 ++#define mmIH_RB_BASE_HI_RING1 0x008e ++#define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 ++#define mmIH_RB_RPTR_RING1 0x008f ++#define mmIH_RB_RPTR_RING1_BASE_IDX 0 ++#define mmIH_RB_WPTR_RING1 0x0090 ++#define mmIH_RB_WPTR_RING1_BASE_IDX 0 ++#define mmIH_DOORBELL_RPTR_RING1 0x0093 ++#define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 ++#define mmIH_RB_CNTL_RING2 0x0098 ++#define mmIH_RB_CNTL_RING2_BASE_IDX 0 ++#define mmIH_RB_BASE_RING2 0x0099 ++#define mmIH_RB_BASE_RING2_BASE_IDX 0 ++#define mmIH_RB_BASE_HI_RING2 0x009a ++#define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 ++#define mmIH_RB_RPTR_RING2 0x009b ++#define mmIH_RB_RPTR_RING2_BASE_IDX 0 ++#define mmIH_RB_WPTR_RING2 0x009c ++#define mmIH_RB_WPTR_RING2_BASE_IDX 0 ++#define mmIH_DOORBELL_RPTR_RING2 0x009f ++#define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 ++#define mmIH_VERSION 0x00a5 ++#define mmIH_VERSION_BASE_IDX 0 ++#define mmIH_CNTL 0x00c0 ++#define mmIH_CNTL_BASE_IDX 0 ++#define mmIH_CNTL2 0x00c1 ++#define mmIH_CNTL2_BASE_IDX 0 ++#define mmIH_STATUS 0x00c2 ++#define mmIH_STATUS_BASE_IDX 0 ++#define mmIH_PERFMON_CNTL 0x00c3 ++#define mmIH_PERFMON_CNTL_BASE_IDX 0 ++#define mmIH_PERFCOUNTER0_RESULT 0x00c4 ++#define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 ++#define mmIH_PERFCOUNTER1_RESULT 0x00c5 ++#define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 ++#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 ++#define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 ++#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 ++#define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 ++#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 ++#define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 ++#define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca ++#define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 ++#define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb ++#define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 ++#define mmIH_DSM_MATCH_FCN_ID 0x00cc ++#define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 ++#define mmIH_LIMIT_INT_RATE_CNTL 0x00cd ++#define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 ++#define mmIH_VF_RB_STATUS 0x00ce ++#define mmIH_VF_RB_STATUS_BASE_IDX 0 ++#define mmIH_VF_RB_STATUS2 0x00cf ++#define mmIH_VF_RB_STATUS2_BASE_IDX 0 ++#define mmIH_VF_RB1_STATUS 0x00d0 ++#define mmIH_VF_RB1_STATUS_BASE_IDX 0 ++#define mmIH_VF_RB1_STATUS2 0x00d1 ++#define mmIH_VF_RB1_STATUS2_BASE_IDX 0 ++#define mmIH_VF_RB2_STATUS 0x00d2 ++#define mmIH_VF_RB2_STATUS_BASE_IDX 0 ++#define mmIH_VF_RB2_STATUS2 0x00d3 ++#define mmIH_VF_RB2_STATUS2_BASE_IDX 0 ++#define mmIH_INT_FLOOD_CNTL 0x00d5 ++#define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 ++#define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 ++#define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 ++#define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 ++#define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_INT_FLOOD_STATUS 0x00d9 ++#define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_STORM_CLIENT_LIST_CNTL 0x00da ++#define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 ++#define mmIH_CLK_CTRL 0x00db ++#define mmIH_CLK_CTRL_BASE_IDX 0 ++#define mmIH_INT_FLAGS 0x00dc ++#define mmIH_INT_FLAGS_BASE_IDX 0 ++#define mmIH_LAST_INT_INFO0 0x00dd ++#define mmIH_LAST_INT_INFO0_BASE_IDX 0 ++#define mmIH_LAST_INT_INFO1 0x00de ++#define mmIH_LAST_INT_INFO1_BASE_IDX 0 ++#define mmIH_LAST_INT_INFO2 0x00df ++#define mmIH_LAST_INT_INFO2_BASE_IDX 0 ++#define mmIH_SCRATCH 0x00e0 ++#define mmIH_SCRATCH_BASE_IDX 0 ++#define mmIH_CLIENT_CREDIT_ERROR 0x00e1 ++#define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 ++#define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 ++#define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 ++#define mmIH_GPU_IOV_VIOLATION_LOG2 0x00e3 ++#define mmIH_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 ++#define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e4 ++#define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 ++#define mmIH_CREDIT_STATUS 0x00e5 ++#define mmIH_CREDIT_STATUS_BASE_IDX 0 ++#define mmIH_MMHUB_ERROR 0x00e6 ++#define mmIH_MMHUB_ERROR_BASE_IDX 0 ++#define mmIH_MEM_POWER_CTRL 0x00e9 ++#define mmIH_MEM_POWER_CTRL_BASE_IDX 0 ++#define mmIH_VF_RB_STATUS3 0x00ea ++#define mmIH_VF_RB_STATUS3_BASE_IDX 0 ++#define mmIH_VF_RB_STATUS4 0x00eb ++#define mmIH_VF_RB_STATUS4_BASE_IDX 0 ++#define mmIH_VF_RB1_STATUS3 0x00ec ++#define mmIH_VF_RB1_STATUS3_BASE_IDX 0 ++#define mmIH_VF_RB2_STATUS3 0x00ee ++#define mmIH_VF_RB2_STATUS3_BASE_IDX 0 ++#define mmIH_REGISTER_LAST_PART2 0x00ff ++#define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 ++#define mmSEM_CLK_CTRL 0x0100 ++#define mmSEM_CLK_CTRL_BASE_IDX 0 ++#define mmSEM_UTC_CREDIT 0x0101 ++#define mmSEM_UTC_CREDIT_BASE_IDX 0 ++#define mmSEM_UTC_CONFIG 0x0102 ++#define mmSEM_UTC_CONFIG_BASE_IDX 0 ++#define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 ++#define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 ++#define mmSEM_MCIF_CONFIG 0x0104 ++#define mmSEM_MCIF_CONFIG_BASE_IDX 0 ++#define mmSEM_PERFMON_CNTL 0x0105 ++#define mmSEM_PERFMON_CNTL_BASE_IDX 0 ++#define mmSEM_PERFCOUNTER0_RESULT 0x0106 ++#define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 ++#define mmSEM_PERFCOUNTER1_RESULT 0x0107 ++#define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 ++#define mmSEM_STATUS 0x0108 ++#define mmSEM_STATUS_BASE_IDX 0 ++#define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 ++#define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 ++#define mmSEM_MAILBOX 0x010a ++#define mmSEM_MAILBOX_BASE_IDX 0 ++#define mmSEM_MAILBOX_CONTROL 0x010b ++#define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 ++#define mmSEM_CHICKEN_BITS 0x010c ++#define mmSEM_CHICKEN_BITS_BASE_IDX 0 ++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d ++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 ++#define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e ++#define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 ++#define mmSEM_OUTSTANDING_THRESHOLD 0x010f ++#define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 ++#define mmSEM_MEM_POWER_CTRL 0x0110 ++#define mmSEM_MEM_POWER_CTRL_BASE_IDX 0 ++#define mmSEM_GPU_IOV_VIOLATION_LOG2 0x0111 ++#define mmSEM_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 ++#define mmSEM_REGISTER_LAST_PART2 0x017f ++#define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 ++#define mmIH_ACTIVE_FCN_ID 0x0180 ++#define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmIH_VIRT_RESET_REQ 0x0181 ++#define mmIH_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmIH_CLIENT_CFG 0x0184 ++#define mmIH_CLIENT_CFG_BASE_IDX 0 ++#define mmIH_CLIENT_CFG_INDEX 0x0188 ++#define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 ++#define mmIH_CLIENT_CFG_DATA 0x0189 ++#define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 ++#define mmIH_CID_REMAP_INDEX 0x018a ++#define mmIH_CID_REMAP_INDEX_BASE_IDX 0 ++#define mmIH_CID_REMAP_DATA 0x018b ++#define mmIH_CID_REMAP_DATA_BASE_IDX 0 ++#define mmIH_CHICKEN 0x018c ++#define mmIH_CHICKEN_BASE_IDX 0 ++#define mmIH_MMHUB_CNTL 0x018d ++#define mmIH_MMHUB_CNTL_BASE_IDX 0 ++#define mmIH_INT_DROP_CNTL 0x018e ++#define mmIH_INT_DROP_CNTL_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_VALUE0 0x018f ++#define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_VALUE1 0x0190 ++#define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_MASK0 0x0191 ++#define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_MASK1 0x0192 ++#define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 ++#define mmIH_REGISTER_LAST_PART1 0x019f ++#define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 ++#define mmSEM_ACTIVE_FCN_ID 0x01a0 ++#define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmSEM_VIRT_RESET_REQ 0x01a1 ++#define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmSEM_RESP_SDMA0 0x01a4 ++#define mmSEM_RESP_SDMA0_BASE_IDX 0 ++#define mmSEM_RESP_SDMA1 0x01a5 ++#define mmSEM_RESP_SDMA1_BASE_IDX 0 ++#define mmSEM_RESP_UVD 0x01a6 ++#define mmSEM_RESP_UVD_BASE_IDX 0 ++#define mmSEM_RESP_VCE_0 0x01a7 ++#define mmSEM_RESP_VCE_0_BASE_IDX 0 ++#define mmSEM_RESP_ACP 0x01a8 ++#define mmSEM_RESP_ACP_BASE_IDX 0 ++#define mmSEM_RESP_ISP 0x01a9 ++#define mmSEM_RESP_ISP_BASE_IDX 0 ++#define mmSEM_RESP_VCE_1 0x01aa ++#define mmSEM_RESP_VCE_1_BASE_IDX 0 ++#define mmSEM_RESP_VP8 0x01ab ++#define mmSEM_RESP_VP8_BASE_IDX 0 ++#define mmSEM_RESP_GC 0x01ac ++#define mmSEM_RESP_GC_BASE_IDX 0 ++#define mmSEM_CID_REMAP_INDEX 0x01b0 ++#define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 ++#define mmSEM_CID_REMAP_DATA 0x01b1 ++#define mmSEM_CID_REMAP_DATA_BASE_IDX 0 ++#define mmSEM_ATOMIC_OP_LUT 0x01b2 ++#define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 ++#define mmSEM_EDC_CONFIG 0x01b3 ++#define mmSEM_EDC_CONFIG_BASE_IDX 0 ++#define mmSEM_CHICKEN_BITS2 0x01b4 ++#define mmSEM_CHICKEN_BITS2_BASE_IDX 0 ++#define mmSEM_MMHUB_CNTL 0x01b5 ++#define mmSEM_MMHUB_CNTL_BASE_IDX 0 ++#define mmSEM_REGISTER_LAST_PART1 0x01bf ++#define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h +new file mode 100644 +index 000000000000..05543bde3444 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h +@@ -0,0 +1,1305 @@ ++/* ++ * Copyright (C) 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _osssys_5_0_0_SH_MASK_HEADER ++#define _osssys_5_0_0_SH_MASK_HEADER ++ ++ ++// addressBlock: osssys_osssysdec ++//IH_VMID_0_LUT ++#define IH_VMID_0_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_1_LUT ++#define IH_VMID_1_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_2_LUT ++#define IH_VMID_2_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_3_LUT ++#define IH_VMID_3_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_4_LUT ++#define IH_VMID_4_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_5_LUT ++#define IH_VMID_5_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_6_LUT ++#define IH_VMID_6_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_7_LUT ++#define IH_VMID_7_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_8_LUT ++#define IH_VMID_8_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_9_LUT ++#define IH_VMID_9_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_10_LUT ++#define IH_VMID_10_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_11_LUT ++#define IH_VMID_11_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_12_LUT ++#define IH_VMID_12_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_13_LUT ++#define IH_VMID_13_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_14_LUT ++#define IH_VMID_14_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_15_LUT ++#define IH_VMID_15_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_0_LUT_MM ++#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_1_LUT_MM ++#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_2_LUT_MM ++#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_3_LUT_MM ++#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_4_LUT_MM ++#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_5_LUT_MM ++#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_6_LUT_MM ++#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_7_LUT_MM ++#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_8_LUT_MM ++#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_9_LUT_MM ++#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_10_LUT_MM ++#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_11_LUT_MM ++#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_12_LUT_MM ++#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_13_LUT_MM ++#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_14_LUT_MM ++#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_15_LUT_MM ++#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_COOKIE_0 ++#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 ++#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 ++#define IH_COOKIE_0__RING_ID__SHIFT 0x10 ++#define IH_COOKIE_0__VM_ID__SHIFT 0x18 ++#define IH_COOKIE_0__RESERVED__SHIFT 0x1c ++#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f ++#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL ++#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L ++#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L ++#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L ++#define IH_COOKIE_0__RESERVED_MASK 0x70000000L ++#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L ++//IH_COOKIE_1 ++#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 ++#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL ++//IH_COOKIE_2 ++#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 ++#define IH_COOKIE_2__RESERVED__SHIFT 0x10 ++#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f ++#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL ++#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L ++#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L ++//IH_COOKIE_3 ++#define IH_COOKIE_3__PAS_ID__SHIFT 0x0 ++#define IH_COOKIE_3__RESERVED__SHIFT 0x10 ++#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f ++#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL ++#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L ++#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L ++//IH_COOKIE_4 ++#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 ++#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL ++//IH_COOKIE_5 ++#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 ++#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL ++//IH_COOKIE_6 ++#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 ++#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL ++//IH_COOKIE_7 ++#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 ++#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL ++//IH_REGISTER_LAST_PART0 ++#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 ++#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_0 ++#define SEM_REQ_INPUT_0__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_1 ++#define SEM_REQ_INPUT_1__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_2 ++#define SEM_REQ_INPUT_2__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_3 ++#define SEM_REQ_INPUT_3__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL ++//SEM_REGISTER_LAST_PART0 ++#define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 ++#define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL ++//IH_RB_CNTL ++#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 ++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 ++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 ++#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa ++#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb ++#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc ++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 ++#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 ++#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 ++#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 ++#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 ++#define IH_RB_CNTL__MC_RO__SHIFT 0x16 ++#define IH_RB_CNTL__MC_VMID__SHIFT 0x18 ++#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c ++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L ++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L ++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L ++#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L ++#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L ++#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L ++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L ++#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L ++#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L ++#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L ++#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L ++#define IH_RB_CNTL__MC_RO_MASK 0x00400000L ++#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L ++#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L ++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L ++//IH_RB_BASE ++#define IH_RB_BASE__ADDR__SHIFT 0x0 ++#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//IH_RB_BASE_HI ++#define IH_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL ++//IH_RB_RPTR ++#define IH_RB_RPTR__OFFSET__SHIFT 0x2 ++#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL ++//IH_RB_WPTR ++#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 ++#define IH_RB_WPTR__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 ++#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 ++#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L ++#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL ++#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L ++#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L ++//IH_RB_WPTR_ADDR_HI ++#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL ++//IH_RB_WPTR_ADDR_LO ++#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//IH_DOORBELL_RPTR ++#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 ++#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c ++#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL ++#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L ++//IH_RB_CNTL_RING1 ++#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 ++#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 ++#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7 ++#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 ++#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa ++#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb ++#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 ++#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 ++#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 ++#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 ++#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 ++#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L ++#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL ++#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L ++#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L ++#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L ++#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L ++#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L ++#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L ++#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L ++#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L ++#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L ++#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L ++//IH_RB_BASE_RING1 ++#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL ++//IH_RB_BASE_HI_RING1 ++#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL ++//IH_RB_RPTR_RING1 ++#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 ++#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL ++//IH_RB_WPTR_RING1 ++#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 ++#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 ++#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 ++#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L ++#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL ++#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L ++#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L ++//IH_DOORBELL_RPTR_RING1 ++#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 ++#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c ++#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL ++#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L ++//IH_RB_CNTL_RING2 ++#define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0 ++#define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1 ++#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7 ++#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 ++#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa ++#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR__SHIFT 0xb ++#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 ++#define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12 ++#define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14 ++#define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16 ++#define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18 ++#define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L ++#define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL ++#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L ++#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L ++#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L ++#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR_MASK 0x00000800L ++#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L ++#define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L ++#define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L ++#define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L ++#define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L ++#define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L ++//IH_RB_BASE_RING2 ++#define IH_RB_BASE_RING2__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL ++//IH_RB_BASE_HI_RING2 ++#define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL ++//IH_RB_RPTR_RING2 ++#define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2 ++#define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL ++//IH_RB_WPTR_RING2 ++#define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0 ++#define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12 ++#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13 ++#define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L ++#define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL ++#define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L ++#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L ++//IH_DOORBELL_RPTR_RING2 ++#define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0 ++#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c ++#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL ++#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L ++//IH_VERSION ++#define IH_VERSION__MINVER__SHIFT 0x0 ++#define IH_VERSION__MAJVER__SHIFT 0x8 ++#define IH_VERSION__REV__SHIFT 0x10 ++#define IH_VERSION__MINVER_MASK 0x0000007FL ++#define IH_VERSION__MAJVER_MASK 0x00007F00L ++#define IH_VERSION__REV_MASK 0x003F0000L ++//IH_CNTL ++#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 ++#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 ++#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 ++#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 ++#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL ++#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L ++#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L ++#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L ++//IH_CNTL2 ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L ++//IH_STATUS ++#define IH_STATUS__IDLE__SHIFT 0x0 ++#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 ++#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 ++#define IH_STATUS__RB_FULL__SHIFT 0x3 ++#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 ++#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 ++#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 ++#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 ++#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 ++#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 ++#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa ++#define IH_STATUS__SWITCH_READY__SHIFT 0xb ++#define IH_STATUS__RB1_FULL__SHIFT 0xc ++#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd ++#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe ++#define IH_STATUS__RB2_FULL__SHIFT 0xf ++#define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10 ++#define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11 ++#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 ++#define IH_STATUS__IDLE_MASK 0x00000001L ++#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L ++#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L ++#define IH_STATUS__RB_FULL_MASK 0x00000008L ++#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L ++#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L ++#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L ++#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L ++#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L ++#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L ++#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L ++#define IH_STATUS__SWITCH_READY_MASK 0x00000800L ++#define IH_STATUS__RB1_FULL_MASK 0x00001000L ++#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L ++#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L ++#define IH_STATUS__RB2_FULL_MASK 0x00008000L ++#define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L ++#define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L ++#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L ++//IH_PERFMON_CNTL ++#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 ++#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 ++#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 ++#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 ++#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 ++#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L ++#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L ++#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL ++#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L ++#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L ++#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L ++//IH_PERFCOUNTER0_RESULT ++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//IH_PERFCOUNTER1_RESULT ++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_VALUE_BIT_31_0 ++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_VALUE_BIT_63_32 ++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_VALUE_BIT_95_64 ++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_FIELD_CONTROL ++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 ++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 ++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 ++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 ++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 ++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 ++#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 ++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L ++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L ++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L ++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L ++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L ++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L ++#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L ++//IH_DSM_MATCH_DATA_CONTROL ++#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL ++//IH_DSM_MATCH_FCN_ID ++#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x0 ++#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x7 ++#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001FL ++#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000080L ++//IH_LIMIT_INT_RATE_CNTL ++#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 ++#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 ++#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 ++#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 ++#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 ++#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L ++#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL ++#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L ++#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L ++#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L ++//IH_VF_RB_STATUS ++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 ++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB_STATUS2 ++#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 ++#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB1_STATUS ++#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 ++#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB1_STATUS2 ++#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 ++#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB2_STATUS ++#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 ++#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB2_STATUS2 ++#define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0 ++#define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x7FFFFFFFL ++//IH_INT_FLOOD_CNTL ++#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 ++#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 ++#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 ++#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L ++#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L ++#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L ++//IH_RB0_INT_FLOOD_STATUS ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x7FFFFFFFL ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L ++//IH_RB1_INT_FLOOD_STATUS ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x7FFFFFFFL ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L ++//IH_RB2_INT_FLOOD_STATUS ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x7FFFFFFFL ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L ++//IH_INT_FLOOD_STATUS ++#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1d ++#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e ++#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x1F000000L ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x20000000L ++#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L ++//IH_STORM_CLIENT_LIST_CNTL ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L ++//IH_CLK_CTRL ++#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a ++#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b ++#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c ++#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d ++#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e ++#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f ++#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L ++#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L ++#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L ++#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L ++#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L ++#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L ++//IH_INT_FLAGS ++#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 ++#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 ++#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 ++#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 ++#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 ++#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 ++#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 ++#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 ++#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 ++#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 ++#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa ++#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb ++#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc ++#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd ++#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe ++#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf ++#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 ++#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 ++#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 ++#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 ++#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 ++#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 ++#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 ++#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 ++#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 ++#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 ++#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a ++#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b ++#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c ++#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d ++#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e ++#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f ++#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L ++#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L ++#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L ++#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L ++#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L ++#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L ++#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L ++#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L ++#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L ++#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L ++#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L ++#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L ++#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L ++#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L ++#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L ++#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L ++#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L ++#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L ++#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L ++#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L ++#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L ++#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L ++#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L ++#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L ++#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L ++#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L ++#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L ++#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L ++#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L ++#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L ++#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L ++#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L ++//IH_LAST_INT_INFO0 ++#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 ++#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 ++#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 ++#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 ++#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f ++#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL ++#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L ++#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L ++#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L ++#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L ++//IH_LAST_INT_INFO1 ++#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 ++#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL ++//IH_LAST_INT_INFO2 ++#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 ++#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 ++#define IH_LAST_INT_INFO2__VF__SHIFT 0x17 ++#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL ++#define IH_LAST_INT_INFO2__VF_ID_MASK 0x001F0000L ++#define IH_LAST_INT_INFO2__VF_MASK 0x00800000L ++//IH_SCRATCH ++#define IH_SCRATCH__DATA__SHIFT 0x0 ++#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL ++//IH_CLIENT_CREDIT_ERROR ++#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f ++#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L ++//IH_GPU_IOV_VIOLATION_LOG ++#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 ++#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 ++#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 ++#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 ++#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 ++#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L ++#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL ++#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L ++#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L ++#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x01F00000L ++//IH_GPU_IOV_VIOLATION_LOG2 ++#define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 ++#define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL ++//IH_COOKIE_REC_VIOLATION_LOG ++#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8 ++#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10 ++#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L ++#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L ++//IH_CREDIT_STATUS ++#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 ++#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 ++#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 ++#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 ++#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 ++#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 ++#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 ++#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 ++#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 ++#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa ++#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb ++#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc ++#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd ++#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe ++#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf ++#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 ++#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 ++#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 ++#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 ++#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 ++#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 ++#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 ++#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 ++#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 ++#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 ++#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a ++#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b ++#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c ++#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d ++#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e ++#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f ++#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L ++#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L ++#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L ++#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L ++#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L ++#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L ++#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L ++#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L ++#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L ++#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L ++#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L ++#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L ++#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L ++#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L ++#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L ++#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L ++#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L ++#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L ++#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L ++#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L ++#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L ++#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L ++#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L ++#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L ++#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L ++#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L ++#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L ++#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L ++#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L ++#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L ++#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L ++//IH_MMHUB_ERROR ++#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 ++#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 ++#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 ++#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L ++#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L ++#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L ++//IH_MEM_POWER_CTRL ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0 ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1 ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2 ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3 ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4 ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L ++#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L ++//IH_VF_RB_STATUS3 ++#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 ++#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB_STATUS4 ++#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT 0x0 ++#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB1_STATUS3 ++#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 ++#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK 0x7FFFFFFFL ++//IH_VF_RB2_STATUS3 ++#define IH_VF_RB2_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 ++#define IH_VF_RB2_STATUS3__RB_OVERFLOW_VF_MASK 0x7FFFFFFFL ++//IH_REGISTER_LAST_PART2 ++#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 ++#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL ++//SEM_CLK_CTRL ++#define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define SEM_CLK_CTRL__RESERVED__SHIFT 0xc ++#define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define SEM_CLK_CTRL__MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a ++#define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define SEM_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e ++#define SEM_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f ++#define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define SEM_CLK_CTRL__MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define SEM_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L ++#define SEM_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L ++//SEM_UTC_CREDIT ++#define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0 ++#define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8 ++#define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL ++#define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L ++//SEM_UTC_CONFIG ++#define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0 ++#define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3 ++#define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4 ++#define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5 ++#define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L ++#define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L ++#define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L ++#define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L ++//SEM_UTCL2_TRAN_EN_LUT ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0 ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1 ++#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2 ++#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3 ++#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4 ++#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5 ++#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6 ++#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7 ++#define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x8 ++#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L ++#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L ++#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L ++#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L ++#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L ++#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L ++#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L ++#define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFF00L ++#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L ++//SEM_MCIF_CONFIG ++#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 ++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 ++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 ++#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L ++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL ++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L ++//SEM_PERFMON_CNTL ++#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 ++#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 ++#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa ++#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb ++#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc ++#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L ++#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L ++#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL ++#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L ++#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L ++#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L ++//SEM_PERFCOUNTER0_RESULT ++#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SEM_PERFCOUNTER1_RESULT ++#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SEM_STATUS ++#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 ++#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 ++#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 ++#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 ++#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 ++#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 ++#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 ++#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 ++#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 ++#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 ++#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa ++#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb ++#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc ++#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd ++#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe ++#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf ++#define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10 ++#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11 ++#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12 ++#define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13 ++#define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14 ++#define SEM_STATUS__MIF_IDLE__SHIFT 0x15 ++#define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16 ++#define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17 ++#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f ++#define SEM_STATUS__SEM_IDLE_MASK 0x00000001L ++#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L ++#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L ++#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L ++#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L ++#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L ++#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L ++#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L ++#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L ++#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L ++#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L ++#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L ++#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L ++#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L ++#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L ++#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L ++#define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L ++#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L ++#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L ++#define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L ++#define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L ++#define SEM_STATUS__MIF_IDLE_MASK 0x00200000L ++#define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L ++#define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L ++#define SEM_STATUS__SWITCH_READY_MASK 0x80000000L ++//SEM_MAILBOX_CLIENTCONFIG ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc ++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 ++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L ++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L ++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L ++//SEM_MAILBOX ++#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 ++#define SEM_MAILBOX__RESERVED__SHIFT 0x10 ++#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL ++#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L ++//SEM_MAILBOX_CONTROL ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0 ++#define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10 ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL ++#define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L ++//SEM_CHICKEN_BITS ++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 ++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 ++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 ++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 ++#define SEM_CHICKEN_BITS__CLIENT_REQ_FCNID_CHECK__SHIFT 0x5 ++#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6 ++#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7 ++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 ++#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa ++#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc ++#define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe ++#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf ++#define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10 ++#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12 ++#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13 ++#define SEM_CHICKEN_BITS__VM_INV_FLUSH__SHIFT 0x14 ++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L ++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L ++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L ++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L ++#define SEM_CHICKEN_BITS__CLIENT_REQ_FCNID_CHECK_MASK 0x00000020L ++#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L ++#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L ++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L ++#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L ++#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L ++#define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L ++#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L ++#define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L ++#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L ++#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L ++#define SEM_CHICKEN_BITS__VM_INV_FLUSH_MASK 0x00100000L ++//SEM_MAILBOX_CLIENTCONFIG_EXTRA ++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 ++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL ++//SEM_GPU_IOV_VIOLATION_LOG ++#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 ++#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 ++#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 ++#define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 ++#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 ++#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L ++#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL ++#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L ++#define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L ++#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x01F00000L ++//SEM_OUTSTANDING_THRESHOLD ++#define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0 ++#define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL ++//SEM_MEM_POWER_CTRL ++#define SEM_MEM_POWER_CTRL__MEM_POWER_CTRL_EN__SHIFT 0x0 ++#define SEM_MEM_POWER_CTRL__MEM_POWER_LS_EN__SHIFT 0x1 ++#define SEM_MEM_POWER_CTRL__MEM_POWER_DS_EN__SHIFT 0x2 ++#define SEM_MEM_POWER_CTRL__MEM_POWER_SD_EN__SHIFT 0x3 ++#define SEM_MEM_POWER_CTRL__MEM_IDLE_HYSTERESIS__SHIFT 0x4 ++#define SEM_MEM_POWER_CTRL__MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 ++#define SEM_MEM_POWER_CTRL__MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe ++#define SEM_MEM_POWER_CTRL__MEM_POWER_CTRL_EN_MASK 0x00000001L ++#define SEM_MEM_POWER_CTRL__MEM_POWER_LS_EN_MASK 0x00000002L ++#define SEM_MEM_POWER_CTRL__MEM_POWER_DS_EN_MASK 0x00000004L ++#define SEM_MEM_POWER_CTRL__MEM_POWER_SD_EN_MASK 0x00000008L ++#define SEM_MEM_POWER_CTRL__MEM_IDLE_HYSTERESIS_MASK 0x00000070L ++#define SEM_MEM_POWER_CTRL__MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L ++#define SEM_MEM_POWER_CTRL__MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L ++//SEM_GPU_IOV_VIOLATION_LOG2 ++#define SEM_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 ++#define SEM_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL ++//SEM_REGISTER_LAST_PART2 ++#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 ++#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL ++//IH_ACTIVE_FCN_ID ++#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 ++#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 ++#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f ++#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL ++#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L ++#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L ++//IH_VIRT_RESET_REQ ++#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define IH_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL ++#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//IH_CLIENT_CFG ++#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 ++#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL ++//IH_CLIENT_CFG_INDEX ++#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 ++#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL ++//IH_CLIENT_CFG_DATA ++#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0 ++#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 ++#define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14 ++#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 ++#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 ++#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19 ++#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0003FFFFL ++#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L ++#define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L ++#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L ++#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L ++#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L ++//IH_CID_REMAP_INDEX ++#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 ++#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L ++//IH_CID_REMAP_DATA ++#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 ++#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 ++#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18 ++#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL ++#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L ++#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L ++//IH_CHICKEN ++#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 ++#define IH_CHICKEN__DBGU_TRIGGER_ENABLE__SHIFT 0x1 ++#define IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT 0x2 ++#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 ++#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 ++#define IH_CHICKEN__REG_FIREWALL_ENABLE__SHIFT 0x5 ++#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L ++#define IH_CHICKEN__DBGU_TRIGGER_ENABLE_MASK 0x00000002L ++#define IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK 0x00000004L ++#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L ++#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L ++#define IH_CHICKEN__REG_FIREWALL_ENABLE_MASK 0x00000020L ++//IH_MMHUB_CNTL ++#define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 ++#define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 ++#define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc ++#define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL ++#define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L ++#define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L ++//IH_INT_DROP_CNTL ++#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 ++#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 ++#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 ++#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 ++#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 ++#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 ++#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 ++#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 ++#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 ++#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L ++#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L ++#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L ++#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L ++#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L ++#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L ++#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L ++#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L ++#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L ++//IH_INT_DROP_MATCH_VALUE0 ++#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 ++#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 ++#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 ++#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 ++#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL ++#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L ++#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x001F0000L ++#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L ++#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L ++//IH_INT_DROP_MATCH_VALUE1 ++#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL ++//IH_INT_DROP_MATCH_MASK0 ++#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 ++#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 ++#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 ++#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 ++#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL ++#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L ++#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x001F0000L ++#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L ++#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L ++//IH_INT_DROP_MATCH_MASK1 ++#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL ++//IH_REGISTER_LAST_PART1 ++#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 ++#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL ++//SEM_ACTIVE_FCN_ID ++#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL ++#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//SEM_VIRT_RESET_REQ ++#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define SEM_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL ++#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//SEM_RESP_SDMA0 ++#define SEM_RESP_SDMA0__ADDR__SHIFT 0x0 ++#define SEM_RESP_SDMA0__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_SDMA1 ++#define SEM_RESP_SDMA1__ADDR__SHIFT 0x0 ++#define SEM_RESP_SDMA1__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_UVD ++#define SEM_RESP_UVD__ADDR__SHIFT 0x0 ++#define SEM_RESP_UVD__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_VCE_0 ++#define SEM_RESP_VCE_0__ADDR__SHIFT 0x0 ++#define SEM_RESP_VCE_0__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_ACP ++#define SEM_RESP_ACP__ADDR__SHIFT 0x0 ++#define SEM_RESP_ACP__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_ISP ++#define SEM_RESP_ISP__ADDR__SHIFT 0x0 ++#define SEM_RESP_ISP__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_VCE_1 ++#define SEM_RESP_VCE_1__ADDR__SHIFT 0x0 ++#define SEM_RESP_VCE_1__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_VP8 ++#define SEM_RESP_VP8__ADDR__SHIFT 0x0 ++#define SEM_RESP_VP8__ADDR_MASK 0x0FFFFFFFL ++//SEM_RESP_GC ++#define SEM_RESP_GC__ADDR__SHIFT 0x0 ++#define SEM_RESP_GC__ADDR_MASK 0x0FFFFFFFL ++//SEM_CID_REMAP_INDEX ++#define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0 ++#define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L ++//SEM_CID_REMAP_DATA ++#define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 ++#define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 ++#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18 ++#define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL ++#define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L ++#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L ++//SEM_ATOMIC_OP_LUT ++#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0 ++#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7 ++#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe ++#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15 ++#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL ++#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L ++#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L ++#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L ++//SEM_EDC_CONFIG ++#define SEM_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 ++#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 ++#define SEM_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L ++#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L ++//SEM_CHICKEN_BITS2 ++#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 ++#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1 ++#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L ++#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L ++//SEM_MMHUB_CNTL ++#define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 ++#define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8 ++#define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL ++#define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L ++//SEM_REGISTER_LAST_PART1 ++#define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 ++#define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL ++ ++#endif +-- +2.17.1 + |