diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2136-drm-amdgpu-add-MMHUB-2.0-register-headers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2136-drm-amdgpu-add-MMHUB-2.0-register-headers.patch | 10330 |
1 files changed, 10330 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2136-drm-amdgpu-add-MMHUB-2.0-register-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2136-drm-amdgpu-add-MMHUB-2.0-register-headers.patch new file mode 100644 index 00000000..b46328cf --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2136-drm-amdgpu-add-MMHUB-2.0-register-headers.patch @@ -0,0 +1,10330 @@ +From 9d24f6ea7d8b2441a3e86b7f740df79558a55660 Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Sun, 3 Mar 2019 11:29:18 +0800 +Subject: [PATCH 2136/2940] drm/amdgpu: add MMHUB 2.0 register headers + +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../asic_reg/mmhub/mmhub_2_0_0_default.h | 927 ++ + .../asic_reg/mmhub/mmhub_2_0_0_offset.h | 1799 ++++ + .../asic_reg/mmhub/mmhub_2_0_0_sh_mask.h | 7567 +++++++++++++++++ + 3 files changed, 10293 insertions(+) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h +new file mode 100644 +index 000000000000..5fca506ffede +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h +@@ -0,0 +1,927 @@ ++/* ++ * Copyright (C) 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _mmhub_2_0_0_DEFAULT_HEADER ++#define _mmhub_2_0_0_DEFAULT_HEADER ++ ++ ++// addressBlock: mmhub_dagbdec ++#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 ++#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x00003046 ++#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 ++#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 ++#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 ++#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 ++#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 ++#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 ++#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a0e408 ++#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 ++#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9 ++#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 ++#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x00003046 ++#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 ++#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 ++#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 ++#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 ++#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 ++#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 ++#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000 ++#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 ++#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a0e408 ++#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 ++#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x60606070 ++#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 ++#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_DEFAULT 0x00000000 ++#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_DEFAULT 0x00000000 ++#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 ++#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa ++#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 ++#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff ++#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 ++#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff ++#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff ++#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 ++#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 ++#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 ++#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 ++#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 ++#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 ++#define mmDAGB0_RESERVE0_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE1_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE2_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE3_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE4_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE5_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE6_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE7_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE8_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE9_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE10_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE11_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE12_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE13_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE14_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE15_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE16_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE17_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE18_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE19_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE20_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE21_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE22_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE23_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE24_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE25_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE26_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE27_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE28_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE29_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE30_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE31_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE32_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE33_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE34_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE35_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE36_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE37_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE38_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE39_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE40_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE41_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE42_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE43_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE44_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE45_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE46_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE47_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE48_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE49_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE50_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE51_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE52_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE53_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE54_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE55_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE56_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE57_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE58_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE59_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE60_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE61_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE62_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE63_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE64_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE65_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE66_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE67_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE68_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE69_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE70_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE71_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE72_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE73_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE74_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE75_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE76_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE77_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE78_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE79_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE80_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE81_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE82_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE83_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE84_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE85_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE86_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE87_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE88_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE89_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE90_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE91_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE92_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE93_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE94_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE95_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE96_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE97_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE98_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE99_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE100_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE101_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE102_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE103_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE104_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE105_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE106_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE107_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE108_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE109_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE110_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE111_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE112_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE113_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE114_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE115_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE116_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE117_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE118_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE119_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE120_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE121_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE122_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE123_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE124_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE125_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE126_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE127_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE128_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE129_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE130_DEFAULT 0xffffffff ++#define mmDAGB0_RESERVE131_DEFAULT 0xffffffff ++ ++ ++// addressBlock: mmhub_mmea_mmeadec ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 ++#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 ++#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 ++#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x78000924 ++#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x78000924 ++#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 ++#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 ++#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 ++#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 ++#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 ++#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 ++#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 ++#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 ++#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 ++#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 ++#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff ++#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef ++#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 ++#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 ++#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 ++#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 ++#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 ++#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 ++#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 ++#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 ++#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 ++#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 ++#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 ++#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 ++#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff ++#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff ++#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00101e40 ++#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff ++#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000101bf ++#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 ++#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f ++#define mmMMEA0_MISC_DEFAULT 0x0c00a070 ++#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 ++#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 ++#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 ++#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 ++#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 ++#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 ++#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 ++#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 ++#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 ++#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 ++#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 ++#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 ++#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 ++#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 ++#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 ++#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 ++#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000300 ++#define mmMMEA0_MISC2_DEFAULT 0x00000000 ++#define mmMMEA0_ADDRDEC_SELECT_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_pctldec ++#define mmPCTL_MISC_DEFAULT 0x00000889 ++#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 ++#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 ++#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 ++#define mmPCTL_PG_DAGB_DEFAULT 0x00000000 ++#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 ++#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 ++#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 ++#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 ++#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 ++#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 ++#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 ++#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 ++#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff ++#define mmPCTL0_MISC_DEFAULT 0x00011000 ++#define mmPCTL1_MISC_DEFAULT 0x00000800 ++#define mmPCTL2_MISC_DEFAULT 0x00000800 ++#define mmPCTL_PERFCOUNTER_LO_DEFAULT 0x00000000 ++#define mmPCTL_PERFCOUNTER_HI_DEFAULT 0x00000000 ++#define mmPCTL_PERFCOUNTER0_CFG_DEFAULT 0x00000000 ++#define mmPCTL_PERFCOUNTER1_CFG_DEFAULT 0x00000000 ++#define mmPCTL_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1pfdec ++#define mmMMMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1pldec ++#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1prdec ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2dec ++#define mmMM_ATC_L2_CNTL_DEFAULT 0x000001c0 ++#define mmMM_ATC_L2_CNTL2_DEFAULT 0x00000100 ++#define mmMM_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_CNTL3_DEFAULT 0x000001f8 ++#define mmMM_ATC_L2_STATUS_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_STATUS2_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_MISC_CG_DEFAULT 0x00000200 ++#define mmMM_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 ++#define mmMM_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 ++#define mmMM_ATC_L2_SDPPORT_CTRL_DEFAULT 0x000003ff ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2pfdec ++#define mmMMVM_L2_CNTL_DEFAULT 0x00080602 ++#define mmMMVM_L2_CNTL2_DEFAULT 0x00000000 ++#define mmMMVM_L2_CNTL3_DEFAULT 0x80100007 ++#define mmMMVM_L2_STATUS_DEFAULT 0x00000000 ++#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 ++#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_CNTL_DEFAULT 0x0000010f ++#define mmMMVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc ++#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 ++#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff ++#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff ++#define mmMMVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 ++#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 ++#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 ++#define mmMMVM_L2_CNTL4_DEFAULT 0x000000c1 ++#define mmMMVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 ++#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 ++#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 ++#define mmMMVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 ++#define mmMMVM_L2_IH_LOG_CNTL_DEFAULT 0x00000002 ++#define mmMMVM_L2_IH_LOG_BUSY_DEFAULT 0x00000000 ++#define mmMMVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 ++#define mmMMVM_L2_CNTL5_DEFAULT 0x00003fe0 ++#define mmMMVM_L2_GCR_CNTL_DEFAULT 0x00000000 ++#define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_DEFAULT 0x00000000 ++#define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000 ++#define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_DEFAULT 0x00000000 ++#define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2vcdec ++#define mmMMVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 ++#define mmMMVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG0_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG1_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG2_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG3_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG4_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG5_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG6_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG7_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG8_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG9_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG10_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG11_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG12_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG13_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG14_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG15_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG16_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG17_REQ_DEFAULT 0x02f80000 ++#define mmMMVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 ++#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2pldec ++#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2prdec ++#define mmMMMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 ++#define mmMMMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_DEFAULT 0x00000000 ++#define mmMMVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 ++#define mmMMMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 ++#define mmMMMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 ++#define mmMMVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 ++#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_16_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_17_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_18_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_19_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_20_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_21_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_22_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_23_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_24_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_25_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_26_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_27_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_28_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_29_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_30_DEFAULT 0x00000000 ++#define mmMMVM_PCIE_ATS_CNTL_VF_31_DEFAULT 0x00000000 ++#define mmMMUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 ++#define mmMMMC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec ++#define mmMMMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 ++#define mmMMMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 ++#define mmMMMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 ++#define mmMMMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 ++#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 ++#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 ++#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_OFFSET_DEFAULT 0x00000000 ++#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 ++#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 ++#define mmMMMC_VM_STEERING_DEFAULT 0x00000001 ++#define mmMMMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 ++#define mmMMMC_MEM_POWER_LS_DEFAULT 0x00000208 ++#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 ++#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 ++#define mmMMMC_VM_APT_CNTL_DEFAULT 0x00000000 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff ++#define mmMMMC_SHARED_VIRT_RESET_REQ2_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec ++#define mmMMMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 ++#define mmMMMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 ++#define mmMMMC_VM_AGP_TOP_DEFAULT 0x00000000 ++#define mmMMMC_VM_AGP_BOT_DEFAULT 0x00000000 ++#define mmMMMC_VM_AGP_BASE_DEFAULT 0x00000000 ++#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 ++#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 ++#define mmMMMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000501 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec ++#define mmMM_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec ++#define mmMM_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 ++#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h +new file mode 100644 +index 000000000000..7883a0140aa3 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h +@@ -0,0 +1,1799 @@ ++/* ++ * Copyright (C) 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _mmhub_2_0_0_OFFSET_HEADER ++#define _mmhub_2_0_0_OFFSET_HEADER ++ ++ ++ ++// addressBlock: mmhub_dagbdec ++// base address: 0x68000 ++#define mmDAGB0_RDCLI0 0x0000 ++#define mmDAGB0_RDCLI0_BASE_IDX 0 ++#define mmDAGB0_RDCLI1 0x0001 ++#define mmDAGB0_RDCLI1_BASE_IDX 0 ++#define mmDAGB0_RDCLI2 0x0002 ++#define mmDAGB0_RDCLI2_BASE_IDX 0 ++#define mmDAGB0_RDCLI3 0x0003 ++#define mmDAGB0_RDCLI3_BASE_IDX 0 ++#define mmDAGB0_RDCLI4 0x0004 ++#define mmDAGB0_RDCLI4_BASE_IDX 0 ++#define mmDAGB0_RDCLI5 0x0005 ++#define mmDAGB0_RDCLI5_BASE_IDX 0 ++#define mmDAGB0_RDCLI6 0x0006 ++#define mmDAGB0_RDCLI6_BASE_IDX 0 ++#define mmDAGB0_RDCLI7 0x0007 ++#define mmDAGB0_RDCLI7_BASE_IDX 0 ++#define mmDAGB0_RDCLI8 0x0008 ++#define mmDAGB0_RDCLI8_BASE_IDX 0 ++#define mmDAGB0_RDCLI9 0x0009 ++#define mmDAGB0_RDCLI9_BASE_IDX 0 ++#define mmDAGB0_RDCLI10 0x000a ++#define mmDAGB0_RDCLI10_BASE_IDX 0 ++#define mmDAGB0_RDCLI11 0x000b ++#define mmDAGB0_RDCLI11_BASE_IDX 0 ++#define mmDAGB0_RDCLI12 0x000c ++#define mmDAGB0_RDCLI12_BASE_IDX 0 ++#define mmDAGB0_RDCLI13 0x000d ++#define mmDAGB0_RDCLI13_BASE_IDX 0 ++#define mmDAGB0_RDCLI14 0x000e ++#define mmDAGB0_RDCLI14_BASE_IDX 0 ++#define mmDAGB0_RDCLI15 0x000f ++#define mmDAGB0_RDCLI15_BASE_IDX 0 ++#define mmDAGB0_RDCLI16 0x0010 ++#define mmDAGB0_RDCLI16_BASE_IDX 0 ++#define mmDAGB0_RDCLI17 0x0011 ++#define mmDAGB0_RDCLI17_BASE_IDX 0 ++#define mmDAGB0_RDCLI18 0x0012 ++#define mmDAGB0_RDCLI18_BASE_IDX 0 ++#define mmDAGB0_RD_CNTL 0x0013 ++#define mmDAGB0_RD_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_GMI_CNTL 0x0014 ++#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB 0x0015 ++#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 ++#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0016 ++#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 ++#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0017 ++#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 ++#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0018 ++#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0019 ++#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x001a ++#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001b ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001c ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001d ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001e ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x001f ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0020 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 ++#define mmDAGB0_RD_VC0_CNTL 0x0021 ++#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC1_CNTL 0x0022 ++#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC2_CNTL 0x0023 ++#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC3_CNTL 0x0024 ++#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC4_CNTL 0x0025 ++#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC5_CNTL 0x0026 ++#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC6_CNTL 0x0027 ++#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC7_CNTL 0x0028 ++#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_CNTL_MISC 0x0029 ++#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB0_RD_TLB_CREDIT 0x002a ++#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 ++#define mmDAGB0_RDCLI_ASK_PENDING 0x002b ++#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_GO_PENDING 0x002c ++#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x002d ++#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_TLB_PENDING 0x002e ++#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_OARB_PENDING 0x002f ++#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_OSD_PENDING 0x0030 ++#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI0 0x0031 ++#define mmDAGB0_WRCLI0_BASE_IDX 0 ++#define mmDAGB0_WRCLI1 0x0032 ++#define mmDAGB0_WRCLI1_BASE_IDX 0 ++#define mmDAGB0_WRCLI2 0x0033 ++#define mmDAGB0_WRCLI2_BASE_IDX 0 ++#define mmDAGB0_WRCLI3 0x0034 ++#define mmDAGB0_WRCLI3_BASE_IDX 0 ++#define mmDAGB0_WRCLI4 0x0035 ++#define mmDAGB0_WRCLI4_BASE_IDX 0 ++#define mmDAGB0_WRCLI5 0x0036 ++#define mmDAGB0_WRCLI5_BASE_IDX 0 ++#define mmDAGB0_WRCLI6 0x0037 ++#define mmDAGB0_WRCLI6_BASE_IDX 0 ++#define mmDAGB0_WRCLI7 0x0038 ++#define mmDAGB0_WRCLI7_BASE_IDX 0 ++#define mmDAGB0_WRCLI8 0x0039 ++#define mmDAGB0_WRCLI8_BASE_IDX 0 ++#define mmDAGB0_WRCLI9 0x003a ++#define mmDAGB0_WRCLI9_BASE_IDX 0 ++#define mmDAGB0_WRCLI10 0x003b ++#define mmDAGB0_WRCLI10_BASE_IDX 0 ++#define mmDAGB0_WRCLI11 0x003c ++#define mmDAGB0_WRCLI11_BASE_IDX 0 ++#define mmDAGB0_WRCLI12 0x003d ++#define mmDAGB0_WRCLI12_BASE_IDX 0 ++#define mmDAGB0_WRCLI13 0x003e ++#define mmDAGB0_WRCLI13_BASE_IDX 0 ++#define mmDAGB0_WRCLI14 0x003f ++#define mmDAGB0_WRCLI14_BASE_IDX 0 ++#define mmDAGB0_WRCLI15 0x0040 ++#define mmDAGB0_WRCLI15_BASE_IDX 0 ++#define mmDAGB0_WRCLI16 0x0041 ++#define mmDAGB0_WRCLI16_BASE_IDX 0 ++#define mmDAGB0_WRCLI17 0x0042 ++#define mmDAGB0_WRCLI17_BASE_IDX 0 ++#define mmDAGB0_WRCLI18 0x0043 ++#define mmDAGB0_WRCLI18_BASE_IDX 0 ++#define mmDAGB0_WR_CNTL 0x0044 ++#define mmDAGB0_WR_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_GMI_CNTL 0x0045 ++#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB 0x0046 ++#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 ++#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0047 ++#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 ++#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0048 ++#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 ++#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0049 ++#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x004a ++#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x004b ++#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x004c ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x004d ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x004e ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x004f ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0050 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0051 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB 0x0052 ++#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0053 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0054 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0055 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0056 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0057 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0058 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 ++#define mmDAGB0_WR_VC0_CNTL 0x0059 ++#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC1_CNTL 0x005a ++#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC2_CNTL 0x005b ++#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC3_CNTL 0x005c ++#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC4_CNTL 0x005d ++#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC5_CNTL 0x005e ++#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC6_CNTL 0x005f ++#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC7_CNTL 0x0060 ++#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_CNTL_MISC 0x0061 ++#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB0_WR_TLB_CREDIT 0x0062 ++#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_CREDIT 0x0063 ++#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 ++#define mmDAGB0_WR_MISC_CREDIT 0x0064 ++#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 ++#define mmDAGB0_WRCLI_ASK_PENDING 0x0065 ++#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_GO_PENDING 0x0066 ++#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x0067 ++#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_TLB_PENDING 0x0068 ++#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_OARB_PENDING 0x0069 ++#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_OSD_PENDING 0x006a ++#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x006b ++#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x006c ++#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x006d ++#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 ++#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x006e ++#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 ++#define mmDAGB0_DAGB_DLY 0x006f ++#define mmDAGB0_DAGB_DLY_BASE_IDX 0 ++#define mmDAGB0_CNTL_MISC 0x0070 ++#define mmDAGB0_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB0_CNTL_MISC2 0x0071 ++#define mmDAGB0_CNTL_MISC2_BASE_IDX 0 ++#define mmDAGB0_FIFO_EMPTY 0x0072 ++#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 ++#define mmDAGB0_FIFO_FULL 0x0073 ++#define mmDAGB0_FIFO_FULL_BASE_IDX 0 ++#define mmDAGB0_WR_CREDITS_FULL 0x0074 ++#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 ++#define mmDAGB0_RD_CREDITS_FULL 0x0075 ++#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER_LO 0x0076 ++#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER_HI 0x0077 ++#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER0_CFG 0x0078 ++#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER1_CFG 0x0079 ++#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER2_CFG 0x007a ++#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x007b ++#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++#define mmDAGB0_RESERVE0 0x007c ++#define mmDAGB0_RESERVE0_BASE_IDX 0 ++#define mmDAGB0_RESERVE1 0x007d ++#define mmDAGB0_RESERVE1_BASE_IDX 0 ++#define mmDAGB0_RESERVE2 0x007e ++#define mmDAGB0_RESERVE2_BASE_IDX 0 ++#define mmDAGB0_RESERVE3 0x007f ++#define mmDAGB0_RESERVE3_BASE_IDX 0 ++#define mmDAGB0_RESERVE4 0x0080 ++#define mmDAGB0_RESERVE4_BASE_IDX 0 ++#define mmDAGB0_RESERVE5 0x0081 ++#define mmDAGB0_RESERVE5_BASE_IDX 0 ++#define mmDAGB0_RESERVE6 0x0082 ++#define mmDAGB0_RESERVE6_BASE_IDX 0 ++#define mmDAGB0_RESERVE7 0x0083 ++#define mmDAGB0_RESERVE7_BASE_IDX 0 ++#define mmDAGB0_RESERVE8 0x0084 ++#define mmDAGB0_RESERVE8_BASE_IDX 0 ++#define mmDAGB0_RESERVE9 0x0085 ++#define mmDAGB0_RESERVE9_BASE_IDX 0 ++#define mmDAGB0_RESERVE10 0x0086 ++#define mmDAGB0_RESERVE10_BASE_IDX 0 ++#define mmDAGB0_RESERVE11 0x0087 ++#define mmDAGB0_RESERVE11_BASE_IDX 0 ++#define mmDAGB0_RESERVE12 0x0088 ++#define mmDAGB0_RESERVE12_BASE_IDX 0 ++#define mmDAGB0_RESERVE13 0x0089 ++#define mmDAGB0_RESERVE13_BASE_IDX 0 ++#define mmDAGB0_RESERVE14 0x008a ++#define mmDAGB0_RESERVE14_BASE_IDX 0 ++#define mmDAGB0_RESERVE15 0x008b ++#define mmDAGB0_RESERVE15_BASE_IDX 0 ++#define mmDAGB0_RESERVE16 0x008c ++#define mmDAGB0_RESERVE16_BASE_IDX 0 ++#define mmDAGB0_RESERVE17 0x008d ++#define mmDAGB0_RESERVE17_BASE_IDX 0 ++#define mmDAGB0_RESERVE18 0x008e ++#define mmDAGB0_RESERVE18_BASE_IDX 0 ++#define mmDAGB0_RESERVE19 0x008f ++#define mmDAGB0_RESERVE19_BASE_IDX 0 ++#define mmDAGB0_RESERVE20 0x0090 ++#define mmDAGB0_RESERVE20_BASE_IDX 0 ++#define mmDAGB0_RESERVE21 0x0091 ++#define mmDAGB0_RESERVE21_BASE_IDX 0 ++#define mmDAGB0_RESERVE22 0x0092 ++#define mmDAGB0_RESERVE22_BASE_IDX 0 ++#define mmDAGB0_RESERVE23 0x0093 ++#define mmDAGB0_RESERVE23_BASE_IDX 0 ++#define mmDAGB0_RESERVE24 0x0094 ++#define mmDAGB0_RESERVE24_BASE_IDX 0 ++#define mmDAGB0_RESERVE25 0x0095 ++#define mmDAGB0_RESERVE25_BASE_IDX 0 ++#define mmDAGB0_RESERVE26 0x0096 ++#define mmDAGB0_RESERVE26_BASE_IDX 0 ++#define mmDAGB0_RESERVE27 0x0097 ++#define mmDAGB0_RESERVE27_BASE_IDX 0 ++#define mmDAGB0_RESERVE28 0x0098 ++#define mmDAGB0_RESERVE28_BASE_IDX 0 ++#define mmDAGB0_RESERVE29 0x0099 ++#define mmDAGB0_RESERVE29_BASE_IDX 0 ++#define mmDAGB0_RESERVE30 0x009a ++#define mmDAGB0_RESERVE30_BASE_IDX 0 ++#define mmDAGB0_RESERVE31 0x009b ++#define mmDAGB0_RESERVE31_BASE_IDX 0 ++#define mmDAGB0_RESERVE32 0x009c ++#define mmDAGB0_RESERVE32_BASE_IDX 0 ++#define mmDAGB0_RESERVE33 0x009d ++#define mmDAGB0_RESERVE33_BASE_IDX 0 ++#define mmDAGB0_RESERVE34 0x009e ++#define mmDAGB0_RESERVE34_BASE_IDX 0 ++#define mmDAGB0_RESERVE35 0x009f ++#define mmDAGB0_RESERVE35_BASE_IDX 0 ++#define mmDAGB0_RESERVE36 0x00a0 ++#define mmDAGB0_RESERVE36_BASE_IDX 0 ++#define mmDAGB0_RESERVE37 0x00a1 ++#define mmDAGB0_RESERVE37_BASE_IDX 0 ++#define mmDAGB0_RESERVE38 0x00a2 ++#define mmDAGB0_RESERVE38_BASE_IDX 0 ++#define mmDAGB0_RESERVE39 0x00a3 ++#define mmDAGB0_RESERVE39_BASE_IDX 0 ++#define mmDAGB0_RESERVE40 0x00a4 ++#define mmDAGB0_RESERVE40_BASE_IDX 0 ++#define mmDAGB0_RESERVE41 0x00a5 ++#define mmDAGB0_RESERVE41_BASE_IDX 0 ++#define mmDAGB0_RESERVE42 0x00a6 ++#define mmDAGB0_RESERVE42_BASE_IDX 0 ++#define mmDAGB0_RESERVE43 0x00a7 ++#define mmDAGB0_RESERVE43_BASE_IDX 0 ++#define mmDAGB0_RESERVE44 0x00a8 ++#define mmDAGB0_RESERVE44_BASE_IDX 0 ++#define mmDAGB0_RESERVE45 0x00a9 ++#define mmDAGB0_RESERVE45_BASE_IDX 0 ++#define mmDAGB0_RESERVE46 0x00aa ++#define mmDAGB0_RESERVE46_BASE_IDX 0 ++#define mmDAGB0_RESERVE47 0x00ab ++#define mmDAGB0_RESERVE47_BASE_IDX 0 ++#define mmDAGB0_RESERVE48 0x00ac ++#define mmDAGB0_RESERVE48_BASE_IDX 0 ++#define mmDAGB0_RESERVE49 0x00ad ++#define mmDAGB0_RESERVE49_BASE_IDX 0 ++#define mmDAGB0_RESERVE50 0x00ae ++#define mmDAGB0_RESERVE50_BASE_IDX 0 ++#define mmDAGB0_RESERVE51 0x00af ++#define mmDAGB0_RESERVE51_BASE_IDX 0 ++#define mmDAGB0_RESERVE52 0x00b0 ++#define mmDAGB0_RESERVE52_BASE_IDX 0 ++#define mmDAGB0_RESERVE53 0x00b1 ++#define mmDAGB0_RESERVE53_BASE_IDX 0 ++#define mmDAGB0_RESERVE54 0x00b2 ++#define mmDAGB0_RESERVE54_BASE_IDX 0 ++#define mmDAGB0_RESERVE55 0x00b3 ++#define mmDAGB0_RESERVE55_BASE_IDX 0 ++#define mmDAGB0_RESERVE56 0x00b4 ++#define mmDAGB0_RESERVE56_BASE_IDX 0 ++#define mmDAGB0_RESERVE57 0x00b5 ++#define mmDAGB0_RESERVE57_BASE_IDX 0 ++#define mmDAGB0_RESERVE58 0x00b6 ++#define mmDAGB0_RESERVE58_BASE_IDX 0 ++#define mmDAGB0_RESERVE59 0x00b7 ++#define mmDAGB0_RESERVE59_BASE_IDX 0 ++#define mmDAGB0_RESERVE60 0x00b8 ++#define mmDAGB0_RESERVE60_BASE_IDX 0 ++#define mmDAGB0_RESERVE61 0x00b9 ++#define mmDAGB0_RESERVE61_BASE_IDX 0 ++#define mmDAGB0_RESERVE62 0x00ba ++#define mmDAGB0_RESERVE62_BASE_IDX 0 ++#define mmDAGB0_RESERVE63 0x00bb ++#define mmDAGB0_RESERVE63_BASE_IDX 0 ++#define mmDAGB0_RESERVE64 0x00bc ++#define mmDAGB0_RESERVE64_BASE_IDX 0 ++#define mmDAGB0_RESERVE65 0x00bd ++#define mmDAGB0_RESERVE65_BASE_IDX 0 ++#define mmDAGB0_RESERVE66 0x00be ++#define mmDAGB0_RESERVE66_BASE_IDX 0 ++#define mmDAGB0_RESERVE67 0x00bf ++#define mmDAGB0_RESERVE67_BASE_IDX 0 ++#define mmDAGB0_RESERVE68 0x00c0 ++#define mmDAGB0_RESERVE68_BASE_IDX 0 ++#define mmDAGB0_RESERVE69 0x00c1 ++#define mmDAGB0_RESERVE69_BASE_IDX 0 ++#define mmDAGB0_RESERVE70 0x00c2 ++#define mmDAGB0_RESERVE70_BASE_IDX 0 ++#define mmDAGB0_RESERVE71 0x00c3 ++#define mmDAGB0_RESERVE71_BASE_IDX 0 ++#define mmDAGB0_RESERVE72 0x00c4 ++#define mmDAGB0_RESERVE72_BASE_IDX 0 ++#define mmDAGB0_RESERVE73 0x00c5 ++#define mmDAGB0_RESERVE73_BASE_IDX 0 ++#define mmDAGB0_RESERVE74 0x00c6 ++#define mmDAGB0_RESERVE74_BASE_IDX 0 ++#define mmDAGB0_RESERVE75 0x00c7 ++#define mmDAGB0_RESERVE75_BASE_IDX 0 ++#define mmDAGB0_RESERVE76 0x00c8 ++#define mmDAGB0_RESERVE76_BASE_IDX 0 ++#define mmDAGB0_RESERVE77 0x00c9 ++#define mmDAGB0_RESERVE77_BASE_IDX 0 ++#define mmDAGB0_RESERVE78 0x00ca ++#define mmDAGB0_RESERVE78_BASE_IDX 0 ++#define mmDAGB0_RESERVE79 0x00cb ++#define mmDAGB0_RESERVE79_BASE_IDX 0 ++#define mmDAGB0_RESERVE80 0x00cc ++#define mmDAGB0_RESERVE80_BASE_IDX 0 ++#define mmDAGB0_RESERVE81 0x00cd ++#define mmDAGB0_RESERVE81_BASE_IDX 0 ++#define mmDAGB0_RESERVE82 0x00ce ++#define mmDAGB0_RESERVE82_BASE_IDX 0 ++#define mmDAGB0_RESERVE83 0x00cf ++#define mmDAGB0_RESERVE83_BASE_IDX 0 ++#define mmDAGB0_RESERVE84 0x00d0 ++#define mmDAGB0_RESERVE84_BASE_IDX 0 ++#define mmDAGB0_RESERVE85 0x00d1 ++#define mmDAGB0_RESERVE85_BASE_IDX 0 ++#define mmDAGB0_RESERVE86 0x00d2 ++#define mmDAGB0_RESERVE86_BASE_IDX 0 ++#define mmDAGB0_RESERVE87 0x00d3 ++#define mmDAGB0_RESERVE87_BASE_IDX 0 ++#define mmDAGB0_RESERVE88 0x00d4 ++#define mmDAGB0_RESERVE88_BASE_IDX 0 ++#define mmDAGB0_RESERVE89 0x00d5 ++#define mmDAGB0_RESERVE89_BASE_IDX 0 ++#define mmDAGB0_RESERVE90 0x00d6 ++#define mmDAGB0_RESERVE90_BASE_IDX 0 ++#define mmDAGB0_RESERVE91 0x00d7 ++#define mmDAGB0_RESERVE91_BASE_IDX 0 ++#define mmDAGB0_RESERVE92 0x00d8 ++#define mmDAGB0_RESERVE92_BASE_IDX 0 ++#define mmDAGB0_RESERVE93 0x00d9 ++#define mmDAGB0_RESERVE93_BASE_IDX 0 ++#define mmDAGB0_RESERVE94 0x00da ++#define mmDAGB0_RESERVE94_BASE_IDX 0 ++#define mmDAGB0_RESERVE95 0x00db ++#define mmDAGB0_RESERVE95_BASE_IDX 0 ++#define mmDAGB0_RESERVE96 0x00dc ++#define mmDAGB0_RESERVE96_BASE_IDX 0 ++#define mmDAGB0_RESERVE97 0x00dd ++#define mmDAGB0_RESERVE97_BASE_IDX 0 ++#define mmDAGB0_RESERVE98 0x00de ++#define mmDAGB0_RESERVE98_BASE_IDX 0 ++#define mmDAGB0_RESERVE99 0x00df ++#define mmDAGB0_RESERVE99_BASE_IDX 0 ++#define mmDAGB0_RESERVE100 0x00e0 ++#define mmDAGB0_RESERVE100_BASE_IDX 0 ++#define mmDAGB0_RESERVE101 0x00e1 ++#define mmDAGB0_RESERVE101_BASE_IDX 0 ++#define mmDAGB0_RESERVE102 0x00e2 ++#define mmDAGB0_RESERVE102_BASE_IDX 0 ++#define mmDAGB0_RESERVE103 0x00e3 ++#define mmDAGB0_RESERVE103_BASE_IDX 0 ++#define mmDAGB0_RESERVE104 0x00e4 ++#define mmDAGB0_RESERVE104_BASE_IDX 0 ++#define mmDAGB0_RESERVE105 0x00e5 ++#define mmDAGB0_RESERVE105_BASE_IDX 0 ++#define mmDAGB0_RESERVE106 0x00e6 ++#define mmDAGB0_RESERVE106_BASE_IDX 0 ++#define mmDAGB0_RESERVE107 0x00e7 ++#define mmDAGB0_RESERVE107_BASE_IDX 0 ++#define mmDAGB0_RESERVE108 0x00e8 ++#define mmDAGB0_RESERVE108_BASE_IDX 0 ++#define mmDAGB0_RESERVE109 0x00e9 ++#define mmDAGB0_RESERVE109_BASE_IDX 0 ++#define mmDAGB0_RESERVE110 0x00ea ++#define mmDAGB0_RESERVE110_BASE_IDX 0 ++#define mmDAGB0_RESERVE111 0x00eb ++#define mmDAGB0_RESERVE111_BASE_IDX 0 ++#define mmDAGB0_RESERVE112 0x00ec ++#define mmDAGB0_RESERVE112_BASE_IDX 0 ++#define mmDAGB0_RESERVE113 0x00ed ++#define mmDAGB0_RESERVE113_BASE_IDX 0 ++#define mmDAGB0_RESERVE114 0x00ee ++#define mmDAGB0_RESERVE114_BASE_IDX 0 ++#define mmDAGB0_RESERVE115 0x00ef ++#define mmDAGB0_RESERVE115_BASE_IDX 0 ++#define mmDAGB0_RESERVE116 0x00f0 ++#define mmDAGB0_RESERVE116_BASE_IDX 0 ++#define mmDAGB0_RESERVE117 0x00f1 ++#define mmDAGB0_RESERVE117_BASE_IDX 0 ++#define mmDAGB0_RESERVE118 0x00f2 ++#define mmDAGB0_RESERVE118_BASE_IDX 0 ++#define mmDAGB0_RESERVE119 0x00f3 ++#define mmDAGB0_RESERVE119_BASE_IDX 0 ++#define mmDAGB0_RESERVE120 0x00f4 ++#define mmDAGB0_RESERVE120_BASE_IDX 0 ++#define mmDAGB0_RESERVE121 0x00f5 ++#define mmDAGB0_RESERVE121_BASE_IDX 0 ++#define mmDAGB0_RESERVE122 0x00f6 ++#define mmDAGB0_RESERVE122_BASE_IDX 0 ++#define mmDAGB0_RESERVE123 0x00f7 ++#define mmDAGB0_RESERVE123_BASE_IDX 0 ++#define mmDAGB0_RESERVE124 0x00f8 ++#define mmDAGB0_RESERVE124_BASE_IDX 0 ++#define mmDAGB0_RESERVE125 0x00f9 ++#define mmDAGB0_RESERVE125_BASE_IDX 0 ++#define mmDAGB0_RESERVE126 0x00fa ++#define mmDAGB0_RESERVE126_BASE_IDX 0 ++#define mmDAGB0_RESERVE127 0x00fb ++#define mmDAGB0_RESERVE127_BASE_IDX 0 ++#define mmDAGB0_RESERVE128 0x00fc ++#define mmDAGB0_RESERVE128_BASE_IDX 0 ++#define mmDAGB0_RESERVE129 0x00fd ++#define mmDAGB0_RESERVE129_BASE_IDX 0 ++#define mmDAGB0_RESERVE130 0x00fe ++#define mmDAGB0_RESERVE130_BASE_IDX 0 ++#define mmDAGB0_RESERVE131 0x00ff ++#define mmDAGB0_RESERVE131_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmea_mmeadec ++// base address: 0x68400 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 ++#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 ++#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_LAZY 0x0106 ++#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_LAZY 0x0107 ++#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 ++#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 ++#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 ++#define mmMMEA0_DRAM_PAGE_BURST 0x010a ++#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b ++#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c ++#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d ++#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e ++#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f ++#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 ++#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 ++#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 ++#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134 ++#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136 ++#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138 ++#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 ++#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143 ++#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 ++#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0145 ++#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC_BANK_CFG 0x0147 ++#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC_MISC_CFG 0x0148 ++#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014e ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014f ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0150 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0151 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0152 ++#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 0x0153 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 0x0154 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 0x0155 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 0x0156 ++#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0165 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0166 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0167 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0168 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0169 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x016a ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x016b ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x016c ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x016d ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x016e ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x016f ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0170 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0171 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0172 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0173 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0174 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0175 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0176 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0177 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0178 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x0179 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x017a ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x017b ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x017c ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x017d ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x017e ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x017f ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0180 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0181 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0182 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0183 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0184 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0185 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0186 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0187 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0188 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0189 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x018a ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x018b ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x018c ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x018d ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x018e ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x018f ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0190 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0191 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0192 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0193 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0194 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01dd ++#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01de ++#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01df ++#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01e0 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01e1 ++#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 ++#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01e2 ++#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 ++#define mmMMEA0_IO_GROUP_BURST 0x01e3 ++#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_AGE 0x01e4 ++#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_AGE 0x01e5 ++#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUEUING 0x01e6 ++#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUEUING 0x01e7 ++#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_FIXED 0x01e8 ++#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_FIXED 0x01e9 ++#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_URGENCY 0x01ea ++#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_URGENCY 0x01eb ++#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x01ec ++#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x01ed ++#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01ee ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01ef ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01f0 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01f1 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01f2 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01f3 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_SDP_ARB_DRAM 0x01f4 ++#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 ++#define mmMMEA0_SDP_ARB_FINAL 0x01f6 ++#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 ++#define mmMMEA0_SDP_DRAM_PRIORITY 0x01f7 ++#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 ++#define mmMMEA0_SDP_IO_PRIORITY 0x01f9 ++#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 ++#define mmMMEA0_SDP_CREDITS 0x01fa ++#define mmMMEA0_SDP_CREDITS_BASE_IDX 0 ++#define mmMMEA0_SDP_TAG_RESERVE0 0x01fb ++#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 ++#define mmMMEA0_SDP_TAG_RESERVE1 0x01fc ++#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 ++#define mmMMEA0_SDP_VCC_RESERVE0 0x01fd ++#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 ++#define mmMMEA0_SDP_VCC_RESERVE1 0x01fe ++#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 ++#define mmMMEA0_SDP_VCD_RESERVE0 0x01ff ++#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 ++#define mmMMEA0_SDP_VCD_RESERVE1 0x0200 ++#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 ++#define mmMMEA0_SDP_REQ_CNTL 0x0201 ++#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 ++#define mmMMEA0_MISC 0x0202 ++#define mmMMEA0_MISC_BASE_IDX 0 ++#define mmMMEA0_LATENCY_SAMPLING 0x0203 ++#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER_LO 0x0204 ++#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER_HI 0x0205 ++#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER0_CFG 0x0206 ++#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER1_CFG 0x0207 ++#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0208 ++#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++#define mmMMEA0_EDC_CNT 0x020f ++#define mmMMEA0_EDC_CNT_BASE_IDX 0 ++#define mmMMEA0_EDC_CNT2 0x0210 ++#define mmMMEA0_EDC_CNT2_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL 0x0211 ++#define mmMMEA0_DSM_CNTL_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTLA 0x0212 ++#define mmMMEA0_DSM_CNTLA_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTLB 0x0213 ++#define mmMMEA0_DSM_CNTLB_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL2 0x0214 ++#define mmMMEA0_DSM_CNTL2_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL2A 0x0215 ++#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL2B 0x0216 ++#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 ++#define mmMMEA0_CGTT_CLK_CTRL 0x0218 ++#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmMMEA0_EDC_MODE 0x0219 ++#define mmMMEA0_EDC_MODE_BASE_IDX 0 ++#define mmMMEA0_ERR_STATUS 0x021a ++#define mmMMEA0_ERR_STATUS_BASE_IDX 0 ++#define mmMMEA0_MISC2 0x021b ++#define mmMMEA0_MISC2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC_SELECT 0x021c ++#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_pctldec ++// base address: 0x68e00 ++#define mmPCTL_MISC 0x0380 ++#define mmPCTL_MISC_BASE_IDX 0 ++#define mmPCTL_MMHUB_DEEPSLEEP 0x0381 ++#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 ++#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 ++#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 ++#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 ++#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 ++#define mmPCTL_PG_DAGB 0x0384 ++#define mmPCTL_PG_DAGB_BASE_IDX 0 ++#define mmPCTL0_RENG_RAM_INDEX 0x0385 ++#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 ++#define mmPCTL0_RENG_RAM_DATA 0x0386 ++#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 ++#define mmPCTL0_RENG_EXECUTE 0x0387 ++#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 ++#define mmPCTL1_RENG_RAM_INDEX 0x0388 ++#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 ++#define mmPCTL1_RENG_RAM_DATA 0x0389 ++#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 ++#define mmPCTL1_RENG_EXECUTE 0x038a ++#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 ++#define mmPCTL2_RENG_RAM_INDEX 0x038b ++#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 ++#define mmPCTL2_RENG_RAM_DATA 0x038c ++#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 ++#define mmPCTL2_RENG_EXECUTE 0x038d ++#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x038e ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038f ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x0390 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3 0x0391 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4 0x0392 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x0393 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0394 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0395 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0396 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0397 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3 0x0398 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4 0x0399 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x039a ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039b ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039c ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039d ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039e ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3 0x039f ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4 0x03a0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x03a1 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a2 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 ++#define mmPCTL0_MISC 0x03a3 ++#define mmPCTL0_MISC_BASE_IDX 0 ++#define mmPCTL1_MISC 0x03a4 ++#define mmPCTL1_MISC_BASE_IDX 0 ++#define mmPCTL2_MISC 0x03a5 ++#define mmPCTL2_MISC_BASE_IDX 0 ++#define mmPCTL_PERFCOUNTER_LO 0x03a6 ++#define mmPCTL_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmPCTL_PERFCOUNTER_HI 0x03a7 ++#define mmPCTL_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmPCTL_PERFCOUNTER0_CFG 0x03a8 ++#define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmPCTL_PERFCOUNTER1_CFG 0x03a9 ++#define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmPCTL_PERFCOUNTER_RSLT_CNTL 0x03aa ++#define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1pfdec ++// base address: 0x69600 ++#define mmMMMC_VM_MX_L1_TLB0_STATUS 0x0588 ++#define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB1_STATUS 0x0589 ++#define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB2_STATUS 0x058a ++#define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB3_STATUS 0x058b ++#define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB4_STATUS 0x058c ++#define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB5_STATUS 0x058d ++#define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB6_STATUS 0x058e ++#define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB7_STATUS 0x058f ++#define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1pldec ++// base address: 0x69650 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1prdec ++// base address: 0x69670 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO 0x059c ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI 0x059d ++#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2dec ++// base address: 0x69900 ++#define mmMM_ATC_L2_CNTL 0x0640 ++#define mmMM_ATC_L2_CNTL_BASE_IDX 0 ++#define mmMM_ATC_L2_CNTL2 0x0641 ++#define mmMM_ATC_L2_CNTL2_BASE_IDX 0 ++#define mmMM_ATC_L2_CACHE_DATA0 0x0644 ++#define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX 0 ++#define mmMM_ATC_L2_CACHE_DATA1 0x0645 ++#define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX 0 ++#define mmMM_ATC_L2_CACHE_DATA2 0x0646 ++#define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX 0 ++#define mmMM_ATC_L2_CNTL3 0x0647 ++#define mmMM_ATC_L2_CNTL3_BASE_IDX 0 ++#define mmMM_ATC_L2_STATUS 0x0648 ++#define mmMM_ATC_L2_STATUS_BASE_IDX 0 ++#define mmMM_ATC_L2_STATUS2 0x0649 ++#define mmMM_ATC_L2_STATUS2_BASE_IDX 0 ++#define mmMM_ATC_L2_MISC_CG 0x064a ++#define mmMM_ATC_L2_MISC_CG_BASE_IDX 0 ++#define mmMM_ATC_L2_MEM_POWER_LS 0x064b ++#define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX 0 ++#define mmMM_ATC_L2_CGTT_CLK_CTRL 0x064c ++#define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmMM_ATC_L2_SDPPORT_CTRL 0x064d ++#define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2pfdec ++// base address: 0x69a00 ++#define mmMMVM_L2_CNTL 0x0680 ++#define mmMMVM_L2_CNTL_BASE_IDX 0 ++#define mmMMVM_L2_CNTL2 0x0681 ++#define mmMMVM_L2_CNTL2_BASE_IDX 0 ++#define mmMMVM_L2_CNTL3 0x0682 ++#define mmMMVM_L2_CNTL3_BASE_IDX 0 ++#define mmMMVM_L2_STATUS 0x0683 ++#define mmMMVM_L2_STATUS_BASE_IDX 0 ++#define mmMMVM_DUMMY_PAGE_FAULT_CNTL 0x0684 ++#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 ++#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 ++#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 ++#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_CNTL 0x0687 ++#define mmMMVM_INVALIDATE_CNTL_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_CNTL 0x0688 ++#define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_CNTL2 0x0689 ++#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x068a ++#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068b ++#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_STATUS 0x068c ++#define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068d ++#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068e ++#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068f ++#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0690 ++#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0692 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0693 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0694 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0695 ++#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0696 ++#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 ++#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0697 ++#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 ++#define mmMMVM_L2_CNTL4 0x0698 ++#define mmMMVM_L2_CNTL4_BASE_IDX 0 ++#define mmMMVM_L2_MM_GROUP_RT_CLASSES 0x0699 ++#define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 ++#define mmMMVM_L2_BANK_SELECT_RESERVED_CID 0x069a ++#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 ++#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2 0x069b ++#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 ++#define mmMMVM_L2_CACHE_PARITY_CNTL 0x069c ++#define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 ++#define mmMMVM_L2_IH_LOG_CNTL 0x069d ++#define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX 0 ++#define mmMMVM_L2_IH_LOG_BUSY 0x069e ++#define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX 0 ++#define mmMMVM_L2_CGTT_CLK_CTRL 0x069f ++#define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmMMVM_L2_CNTL5 0x06a1 ++#define mmMMVM_L2_CNTL5_BASE_IDX 0 ++#define mmMMVM_L2_GCR_CNTL 0x06a2 ++#define mmMMVM_L2_GCR_CNTL_BASE_IDX 0 ++#define mmMMVML2_WALKER_MACRO_THROTTLE_TIME 0x06a3 ++#define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 ++#define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x06a4 ++#define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 ++#define mmMMVML2_WALKER_MICRO_THROTTLE_TIME 0x06a5 ++#define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 ++#define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x06a6 ++#define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2vcdec ++// base address: 0x69b00 ++#define mmMMVM_CONTEXT0_CNTL 0x06c0 ++#define mmMMVM_CONTEXT0_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT1_CNTL 0x06c1 ++#define mmMMVM_CONTEXT1_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT2_CNTL 0x06c2 ++#define mmMMVM_CONTEXT2_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT3_CNTL 0x06c3 ++#define mmMMVM_CONTEXT3_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT4_CNTL 0x06c4 ++#define mmMMVM_CONTEXT4_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT5_CNTL 0x06c5 ++#define mmMMVM_CONTEXT5_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT6_CNTL 0x06c6 ++#define mmMMVM_CONTEXT6_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT7_CNTL 0x06c7 ++#define mmMMVM_CONTEXT7_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT8_CNTL 0x06c8 ++#define mmMMVM_CONTEXT8_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT9_CNTL 0x06c9 ++#define mmMMVM_CONTEXT9_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT10_CNTL 0x06ca ++#define mmMMVM_CONTEXT10_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT11_CNTL 0x06cb ++#define mmMMVM_CONTEXT11_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT12_CNTL 0x06cc ++#define mmMMVM_CONTEXT12_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT13_CNTL 0x06cd ++#define mmMMVM_CONTEXT13_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT14_CNTL 0x06ce ++#define mmMMVM_CONTEXT14_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXT15_CNTL 0x06cf ++#define mmMMVM_CONTEXT15_CNTL_BASE_IDX 0 ++#define mmMMVM_CONTEXTS_DISABLE 0x06d0 ++#define mmMMVM_CONTEXTS_DISABLE_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG0_SEM 0x06d1 ++#define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG1_SEM 0x06d2 ++#define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG2_SEM 0x06d3 ++#define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG3_SEM 0x06d4 ++#define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG4_SEM 0x06d5 ++#define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG5_SEM 0x06d6 ++#define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG6_SEM 0x06d7 ++#define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG7_SEM 0x06d8 ++#define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG8_SEM 0x06d9 ++#define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG9_SEM 0x06da ++#define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG10_SEM 0x06db ++#define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG11_SEM 0x06dc ++#define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG12_SEM 0x06dd ++#define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG13_SEM 0x06de ++#define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG14_SEM 0x06df ++#define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG15_SEM 0x06e0 ++#define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG16_SEM 0x06e1 ++#define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG17_SEM 0x06e2 ++#define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG0_REQ 0x06e3 ++#define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG1_REQ 0x06e4 ++#define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG2_REQ 0x06e5 ++#define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG3_REQ 0x06e6 ++#define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG4_REQ 0x06e7 ++#define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG5_REQ 0x06e8 ++#define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG6_REQ 0x06e9 ++#define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG7_REQ 0x06ea ++#define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG8_REQ 0x06eb ++#define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG9_REQ 0x06ec ++#define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG10_REQ 0x06ed ++#define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG11_REQ 0x06ee ++#define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG12_REQ 0x06ef ++#define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG13_REQ 0x06f0 ++#define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG14_REQ 0x06f1 ++#define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG15_REQ 0x06f2 ++#define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG16_REQ 0x06f3 ++#define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG17_REQ 0x06f4 ++#define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG0_ACK 0x06f5 ++#define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG1_ACK 0x06f6 ++#define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG2_ACK 0x06f7 ++#define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG3_ACK 0x06f8 ++#define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG4_ACK 0x06f9 ++#define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG5_ACK 0x06fa ++#define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG6_ACK 0x06fb ++#define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG7_ACK 0x06fc ++#define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG8_ACK 0x06fd ++#define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG9_ACK 0x06fe ++#define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG10_ACK 0x06ff ++#define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG11_ACK 0x0700 ++#define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG12_ACK 0x0701 ++#define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG13_ACK 0x0702 ++#define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG14_ACK 0x0703 ++#define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG15_ACK 0x0704 ++#define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG16_ACK 0x0705 ++#define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG17_ACK 0x0706 ++#define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 ++#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 ++#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 ++#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a ++#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b ++#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c ++#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d ++#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e ++#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f ++#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 ++#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 ++#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 ++#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 ++#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 ++#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 ++#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 ++#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 ++#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 ++#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 ++#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a ++#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b ++#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c ++#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d ++#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e ++#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f ++#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 ++#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 ++#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 ++#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 ++#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 ++#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 ++#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 ++#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 ++#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 ++#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 ++#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a ++#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b ++#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c ++#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d ++#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e ++#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f ++#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a ++#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b ++#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c ++#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d ++#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e ++#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f ++#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a ++#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b ++#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c ++#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d ++#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e ++#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f ++#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a ++#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b ++#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c ++#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d ++#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e ++#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f ++#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a ++#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b ++#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c ++#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d ++#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e ++#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f ++#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 ++#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 ++#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 ++#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 ++#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 ++#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a ++#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b ++#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c ++#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d ++#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e ++#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f ++#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 ++#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 ++#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 ++#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 ++#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 ++#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a ++#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2pldec ++// base address: 0x69e90 ++#define mmMMMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 ++#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 ++#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 ++#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 ++#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 ++#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 ++#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER6_CFG 0x07aa ++#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER7_CFG 0x07ab ++#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac ++#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2prdec ++// base address: 0x69ee0 ++#define mmMMMC_VM_L2_PERFCOUNTER_LO 0x07b8 ++#define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMMMC_VM_L2_PERFCOUNTER_HI 0x07b9 ++#define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec ++// base address: 0x69f30 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF0 0x07cc ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF1 0x07cd ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF2 0x07ce ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF3 0x07cf ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF14 0x07da ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF15 0x07db ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF16 0x07dc ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF17 0x07dd ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF18 0x07de ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF19 0x07df ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF20 0x07e0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF21 0x07e1 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF22 0x07e2 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF23 0x07e3 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF24 0x07e4 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF25 0x07e5 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF26 0x07e6 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF27 0x07e7 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF28 0x07e8 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF29 0x07e9 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF30 0x07ea ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 0 ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF31 0x07eb ++#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 0 ++#define mmMMVM_IOMMU_MMIO_CNTRL_1 0x07ec ++#define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_LO_0 0x07ed ++#define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_LO_1 0x07ee ++#define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_LO_2 0x07ef ++#define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_LO_3 0x07f0 ++#define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_HI_0 0x07f1 ++#define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_HI_1 0x07f2 ++#define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_HI_2 0x07f3 ++#define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX 0 ++#define mmMMMC_VM_MARC_BASE_HI_3 0x07f4 ++#define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_LO_0 0x07f5 ++#define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_LO_1 0x07f6 ++#define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_LO_2 0x07f7 ++#define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_LO_3 0x07f8 ++#define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_HI_0 0x07f9 ++#define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_HI_1 0x07fa ++#define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_HI_2 0x07fb ++#define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 ++#define mmMMMC_VM_MARC_RELOC_HI_3 0x07fc ++#define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_LO_0 0x07fd ++#define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_LO_1 0x07fe ++#define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_LO_2 0x07ff ++#define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_LO_3 0x0800 ++#define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_HI_0 0x0801 ++#define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_HI_1 0x0802 ++#define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_HI_2 0x0803 ++#define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX 0 ++#define mmMMMC_VM_MARC_LEN_HI_3 0x0804 ++#define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX 0 ++#define mmMMVM_IOMMU_CONTROL_REGISTER 0x0805 ++#define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 ++#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0806 ++#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL 0x0807 ++#define mmMMVM_PCIE_ATS_CNTL_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_0 0x0808 ++#define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_1 0x0809 ++#define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_2 0x080a ++#define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_3 0x080b ++#define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_4 0x080c ++#define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_5 0x080d ++#define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_6 0x080e ++#define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_7 0x080f ++#define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_8 0x0810 ++#define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_9 0x0811 ++#define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_10 0x0812 ++#define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_11 0x0813 ++#define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_12 0x0814 ++#define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_13 0x0815 ++#define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_14 0x0816 ++#define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_15 0x0817 ++#define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_16 0x0818 ++#define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_17 0x0819 ++#define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_18 0x081a ++#define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_19 0x081b ++#define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_20 0x081c ++#define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_21 0x081d ++#define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_22 0x081e ++#define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_23 0x081f ++#define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_24 0x0820 ++#define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_25 0x0821 ++#define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_26 0x0822 ++#define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_27 0x0823 ++#define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_28 0x0824 ++#define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_29 0x0825 ++#define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_30 0x0826 ++#define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX 0 ++#define mmMMVM_PCIE_ATS_CNTL_VF_31 0x0827 ++#define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX 0 ++#define mmMMUTCL2_CGTT_CLK_CTRL 0x0828 ++#define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmMMMC_SHARED_ACTIVE_FCN_ID 0x0829 ++#define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec ++// base address: 0x6a140 ++#define mmMMMC_VM_NB_MMIOBASE 0x0850 ++#define mmMMMC_VM_NB_MMIOBASE_BASE_IDX 0 ++#define mmMMMC_VM_NB_MMIOLIMIT 0x0851 ++#define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX 0 ++#define mmMMMC_VM_NB_PCI_CTRL 0x0852 ++#define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX 0 ++#define mmMMMC_VM_NB_PCI_ARB 0x0853 ++#define mmMMMC_VM_NB_PCI_ARB_BASE_IDX 0 ++#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0854 ++#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 ++#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0855 ++#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 ++#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0856 ++#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 ++#define mmMMMC_VM_FB_OFFSET 0x0857 ++#define mmMMMC_VM_FB_OFFSET_BASE_IDX 0 ++#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0858 ++#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 ++#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0859 ++#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 ++#define mmMMMC_VM_STEERING 0x085a ++#define mmMMMC_VM_STEERING_BASE_IDX 0 ++#define mmMMMC_SHARED_VIRT_RESET_REQ 0x085b ++#define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmMMMC_MEM_POWER_LS 0x085c ++#define mmMMMC_MEM_POWER_LS_BASE_IDX 0 ++#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x085d ++#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 ++#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x085e ++#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 ++#define mmMMMC_VM_APT_CNTL 0x085f ++#define mmMMMC_VM_APT_CNTL_BASE_IDX 0 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0860 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START 0x0861 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END 0x0862 ++#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 ++#define mmMMMC_SHARED_VIRT_RESET_REQ2 0x0863 ++#define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec ++// base address: 0x6a1b0 ++#define mmMMMC_VM_FB_LOCATION_BASE 0x086c ++#define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0 ++#define mmMMMC_VM_FB_LOCATION_TOP 0x086d ++#define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0 ++#define mmMMMC_VM_AGP_TOP 0x086e ++#define mmMMMC_VM_AGP_TOP_BASE_IDX 0 ++#define mmMMMC_VM_AGP_BOT 0x086f ++#define mmMMMC_VM_AGP_BOT_BASE_IDX 0 ++#define mmMMMC_VM_AGP_BASE 0x0870 ++#define mmMMMC_VM_AGP_BASE_BASE_IDX 0 ++#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0871 ++#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 ++#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0872 ++#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 ++#define mmMMMC_VM_MX_L1_TLB_CNTL 0x0873 ++#define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec ++// base address: 0x6a200 ++#define mmMM_ATC_L2_PERFCOUNTER_LO 0x0880 ++#define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMM_ATC_L2_PERFCOUNTER_HI 0x0881 ++#define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec ++// base address: 0x6a220 ++#define mmMM_ATC_L2_PERFCOUNTER0_CFG 0x0888 ++#define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMM_ATC_L2_PERFCOUNTER1_CFG 0x0889 ++#define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x088a ++#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h +new file mode 100644 +index 000000000000..0a0a889cc405 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h +@@ -0,0 +1,7567 @@ ++/* ++ * Copyright (C) 2019 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _mmhub_2_0_0_SH_MASK_HEADER ++#define _mmhub_2_0_0_SH_MASK_HEADER ++ ++ ++// addressBlock: mmhub_dagbdec ++//DAGB0_RDCLI0 ++#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI1 ++#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI2 ++#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI3 ++#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI4 ++#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI5 ++#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI6 ++#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI7 ++#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI8 ++#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI9 ++#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI10 ++#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI11 ++#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI12 ++#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI13 ++#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI14 ++#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI15 ++#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI16 ++#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI17 ++#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI18 ++#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RD_CNTL ++#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 ++#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 ++#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa ++#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 ++#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 ++#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 ++#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 ++#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL ++#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L ++#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L ++#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L ++#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L ++#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L ++#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L ++//DAGB0_RD_GMI_CNTL ++#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 ++#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 ++#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd ++#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL ++#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L ++#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L ++#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L ++//DAGB0_RD_ADDR_DAGB ++#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB0_RD_OUTPUT_DAGB_MAX_BURST ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L ++//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L ++//DAGB0_RD_CGTT_CLK_CTRL ++#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_L1TLB_RD_CGTT_CLK_CTRL ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_ATCVM_RD_CGTT_CLK_CTRL ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_RD_ADDR_DAGB_MAX_BURST0 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_MAX_BURST1 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_MAX_BURST2 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L ++//DAGB0_RD_VC0_CNTL ++#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC1_CNTL ++#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC2_CNTL ++#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC3_CNTL ++#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC4_CNTL ++#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC5_CNTL ++#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC6_CNTL ++#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC7_CNTL ++#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_CNTL_MISC ++#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 ++#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd ++#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 ++#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 ++#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 ++#define DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT 0x1a ++#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL ++#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L ++#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L ++#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L ++#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L ++#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L ++#define DAGB0_RD_CNTL_MISC__HDP_CID_MASK 0x7C000000L ++//DAGB0_RD_TLB_CREDIT ++#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 ++#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 ++#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa ++#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf ++#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 ++#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 ++#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL ++#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L ++#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L ++#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L ++#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L ++#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L ++//DAGB0_RDCLI_ASK_PENDING ++#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_GO_PENDING ++#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_GBLSEND_PENDING ++#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_TLB_PENDING ++#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_OARB_PENDING ++#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_OSD_PENDING ++#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI0 ++#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI1 ++#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI2 ++#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI3 ++#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI4 ++#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI5 ++#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI6 ++#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI7 ++#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI8 ++#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI9 ++#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI10 ++#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI11 ++#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI12 ++#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI13 ++#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI14 ++#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI15 ++#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI16 ++#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI17 ++#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI18 ++#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WR_CNTL ++#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 ++#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 ++#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa ++#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 ++#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 ++#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 ++#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 ++#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL ++#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L ++#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L ++#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L ++#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L ++#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L ++#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L ++//DAGB0_WR_GMI_CNTL ++#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 ++#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 ++#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd ++#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL ++#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L ++#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L ++#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L ++//DAGB0_WR_ADDR_DAGB ++#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB0_WR_OUTPUT_DAGB_MAX_BURST ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L ++//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L ++//DAGB0_WR_CGTT_CLK_CTRL ++#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_L1TLB_WR_CGTT_CLK_CTRL ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_ATCVM_WR_CGTT_CLK_CTRL ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_WR_ADDR_DAGB_MAX_BURST0 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_MAX_BURST1 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_MAX_BURST2 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB ++#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB0_WR_DATA_DAGB_MAX_BURST0 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_MAX_BURST1 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_MAX_BURST2 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L ++//DAGB0_WR_VC0_CNTL ++#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC1_CNTL ++#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC2_CNTL ++#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC3_CNTL ++#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC4_CNTL ++#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC5_CNTL ++#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC6_CNTL ++#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC7_CNTL ++#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_CNTL_MISC ++#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 ++#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd ++#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 ++#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 ++#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 ++#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x1a ++#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL ++#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L ++#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L ++#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L ++#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L ++#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L ++#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x7C000000L ++//DAGB0_WR_TLB_CREDIT ++#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 ++#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 ++#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa ++#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf ++#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 ++#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 ++#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL ++#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L ++#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L ++#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L ++#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L ++#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L ++//DAGB0_WR_DATA_CREDIT ++#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 ++#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 ++#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 ++#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 ++#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL ++#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L ++#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L ++#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L ++//DAGB0_WR_MISC_CREDIT ++#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 ++#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 ++#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 ++#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL ++#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L ++#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L ++#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L ++//DAGB0_WRCLI_ASK_PENDING ++#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_GO_PENDING ++#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_GBLSEND_PENDING ++#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_TLB_PENDING ++#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_OARB_PENDING ++#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_OSD_PENDING ++#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_DBUS_ASK_PENDING ++#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_DBUS_GO_PENDING ++#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE ++#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 ++#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE ++#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 ++#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL ++//DAGB0_DAGB_DLY ++#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 ++#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 ++#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 ++#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL ++#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L ++#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L ++//DAGB0_CNTL_MISC ++#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 ++#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 ++#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 ++#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 ++#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc ++#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf ++#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 ++#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 ++#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 ++#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e ++#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L ++#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L ++#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L ++#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L ++#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L ++#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L ++#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L ++#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L ++#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L ++#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L ++//DAGB0_CNTL_MISC2 ++#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 ++#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 ++#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 ++#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 ++#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 ++#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 ++#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 ++#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 ++#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 ++#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 ++#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa ++#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0xb ++#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L ++#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L ++#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L ++#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L ++#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L ++#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L ++#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L ++#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L ++#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L ++#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L ++#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L ++#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000800L ++//DAGB0_FIFO_EMPTY ++#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 ++#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL ++//DAGB0_FIFO_FULL ++#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 ++#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL ++//DAGB0_WR_CREDITS_FULL ++#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 ++#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL ++//DAGB0_RD_CREDITS_FULL ++#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 ++#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL ++//DAGB0_PERFCOUNTER_LO ++#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//DAGB0_PERFCOUNTER_HI ++#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//DAGB0_PERFCOUNTER0_CFG ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//DAGB0_PERFCOUNTER1_CFG ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//DAGB0_PERFCOUNTER2_CFG ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//DAGB0_PERFCOUNTER_RSLT_CNTL ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++//DAGB0_RESERVE0 ++#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE1 ++#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE2 ++#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE3 ++#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE4 ++#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE5 ++#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE6 ++#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE7 ++#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE8 ++#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE9 ++#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE10 ++#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE11 ++#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE12 ++#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE13 ++#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE14 ++#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE15 ++#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE16 ++#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE17 ++#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE18 ++#define DAGB0_RESERVE18__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE19 ++#define DAGB0_RESERVE19__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE20 ++#define DAGB0_RESERVE20__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE21 ++#define DAGB0_RESERVE21__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE22 ++#define DAGB0_RESERVE22__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE23 ++#define DAGB0_RESERVE23__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE24 ++#define DAGB0_RESERVE24__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE25 ++#define DAGB0_RESERVE25__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE26 ++#define DAGB0_RESERVE26__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE27 ++#define DAGB0_RESERVE27__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE28 ++#define DAGB0_RESERVE28__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE29 ++#define DAGB0_RESERVE29__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE30 ++#define DAGB0_RESERVE30__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE31 ++#define DAGB0_RESERVE31__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE32 ++#define DAGB0_RESERVE32__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE33 ++#define DAGB0_RESERVE33__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE34 ++#define DAGB0_RESERVE34__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE35 ++#define DAGB0_RESERVE35__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE36 ++#define DAGB0_RESERVE36__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE37 ++#define DAGB0_RESERVE37__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE38 ++#define DAGB0_RESERVE38__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE39 ++#define DAGB0_RESERVE39__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE40 ++#define DAGB0_RESERVE40__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE41 ++#define DAGB0_RESERVE41__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE42 ++#define DAGB0_RESERVE42__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE43 ++#define DAGB0_RESERVE43__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE44 ++#define DAGB0_RESERVE44__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE45 ++#define DAGB0_RESERVE45__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE46 ++#define DAGB0_RESERVE46__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE47 ++#define DAGB0_RESERVE47__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE48 ++#define DAGB0_RESERVE48__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE49 ++#define DAGB0_RESERVE49__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE50 ++#define DAGB0_RESERVE50__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE51 ++#define DAGB0_RESERVE51__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE52 ++#define DAGB0_RESERVE52__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE53 ++#define DAGB0_RESERVE53__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE54 ++#define DAGB0_RESERVE54__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE55 ++#define DAGB0_RESERVE55__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE56 ++#define DAGB0_RESERVE56__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE57 ++#define DAGB0_RESERVE57__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE58 ++#define DAGB0_RESERVE58__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE59 ++#define DAGB0_RESERVE59__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE60 ++#define DAGB0_RESERVE60__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE61 ++#define DAGB0_RESERVE61__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE62 ++#define DAGB0_RESERVE62__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE63 ++#define DAGB0_RESERVE63__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE64 ++#define DAGB0_RESERVE64__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE65 ++#define DAGB0_RESERVE65__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE66 ++#define DAGB0_RESERVE66__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE67 ++#define DAGB0_RESERVE67__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE68 ++#define DAGB0_RESERVE68__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE69 ++#define DAGB0_RESERVE69__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE70 ++#define DAGB0_RESERVE70__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE71 ++#define DAGB0_RESERVE71__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE72 ++#define DAGB0_RESERVE72__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE73 ++#define DAGB0_RESERVE73__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE74 ++#define DAGB0_RESERVE74__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE75 ++#define DAGB0_RESERVE75__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE76 ++#define DAGB0_RESERVE76__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE77 ++#define DAGB0_RESERVE77__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE78 ++#define DAGB0_RESERVE78__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE79 ++#define DAGB0_RESERVE79__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE80 ++#define DAGB0_RESERVE80__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE81 ++#define DAGB0_RESERVE81__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE82 ++#define DAGB0_RESERVE82__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE83 ++#define DAGB0_RESERVE83__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE84 ++#define DAGB0_RESERVE84__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE85 ++#define DAGB0_RESERVE85__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE86 ++#define DAGB0_RESERVE86__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE87 ++#define DAGB0_RESERVE87__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE88 ++#define DAGB0_RESERVE88__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE89 ++#define DAGB0_RESERVE89__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE90 ++#define DAGB0_RESERVE90__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE91 ++#define DAGB0_RESERVE91__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE92 ++#define DAGB0_RESERVE92__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE93 ++#define DAGB0_RESERVE93__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE94 ++#define DAGB0_RESERVE94__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE95 ++#define DAGB0_RESERVE95__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE96 ++#define DAGB0_RESERVE96__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE97 ++#define DAGB0_RESERVE97__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE98 ++#define DAGB0_RESERVE98__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE99 ++#define DAGB0_RESERVE99__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE100 ++#define DAGB0_RESERVE100__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE101 ++#define DAGB0_RESERVE101__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE102 ++#define DAGB0_RESERVE102__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE102__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE103 ++#define DAGB0_RESERVE103__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE103__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE104 ++#define DAGB0_RESERVE104__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE104__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE105 ++#define DAGB0_RESERVE105__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE105__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE106 ++#define DAGB0_RESERVE106__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE106__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE107 ++#define DAGB0_RESERVE107__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE107__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE108 ++#define DAGB0_RESERVE108__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE108__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE109 ++#define DAGB0_RESERVE109__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE109__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE110 ++#define DAGB0_RESERVE110__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE110__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE111 ++#define DAGB0_RESERVE111__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE111__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE112 ++#define DAGB0_RESERVE112__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE112__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE113 ++#define DAGB0_RESERVE113__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE113__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE114 ++#define DAGB0_RESERVE114__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE114__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE115 ++#define DAGB0_RESERVE115__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE115__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE116 ++#define DAGB0_RESERVE116__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE116__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE117 ++#define DAGB0_RESERVE117__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE117__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE118 ++#define DAGB0_RESERVE118__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE118__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE119 ++#define DAGB0_RESERVE119__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE119__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE120 ++#define DAGB0_RESERVE120__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE120__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE121 ++#define DAGB0_RESERVE121__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE121__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE122 ++#define DAGB0_RESERVE122__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE122__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE123 ++#define DAGB0_RESERVE123__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE123__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE124 ++#define DAGB0_RESERVE124__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE124__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE125 ++#define DAGB0_RESERVE125__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE125__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE126 ++#define DAGB0_RESERVE126__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE126__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE127 ++#define DAGB0_RESERVE127__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE127__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE128 ++#define DAGB0_RESERVE128__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE128__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE129 ++#define DAGB0_RESERVE129__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE129__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE130 ++#define DAGB0_RESERVE130__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE130__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE131 ++#define DAGB0_RESERVE131__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE131__RESERVE_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: mmhub_mmea_mmeadec ++//MMEA0_DRAM_RD_CLI2GRP_MAP0 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_RD_CLI2GRP_MAP1 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_WR_CLI2GRP_MAP0 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_WR_CLI2GRP_MAP1 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_RD_GRP2VC_MAP ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//MMEA0_DRAM_WR_GRP2VC_MAP ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//MMEA0_DRAM_RD_LAZY ++#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b ++#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L ++//MMEA0_DRAM_WR_LAZY ++#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b ++#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L ++//MMEA0_DRAM_RD_CAM_CNTL ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L ++//MMEA0_DRAM_WR_CAM_CNTL ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L ++//MMEA0_DRAM_PAGE_BURST ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//MMEA0_DRAM_RD_PRI_AGE ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_DRAM_WR_PRI_AGE ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_DRAM_RD_PRI_QUEUING ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_WR_PRI_QUEUING ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_RD_PRI_FIXED ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_WR_PRI_FIXED ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_RD_PRI_URGENCY ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_DRAM_WR_PRI_URGENCY ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_DRAM_RD_PRI_QUANT_PRI1 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_RD_PRI_QUANT_PRI2 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_RD_PRI_QUANT_PRI3 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_WR_PRI_QUANT_PRI1 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_WR_PRI_QUANT_PRI2 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_WR_PRI_QUANT_PRI3 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_ADDRNORM_BASE_ADDR0 ++#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 ++#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 ++#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L ++#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L ++#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_LIMIT_ADDR0 ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_BASE_ADDR1 ++#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 ++#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 ++#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L ++#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L ++#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_LIMIT_ADDR1 ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_OFFSET_ADDR1 ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L ++//MMEA0_ADDRNORMDRAM_HOLE_CNTL ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L ++//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG ++#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 ++#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 ++#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL ++#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L ++//MMEA0_ADDRDEC_BANK_CFG ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L ++//MMEA0_ADDRDEC_MISC_CFG ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_PC ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL ++//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDECDRAM_HARVEST_ENABLE ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L ++//MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT 0x1c ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK 0x000FFFFFL ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK 0xF0000000L ++//MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK 0x000FFFFFL ++//MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT 0x1c ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK 0x000FFFFFL ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK 0xF0000000L ++//MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK 0x000FFFFFL ++//MMEA0_ADDRDEC0_BASE_ADDR_CS0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_CS1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_CS2 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_CS3 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_CS01 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_CS23 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_CFG_CS01 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC0_ADDR_CFG_CS23 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC0_ADDR_SEL_CS01 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_ADDR_SEL_CS23 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_RM_SEL_CS01 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC0_RM_SEL_CS23 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC0_RM_SEL_SECCS01 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC0_RM_SEL_SECCS23 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_BASE_ADDR_CS0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_CS1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_CS2 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_CS3 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_CS01 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_CS23 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_CFG_CS01 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC1_ADDR_CFG_CS23 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC1_ADDR_SEL_CS01 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_ADDR_SEL_CS23 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_RM_SEL_CS01 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_RM_SEL_CS23 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_RM_SEL_SECCS01 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_RM_SEL_SECCS23 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_IO_RD_CLI2GRP_MAP0 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_IO_RD_CLI2GRP_MAP1 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_IO_WR_CLI2GRP_MAP0 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_IO_WR_CLI2GRP_MAP1 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_IO_RD_COMBINE_FLUSH ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//MMEA0_IO_WR_COMBINE_FLUSH ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//MMEA0_IO_GROUP_BURST ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//MMEA0_IO_RD_PRI_AGE ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_IO_WR_PRI_AGE ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_IO_RD_PRI_QUEUING ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_WR_PRI_QUEUING ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_RD_PRI_FIXED ++#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_WR_PRI_FIXED ++#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_RD_PRI_URGENCY ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_IO_WR_PRI_URGENCY ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_IO_RD_PRI_URGENCY_MASKING ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L ++//MMEA0_IO_WR_PRI_URGENCY_MASKING ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L ++//MMEA0_IO_RD_PRI_QUANT_PRI1 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_RD_PRI_QUANT_PRI2 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_RD_PRI_QUANT_PRI3 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_WR_PRI_QUANT_PRI1 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_WR_PRI_QUANT_PRI2 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_WR_PRI_QUANT_PRI3 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_SDP_ARB_DRAM ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 ++#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 ++#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L ++#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L ++#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L ++//MMEA0_SDP_ARB_FINAL ++#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 ++#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 ++#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa ++#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 ++#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 ++#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a ++#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL ++#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L ++#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L ++#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L ++#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L ++#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L ++//MMEA0_SDP_DRAM_PRIORITY ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//MMEA0_SDP_IO_PRIORITY ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//MMEA0_SDP_CREDITS ++#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 ++#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 ++#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 ++#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL ++#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L ++#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L ++//MMEA0_SDP_TAG_RESERVE0 ++#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 ++#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 ++#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 ++#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 ++#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL ++#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L ++#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L ++#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L ++//MMEA0_SDP_TAG_RESERVE1 ++#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 ++#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 ++#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 ++#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 ++#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL ++#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L ++#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L ++#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L ++//MMEA0_SDP_VCC_RESERVE0 ++#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//MMEA0_SDP_VCC_RESERVE1 ++#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//MMEA0_SDP_VCD_RESERVE0 ++#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//MMEA0_SDP_VCD_RESERVE1 ++#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//MMEA0_SDP_REQ_CNTL ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 ++#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 ++#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L ++#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L ++#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L ++//MMEA0_MISC ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd ++#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe ++#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf ++#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 ++#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 ++#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L ++#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L ++#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L ++#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L ++#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L ++#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L ++#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L ++//MMEA0_LATENCY_SAMPLING ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L ++//MMEA0_PERFCOUNTER_LO ++#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MMEA0_PERFCOUNTER_HI ++#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//MMEA0_PERFCOUNTER0_CFG ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MMEA0_PERFCOUNTER1_CFG ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MMEA0_PERFCOUNTER_RSLT_CNTL ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++//MMEA0_EDC_CNT ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc ++#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe ++#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 ++#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 ++#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 ++#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 ++#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 ++#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a ++#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L ++#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L ++#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L ++#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L ++#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L ++#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L ++#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L ++#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L ++#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L ++//MMEA0_EDC_CNT2 ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc ++#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L ++#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L ++//MMEA0_DSM_CNTL ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L ++//MMEA0_DSM_CNTLA ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++//MMEA0_DSM_CNTL2 ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L ++//MMEA0_DSM_CNTL2A ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++//MMEA0_CGTT_CLK_CTRL ++#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 ++#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 ++#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f ++#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L ++#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L ++#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L ++//MMEA0_EDC_MODE ++#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 ++#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 ++#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 ++#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d ++#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f ++#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L ++#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L ++#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L ++#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L ++#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L ++//MMEA0_ERR_STATUS ++#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 ++#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa ++#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb ++#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc ++#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd ++#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL ++#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L ++#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L ++#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L ++#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L ++//MMEA0_MISC2 ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 ++#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc ++#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L ++#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L ++#define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L ++//MMEA0_ADDRDEC_SELECT ++#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 ++#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 ++#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa ++#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf ++#define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14 ++#define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15 ++#define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16 ++#define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17 ++#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL ++#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L ++#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L ++#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L ++#define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L ++#define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L ++#define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L ++#define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L ++ ++ ++// addressBlock: mmhub_pctldec ++//PCTL_MISC ++#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 ++#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 ++#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 ++#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb ++#define PCTL_MISC__OVR_EA0_SDP_PARTACK__SHIFT 0xc ++#define PCTL_MISC__OVR_EA1_SDP_PARTACK__SHIFT 0xd ++#define PCTL_MISC__OVR_EA0_SDP_FULLACK__SHIFT 0xe ++#define PCTL_MISC__OVR_EA1_SDP_FULLACK__SHIFT 0xf ++#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0x10 ++#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L ++#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L ++#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L ++#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L ++#define PCTL_MISC__OVR_EA0_SDP_PARTACK_MASK 0x00001000L ++#define PCTL_MISC__OVR_EA1_SDP_PARTACK_MASK 0x00002000L ++#define PCTL_MISC__OVR_EA0_SDP_FULLACK_MASK 0x00004000L ++#define PCTL_MISC__OVR_EA1_SDP_FULLACK_MASK 0x00008000L ++#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x00030000L ++//PCTL_MMHUB_DEEPSLEEP ++#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 ++#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 ++#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 ++#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 ++#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 ++#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 ++#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 ++#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 ++#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 ++#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 ++#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa ++#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb ++#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc ++#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd ++#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe ++#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf ++#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 ++#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f ++#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L ++#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L ++#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L ++#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L ++#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L ++#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L ++#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L ++#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L ++#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L ++#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L ++#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L ++#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L ++#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L ++#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L ++#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L ++#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L ++#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L ++#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L ++//PCTL_MMHUB_DEEPSLEEP_OVERRIDE ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L ++//PCTL_PG_IGNORE_DEEPSLEEP ++#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 ++#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L ++//PCTL_PG_DAGB ++#define PCTL_PG_DAGB__DS0__SHIFT 0x0 ++#define PCTL_PG_DAGB__DS1__SHIFT 0x1 ++#define PCTL_PG_DAGB__DS2__SHIFT 0x2 ++#define PCTL_PG_DAGB__DS3__SHIFT 0x3 ++#define PCTL_PG_DAGB__DS4__SHIFT 0x4 ++#define PCTL_PG_DAGB__DS5__SHIFT 0x5 ++#define PCTL_PG_DAGB__DS6__SHIFT 0x6 ++#define PCTL_PG_DAGB__DS7__SHIFT 0x7 ++#define PCTL_PG_DAGB__DS8__SHIFT 0x8 ++#define PCTL_PG_DAGB__DS9__SHIFT 0x9 ++#define PCTL_PG_DAGB__DS10__SHIFT 0xa ++#define PCTL_PG_DAGB__DS11__SHIFT 0xb ++#define PCTL_PG_DAGB__DS12__SHIFT 0xc ++#define PCTL_PG_DAGB__DS13__SHIFT 0xd ++#define PCTL_PG_DAGB__DS14__SHIFT 0xe ++#define PCTL_PG_DAGB__DS15__SHIFT 0xf ++#define PCTL_PG_DAGB__DS16__SHIFT 0x10 ++#define PCTL_PG_DAGB__DS0_MASK 0x00000001L ++#define PCTL_PG_DAGB__DS1_MASK 0x00000002L ++#define PCTL_PG_DAGB__DS2_MASK 0x00000004L ++#define PCTL_PG_DAGB__DS3_MASK 0x00000008L ++#define PCTL_PG_DAGB__DS4_MASK 0x00000010L ++#define PCTL_PG_DAGB__DS5_MASK 0x00000020L ++#define PCTL_PG_DAGB__DS6_MASK 0x00000040L ++#define PCTL_PG_DAGB__DS7_MASK 0x00000080L ++#define PCTL_PG_DAGB__DS8_MASK 0x00000100L ++#define PCTL_PG_DAGB__DS9_MASK 0x00000200L ++#define PCTL_PG_DAGB__DS10_MASK 0x00000400L ++#define PCTL_PG_DAGB__DS11_MASK 0x00000800L ++#define PCTL_PG_DAGB__DS12_MASK 0x00001000L ++#define PCTL_PG_DAGB__DS13_MASK 0x00002000L ++#define PCTL_PG_DAGB__DS14_MASK 0x00004000L ++#define PCTL_PG_DAGB__DS15_MASK 0x00008000L ++#define PCTL_PG_DAGB__DS16_MASK 0x00010000L ++//PCTL0_RENG_RAM_INDEX ++#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 ++#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL ++//PCTL0_RENG_RAM_DATA ++#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 ++#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL ++//PCTL0_RENG_EXECUTE ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L ++//PCTL1_RENG_RAM_INDEX ++#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 ++#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL ++//PCTL1_RENG_RAM_DATA ++#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 ++#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL ++//PCTL1_RENG_EXECUTE ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L ++//PCTL2_RENG_RAM_INDEX ++#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 ++#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL ++//PCTL2_RENG_RAM_DATA ++#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 ++#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL ++//PCTL2_RENG_EXECUTE ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE1 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE2 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE3 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE4 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE1 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE2 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE3 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE4 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE1 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE2 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE3 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE4 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L ++//PCTL0_MISC ++#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb ++#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc ++#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf ++#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 ++#define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 ++#define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 ++#define PCTL0_MISC__RD_TIMER_ENABLE__SHIFT 0x13 ++#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L ++#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L ++#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L ++#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L ++#define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L ++#define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L ++#define PCTL0_MISC__RD_TIMER_ENABLE_MASK 0x00080000L ++//PCTL1_MISC ++#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa ++#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb ++#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe ++#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf ++#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 ++#define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 ++#define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 ++#define PCTL1_MISC__RD_TIMER_ENABLE__SHIFT 0x13 ++#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L ++#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L ++#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L ++#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L ++#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L ++#define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L ++#define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L ++#define PCTL1_MISC__RD_TIMER_ENABLE_MASK 0x00080000L ++//PCTL2_MISC ++#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa ++#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb ++#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe ++#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf ++#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 ++#define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 ++#define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 ++#define PCTL2_MISC__RD_TIMER_ENABLE__SHIFT 0x13 ++#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L ++#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L ++#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L ++#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L ++#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L ++#define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L ++#define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L ++#define PCTL2_MISC__RD_TIMER_ENABLE_MASK 0x00080000L ++//PCTL_PERFCOUNTER_LO ++#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//PCTL_PERFCOUNTER_HI ++#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//PCTL_PERFCOUNTER0_CFG ++#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//PCTL_PERFCOUNTER1_CFG ++#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//PCTL_PERFCOUNTER_RSLT_CNTL ++#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1pfdec ++//MMMC_VM_MX_L1_TLB0_STATUS ++#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MMMC_VM_MX_L1_TLB1_STATUS ++#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MMMC_VM_MX_L1_TLB2_STATUS ++#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MMMC_VM_MX_L1_TLB3_STATUS ++#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MMMC_VM_MX_L1_TLB4_STATUS ++#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MMMC_VM_MX_L1_TLB5_STATUS ++#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MMMC_VM_MX_L1_TLB6_STATUS ++#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MMMC_VM_MX_L1_TLB7_STATUS ++#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1pldec ++//MMMC_VM_MX_L1_PERFCOUNTER0_CFG ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_MX_L1_PERFCOUNTER1_CFG ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_MX_L1_PERFCOUNTER2_CFG ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_MX_L1_PERFCOUNTER3_CFG ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++ ++// addressBlock: mmhub_l1tlb_mmvml1prdec ++//MMMC_VM_MX_L1_PERFCOUNTER_LO ++#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MMMC_VM_MX_L1_PERFCOUNTER_HI ++#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2dec ++//MM_ATC_L2_CNTL ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 ++#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 ++#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L ++#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L ++#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L ++#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L ++//MM_ATC_L2_CNTL2 ++#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 ++#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 ++#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 ++#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc ++#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf ++#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL ++#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L ++#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L ++#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L ++#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L ++#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L ++//MM_ATC_L2_CACHE_DATA0 ++#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 ++#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 ++#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 ++#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 ++#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L ++#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L ++#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL ++#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L ++//MM_ATC_L2_CACHE_DATA1 ++#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 ++#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL ++//MM_ATC_L2_CACHE_DATA2 ++#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 ++#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL ++//MM_ATC_L2_CNTL3 ++#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 ++#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 ++#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 ++#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L ++#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L ++#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L ++//MM_ATC_L2_STATUS ++#define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 ++#define MM_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 ++#define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L ++#define MM_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL ++//MM_ATC_L2_STATUS2 ++#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 ++#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 ++#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL ++#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L ++//MM_ATC_L2_MISC_CG ++#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 ++#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 ++#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L ++#define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L ++#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L ++//MM_ATC_L2_MEM_POWER_LS ++#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 ++#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 ++#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL ++#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L ++//MM_ATC_L2_CGTT_CLK_CTRL ++#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++//MM_ATC_L2_SDPPORT_CTRL ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L ++#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2pfdec ++//MMVM_L2_CNTL ++#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 ++#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 ++#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 ++#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 ++#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 ++#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 ++#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa ++#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb ++#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc ++#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf ++#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 ++#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 ++#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 ++#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a ++#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L ++#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L ++#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL ++#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L ++#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L ++#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L ++#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L ++#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L ++#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L ++#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L ++#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L ++#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L ++#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L ++#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L ++//MMVM_L2_CNTL2 ++#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 ++#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 ++#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 ++#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 ++#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 ++#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a ++#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c ++#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L ++#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L ++#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L ++#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L ++#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L ++#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L ++#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L ++//MMVM_L2_CNTL3 ++#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 ++#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 ++#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 ++#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d ++#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e ++#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f ++#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL ++#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L ++#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L ++#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L ++#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L ++#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L ++#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L ++#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L ++//MMVM_L2_STATUS ++#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 ++#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 ++#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 ++#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 ++#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 ++#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 ++#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 ++#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L ++#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL ++#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L ++#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L ++#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L ++#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L ++#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L ++//MMVM_DUMMY_PAGE_FAULT_CNTL ++#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 ++#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 ++#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 ++#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L ++#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L ++#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL ++//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 ++#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 ++#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 ++#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 ++#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL ++//MMVM_INVALIDATE_CNTL ++#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 ++#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 ++#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL ++#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L ++//MMVM_L2_PROTECTION_FAULT_CNTL ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 ++#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb ++#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd ++#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L ++#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L ++//MMVM_L2_PROTECTION_FAULT_CNTL2 ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L ++#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L ++//MMVM_L2_PROTECTION_FAULT_MM_CNTL3 ++#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL ++//MMVM_L2_PROTECTION_FAULT_MM_CNTL4 ++#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL ++//MMVM_L2_PROTECTION_FAULT_STATUS ++#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 ++#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL ++#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L ++#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L ++//MMVM_L2_PROTECTION_FAULT_ADDR_LO32 ++#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//MMVM_L2_PROTECTION_FAULT_ADDR_HI32 ++#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL ++//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 ++#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 ++#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 ++#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL ++//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 ++#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 ++#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL ++//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 ++#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 ++#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL ++//MMVM_L2_CNTL4 ++#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 ++#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 ++#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 ++#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 ++#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 ++#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c ++#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d ++#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL ++#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L ++#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L ++#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L ++#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L ++#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L ++#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L ++//MMVM_L2_MM_GROUP_RT_CLASSES ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L ++#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L ++//MMVM_L2_BANK_SELECT_RESERVED_CID ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L ++//MMVM_L2_BANK_SELECT_RESERVED_CID2 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L ++#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L ++//MMVM_L2_CACHE_PARITY_CNTL ++#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 ++#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 ++#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc ++#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L ++#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L ++#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L ++#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L ++//MMVM_L2_IH_LOG_CNTL ++#define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING__SHIFT 0x0 ++#define MMVM_L2_IH_LOG_CNTL__USE_L_BIT__SHIFT 0x1 ++#define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS__SHIFT 0x2 ++#define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS__SHIFT 0x14 ++#define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING_MASK 0x00000001L ++#define MMVM_L2_IH_LOG_CNTL__USE_L_BIT_MASK 0x00000002L ++#define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS_MASK 0x000FFFFCL ++#define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS_MASK 0x00100000L ++//MMVM_L2_IH_LOG_BUSY ++#define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY__SHIFT 0x0 ++#define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY__SHIFT 0x10 ++#define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY_MASK 0x0000FFFFL ++#define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY_MASK 0xFFFF0000L ++//MMVM_L2_CGTT_CLK_CTRL ++#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++//MMVM_L2_CNTL5 ++#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 ++#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 ++#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL ++#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L ++//MMVM_L2_GCR_CNTL ++#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 ++#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 ++#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L ++#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL ++//MMVML2_WALKER_MACRO_THROTTLE_TIME ++#define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 ++#define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL ++//MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT ++#define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 ++#define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL ++//MMVML2_WALKER_MICRO_THROTTLE_TIME ++#define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 ++#define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL ++//MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT ++#define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 ++#define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2vcdec ++//MMVM_CONTEXT0_CNTL ++#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT1_CNTL ++#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT2_CNTL ++#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT3_CNTL ++#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT4_CNTL ++#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT5_CNTL ++#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT6_CNTL ++#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT7_CNTL ++#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT8_CNTL ++#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT9_CNTL ++#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT10_CNTL ++#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT11_CNTL ++#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT12_CNTL ++#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT13_CNTL ++#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT14_CNTL ++#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXT15_CNTL ++#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//MMVM_CONTEXTS_DISABLE ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L ++#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L ++//MMVM_INVALIDATE_ENG0_SEM ++#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG1_SEM ++#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG2_SEM ++#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG3_SEM ++#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG4_SEM ++#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG5_SEM ++#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG6_SEM ++#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG7_SEM ++#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG8_SEM ++#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG9_SEM ++#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG10_SEM ++#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG11_SEM ++#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG12_SEM ++#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG13_SEM ++#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG14_SEM ++#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG15_SEM ++#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG16_SEM ++#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG17_SEM ++#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L ++//MMVM_INVALIDATE_ENG0_REQ ++#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG1_REQ ++#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG2_REQ ++#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG3_REQ ++#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG4_REQ ++#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG5_REQ ++#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG6_REQ ++#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG7_REQ ++#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG8_REQ ++#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG9_REQ ++#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG10_REQ ++#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG11_REQ ++#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG12_REQ ++#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG13_REQ ++#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG14_REQ ++#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG15_REQ ++#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG16_REQ ++#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG17_REQ ++#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 ++#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 ++#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a ++#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L ++#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L ++#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L ++#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L ++//MMVM_INVALIDATE_ENG0_ACK ++#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG1_ACK ++#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG2_ACK ++#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG3_ACK ++#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG4_ACK ++#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG5_ACK ++#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG6_ACK ++#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG7_ACK ++#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG8_ACK ++#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG9_ACK ++#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG10_ACK ++#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG11_ACK ++#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG12_ACK ++#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG13_ACK ++#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG14_ACK ++#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG15_ACK ++#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG16_ACK ++#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG17_ACK ++#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 ++#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L ++//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 ++#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 ++#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 ++#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 ++#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 ++#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 ++#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 ++#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 ++#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2pldec ++//MMMC_VM_L2_PERFCOUNTER0_CFG ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER1_CFG ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER2_CFG ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER3_CFG ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER4_CFG ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER5_CFG ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER6_CFG ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER7_CFG ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L ++#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L ++//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvml2prdec ++//MMMC_VM_L2_PERFCOUNTER_LO ++#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MMMC_VM_L2_PERFCOUNTER_HI ++#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec ++//MMMC_VM_FB_SIZE_OFFSET_VF0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF1 ++#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF2 ++#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF3 ++#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF4 ++#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF5 ++#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF6 ++#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF7 ++#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF8 ++#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF9 ++#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF11 ++#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF12 ++#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF13 ++#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF14 ++#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF15 ++#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF16 ++#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF17 ++#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF18 ++#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF19 ++#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF20 ++#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF21 ++#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF22 ++#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF23 ++#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF24 ++#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF25 ++#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF26 ++#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF27 ++#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF28 ++#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF29 ++#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF30 ++#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMMC_VM_FB_SIZE_OFFSET_VF31 ++#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0 ++#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10 ++#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MMVM_IOMMU_MMIO_CNTRL_1 ++#define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 ++#define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L ++//MMMC_VM_MARC_BASE_LO_0 ++#define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc ++#define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L ++//MMMC_VM_MARC_BASE_LO_1 ++#define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc ++#define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L ++//MMMC_VM_MARC_BASE_LO_2 ++#define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc ++#define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L ++//MMMC_VM_MARC_BASE_LO_3 ++#define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc ++#define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L ++//MMMC_VM_MARC_BASE_HI_0 ++#define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 ++#define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL ++//MMMC_VM_MARC_BASE_HI_1 ++#define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 ++#define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL ++//MMMC_VM_MARC_BASE_HI_2 ++#define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 ++#define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL ++//MMMC_VM_MARC_BASE_HI_3 ++#define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 ++#define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL ++//MMMC_VM_MARC_RELOC_LO_0 ++#define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 ++#define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc ++#define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L ++#define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L ++#define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L ++//MMMC_VM_MARC_RELOC_LO_1 ++#define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 ++#define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc ++#define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L ++#define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L ++#define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L ++//MMMC_VM_MARC_RELOC_LO_2 ++#define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 ++#define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc ++#define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L ++#define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L ++#define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L ++//MMMC_VM_MARC_RELOC_LO_3 ++#define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 ++#define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc ++#define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L ++#define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L ++#define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L ++//MMMC_VM_MARC_RELOC_HI_0 ++#define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL ++//MMMC_VM_MARC_RELOC_HI_1 ++#define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL ++//MMMC_VM_MARC_RELOC_HI_2 ++#define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL ++//MMMC_VM_MARC_RELOC_HI_3 ++#define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 ++#define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL ++//MMMC_VM_MARC_LEN_LO_0 ++#define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc ++#define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L ++//MMMC_VM_MARC_LEN_LO_1 ++#define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc ++#define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L ++//MMMC_VM_MARC_LEN_LO_2 ++#define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc ++#define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L ++//MMMC_VM_MARC_LEN_LO_3 ++#define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc ++#define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L ++//MMMC_VM_MARC_LEN_HI_0 ++#define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 ++#define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL ++//MMMC_VM_MARC_LEN_HI_1 ++#define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 ++#define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL ++//MMMC_VM_MARC_LEN_HI_2 ++#define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 ++#define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL ++//MMMC_VM_MARC_LEN_HI_3 ++#define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 ++#define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL ++//MMVM_IOMMU_CONTROL_REGISTER ++#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 ++#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L ++//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER ++#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd ++#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L ++//MMVM_PCIE_ATS_CNTL ++#define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 ++#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L ++#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_0 ++#define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_1 ++#define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_2 ++#define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_3 ++#define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_4 ++#define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_5 ++#define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_6 ++#define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_7 ++#define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_8 ++#define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_9 ++#define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_10 ++#define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_11 ++#define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_12 ++#define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_13 ++#define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_14 ++#define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_15 ++#define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_16 ++#define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_17 ++#define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_18 ++#define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_19 ++#define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_20 ++#define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_21 ++#define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_22 ++#define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_23 ++#define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_24 ++#define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_25 ++#define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_26 ++#define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_27 ++#define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_28 ++#define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_29 ++#define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_30 ++#define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L ++//MMVM_PCIE_ATS_CNTL_VF_31 ++#define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT 0x1f ++#define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK 0x80000000L ++//MMUTCL2_CGTT_CLK_CTRL ++#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc ++#define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L ++#define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++//MMMC_SHARED_ACTIVE_FCN_ID ++#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL ++#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec ++//MMMC_VM_NB_MMIOBASE ++#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 ++#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL ++//MMMC_VM_NB_MMIOLIMIT ++#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 ++#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL ++//MMMC_VM_NB_PCI_CTRL ++#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 ++#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L ++//MMMC_VM_NB_PCI_ARB ++#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 ++#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L ++//MMMC_VM_NB_TOP_OF_DRAM_SLOT1 ++#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 ++#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L ++//MMMC_VM_NB_LOWER_TOP_OF_DRAM2 ++#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 ++#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 ++#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L ++#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L ++//MMMC_VM_NB_UPPER_TOP_OF_DRAM2 ++#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 ++#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL ++//MMMC_VM_FB_OFFSET ++#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 ++#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL ++//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB ++#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 ++#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL ++//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB ++#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 ++#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL ++//MMMC_VM_STEERING ++#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 ++#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L ++//MMMC_SHARED_VIRT_RESET_REQ ++#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL ++#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//MMMC_MEM_POWER_LS ++#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 ++#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 ++#define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL ++#define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L ++//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START ++#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 ++#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL ++//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END ++#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 ++#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL ++//MMMC_VM_APT_CNTL ++#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 ++#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 ++#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L ++#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L ++//MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL ++#define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 ++#define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L ++//MMMC_VM_LOCAL_HBM_ADDRESS_START ++#define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 ++#define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL ++//MMMC_VM_LOCAL_HBM_ADDRESS_END ++#define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 ++#define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL ++//MMMC_SHARED_VIRT_RESET_REQ2 ++#define MMMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0 ++#define MMMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec ++//MMMC_VM_FB_LOCATION_BASE ++#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 ++#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL ++//MMMC_VM_FB_LOCATION_TOP ++#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 ++#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL ++//MMMC_VM_AGP_TOP ++#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 ++#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL ++//MMMC_VM_AGP_BOT ++#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 ++#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL ++//MMMC_VM_AGP_BASE ++#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 ++#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL ++//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR ++#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 ++#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL ++//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR ++#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 ++#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL ++//MMMC_VM_MX_L1_TLB_CNTL ++#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 ++#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 ++#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 ++#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 ++#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 ++#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb ++#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L ++#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L ++#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L ++#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L ++#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L ++#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec ++//MM_ATC_L2_PERFCOUNTER_LO ++#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MM_ATC_L2_PERFCOUNTER_HI ++#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec ++//MM_ATC_L2_PERFCOUNTER0_CFG ++#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MM_ATC_L2_PERFCOUNTER1_CFG ++#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++#endif +-- +2.17.1 + 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