diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2132-drm-amdgpu-add-MP-11.0-register-headers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2132-drm-amdgpu-add-MP-11.0-register-headers.patch | 454 |
1 files changed, 454 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2132-drm-amdgpu-add-MP-11.0-register-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2132-drm-amdgpu-add-MP-11.0-register-headers.patch new file mode 100644 index 00000000..60aa397c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2132-drm-amdgpu-add-MP-11.0-register-headers.patch @@ -0,0 +1,454 @@ +From 98748f949ca6f1c0cb90100a18ebf4131626741c Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Sun, 3 Mar 2019 11:15:26 +0800 +Subject: [PATCH 2132/2940] drm/amdgpu: add MP 11.0 register headers + +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../amd/include/asic_reg/mp/mp_11_0_sh_mask.h | 429 ++++++++++++++++++ + 1 file changed, 429 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h +index 1ac8895c29a9..136fb5de6a4c 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h +@@ -262,6 +262,435 @@ + #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + ++//MP1_FIRMWARE_FLAGS ++#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 ++#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 ++#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L ++#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL ++//MP1_PUB_SCRATCH0 ++#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL ++//MP1_PUB_SCRATCH1 ++#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL ++//MP1_PUB_SCRATCH2 ++#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL ++//MP1_PUB_SCRATCH3 ++#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_0 ++#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_1 ++#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_2 ++#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_3 ++#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_4 ++#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_5 ++#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_6 ++#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_7 ++#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_8 ++#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_9 ++#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_10 ++#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_11 ++#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_12 ++#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_13 ++#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_14 ++#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_15 ++#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_16 ++#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_17 ++#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_18 ++#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_19 ++#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_20 ++#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_21 ++#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_22 ++#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_23 ++#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_24 ++#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_25 ++#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_26 ++#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_27 ++#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_28 ++#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_29 ++#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_30 ++#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_31 ++#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_0 ++#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_1 ++#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_2 ++#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_3 ++#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_INTEN ++#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 ++#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL ++//MP1_P2CMSG_INTSTS ++#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 ++#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 ++#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 ++#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 ++#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L ++#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L ++#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L ++#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L ++//MP1_P2SMSG_0 ++#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_1 ++#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_2 ++#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_3 ++#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_INTSTS ++#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 ++#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 ++#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 ++#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 ++#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L ++#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L ++#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L ++#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L ++//MP1_S2PMSG_0 ++#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_32 ++#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_33 ++#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_34 ++#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_35 ++#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_36 ++#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_37 ++#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_38 ++#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_39 ++#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_40 ++#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_41 ++#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_42 ++#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_43 ++#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_44 ++#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_45 ++#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_46 ++#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_47 ++#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_48 ++#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_49 ++#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_50 ++#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_51 ++#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_52 ++#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_53 ++#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_54 ++#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_55 ++#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_56 ++#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_57 ++#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_58 ++#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_59 ++#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_60 ++#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_61 ++#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_62 ++#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_63 ++#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_64 ++#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_65 ++#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_66 ++#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_67 ++#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_68 ++#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_69 ++#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_70 ++#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_71 ++#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_72 ++#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_73 ++#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_74 ++#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_75 ++#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_76 ++#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_77 ++#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_78 ++#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_79 ++#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_80 ++#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_81 ++#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_82 ++#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_83 ++#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_84 ++#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_85 ++#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_86 ++#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_87 ++#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_88 ++#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_89 ++#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_90 ++#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_91 ++#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_92 ++#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_93 ++#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_94 ++#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_95 ++#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_96 ++#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_97 ++#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_98 ++#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_99 ++#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_100 ++#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_101 ++#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_102 ++#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_103 ++#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL ++//MP1_ACTIVE_FCN_ID ++#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL ++#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//MP1_IH_CREDIT ++#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 ++#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 ++#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L ++#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L ++//MP1_IH_SW_INT ++#define MP1_IH_SW_INT__ID__SHIFT 0x0 ++#define MP1_IH_SW_INT__VALID__SHIFT 0x8 ++#define MP1_IH_SW_INT__ID_MASK 0x000000FFL ++#define MP1_IH_SW_INT__VALID_MASK 0x00000100L ++//MP1_IH_SW_INT_CTRL ++#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 ++#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 ++#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L ++#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L ++//MP1_FPS_CNT ++#define MP1_FPS_CNT__COUNT__SHIFT 0x0 ++#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL ++//MP1_PUB_CTRL ++#define MP1_PUB_CTRL__RESET__SHIFT 0x0 ++#define MP1_PUB_CTRL__RESET_MASK 0x00000001L ++//MP1_EXT_SCRATCH0 ++#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH1 ++#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH2 ++#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH3 ++#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH4 ++#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH5 ++#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH6 ++#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH7 ++#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL ++ ++ + // addressBlock: mp_SmuMp1_SmnDec + //MP1_SMN_C2PMSG_32 + #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +-- +2.17.1 + |