diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2014-drm-amd-display-Add-GSL-source-select-registers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2014-drm-amd-display-Add-GSL-source-select-registers.patch | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2014-drm-amd-display-Add-GSL-source-select-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2014-drm-amd-display-Add-GSL-source-select-registers.patch new file mode 100644 index 00000000..b1f922ca --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2014-drm-amd-display-Add-GSL-source-select-registers.patch @@ -0,0 +1,66 @@ +From 5674fdc851ee92d6cb701e3b171e4b67d8f806cd Mon Sep 17 00:00:00 2001 +From: Krunoslav Kovac <Krunoslav.Kovac@amd.com> +Date: Fri, 15 Mar 2019 16:25:41 -0400 +Subject: [PATCH 2014/2940] drm/amd/display: Add GSL source select registers + +GSL is a form of locking that can be used to synchronize pipes in a +pipe-split configurations when async flip is used. Add the registers +here. + +Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +index 651b8caa4b9f..70fd56fa56c5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +@@ -84,7 +84,8 @@ + SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ + SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ +- SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst) ++ SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ ++ SR(GSL_SOURCE_SELECT) + + #define TG_COMMON_REG_LIST_DCN1_0(inst) \ + TG_COMMON_REG_LIST_DCN(inst),\ +@@ -156,6 +157,7 @@ struct dcn_optc_registers { + uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; + uint32_t OTG_CRC0_WINDOWB_X_CONTROL; + uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; ++ uint32_t GSL_SOURCE_SELECT; + }; + + #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ +@@ -266,7 +268,10 @@ struct dcn_optc_registers { + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ +- SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh) ++ SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ ++ SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ ++ SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ ++ SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh) + + + #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ +@@ -413,7 +418,10 @@ struct dcn_optc_registers { + type OTG_CRC0_WINDOWB_X_START;\ + type OTG_CRC0_WINDOWB_X_END;\ + type OTG_CRC0_WINDOWB_Y_START;\ +- type OTG_CRC0_WINDOWB_Y_END; ++ type OTG_CRC0_WINDOWB_Y_END;\ ++ type GSL0_READY_SOURCE_SEL;\ ++ type GSL1_READY_SOURCE_SEL;\ ++ type GSL2_READY_SOURCE_SEL; + + + #define TG_REG_FIELD_LIST(type) \ +-- +2.17.1 + |