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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1983-drm-amd-powerplay-Enable-disable-dpm-feature-to-supp.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1983-drm-amd-powerplay-Enable-disable-dpm-feature-to-supp.patch252
1 files changed, 252 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1983-drm-amd-powerplay-Enable-disable-dpm-feature-to-supp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1983-drm-amd-powerplay-Enable-disable-dpm-feature-to-supp.patch
new file mode 100644
index 00000000..f95921d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1983-drm-amd-powerplay-Enable-disable-dpm-feature-to-supp.patch
@@ -0,0 +1,252 @@
+From 15e34fcd06daf28860a90198bd0b13585516a6b3 Mon Sep 17 00:00:00 2001
+From: Chengming Gui <Jack.Gui@amd.com>
+Date: Wed, 8 May 2019 14:38:55 +0800
+Subject: [PATCH 1983/2940] drm/amd/powerplay: Enable "disable dpm" feature to
+ support swSMU debug (v2)
+
+add pm_enabled to control the dpm off/on.
+v2: Directly return 0 to replace return ret and merge some check code.
+
+Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 24 +++++++++++--
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 34 ++++++++++++++++---
+ 3 files changed, 51 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index b119a276a977..3a47130f8150 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -198,6 +198,8 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
+ ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
+ int ret = 0;
+
++ if (!smu->pm_enabled)
++ return -EINVAL;
+ if (header->usStructureSize != size) {
+ pr_err("pp table size not matched !\n");
+ return -EIO;
+@@ -233,6 +235,8 @@ int smu_feature_init_dpm(struct smu_context *smu)
+ int ret = 0;
+ uint32_t unallowed_feature_mask[SMU_FEATURE_MAX/32];
+
++ if (!smu->pm_enabled)
++ return ret;
+ mutex_lock(&feature->mutex);
+ bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
+ mutex_unlock(&feature->mutex);
+@@ -344,6 +348,7 @@ static int smu_early_init(void *handle)
+ struct smu_context *smu = &adev->smu;
+
+ smu->adev = adev;
++ smu->pm_enabled = amdgpu_dpm;
+ mutex_init(&smu->mutex);
+
+ return smu_set_funcs(adev);
+@@ -353,6 +358,9 @@ static int smu_late_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = &adev->smu;
++
++ if (!smu->pm_enabled)
++ return 0;
+ mutex_lock(&smu->mutex);
+ smu_handle_task(&adev->smu,
+ smu->smu_dpm.dpm_level,
+@@ -736,6 +744,9 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ */
+ ret = smu_set_tool_table_location(smu);
+
++ if (!smu_is_dpm_running(smu))
++ pr_info("dpm has been disabled\n");
++
+ return ret;
+ }
+
+@@ -848,7 +859,10 @@ static int smu_hw_init(void *handle)
+
+ mutex_unlock(&smu->mutex);
+
+- adev->pm.dpm_enabled = true;
++ if (!smu->pm_enabled)
++ adev->pm.dpm_enabled = false;
++ else
++ adev->pm.dpm_enabled = true;
+
+ pr_info("SMU is initialized successfully!\n");
+
+@@ -963,7 +977,7 @@ int smu_display_configuration_change(struct smu_context *smu,
+ int index = 0;
+ int num_of_active_display = 0;
+
+- if (!is_support_sw_smu(smu->adev))
++ if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
+ return -EINVAL;
+
+ if (!display_config)
+@@ -1091,7 +1105,7 @@ static int smu_enable_umd_pstate(void *handle,
+
+ struct smu_context *smu = (struct smu_context*)(handle);
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+- if (!smu_dpm_ctx->dpm_context)
++ if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
+ return -EINVAL;
+
+ if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
+@@ -1134,6 +1148,8 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ long workload;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+
++ if (!smu->pm_enabled)
++ return -EINVAL;
+ if (!skip_display_settings) {
+ ret = smu_display_config_changed(smu);
+ if (ret) {
+@@ -1142,6 +1158,8 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ }
+ }
+
++ if (!smu->pm_enabled)
++ return -EINVAL;
+ ret = smu_apply_clocks_adjust_rules(smu);
+ if (ret) {
+ pr_err("Failed to apply clocks adjust rules!");
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 2cb4cc2a8208..3eb1de9ecf73 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -401,6 +401,7 @@ struct smu_context
+ uint32_t workload_setting[WORKLOAD_POLICY_MAX];
+ uint32_t power_profile_mode;
+ uint32_t default_power_profile_mode;
++ bool pm_enabled;
+
+ uint32_t smc_if_version;
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index da59a0972b8e..940b519686d5 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -360,6 +360,8 @@ static int smu_v11_0_init_power(struct smu_context *smu)
+ {
+ struct smu_power_context *smu_power = &smu->smu_power;
+
++ if (!smu->pm_enabled)
++ return 0;
+ if (smu_power->power_context || smu_power->power_context_size != 0)
+ return -EINVAL;
+
+@@ -383,6 +385,8 @@ static int smu_v11_0_fini_power(struct smu_context *smu)
+ {
+ struct smu_power_context *smu_power = &smu->smu_power;
+
++ if (!smu->pm_enabled)
++ return 0;
+ if (!smu_power->power_context || smu_power->power_context_size == 0)
+ return -EINVAL;
+
+@@ -650,6 +654,8 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+ {
+ struct smu_table_context *table_context = &smu->smu_table;
+
++ if (!smu->pm_enabled)
++ return 0;
+ if (!table_context)
+ return -EINVAL;
+
+@@ -678,6 +684,9 @@ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+ static int smu_v11_0_init_display(struct smu_context *smu)
+ {
+ int ret = 0;
++
++ if (!smu->pm_enabled)
++ return ret;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
+ return ret;
+ }
+@@ -687,6 +696,8 @@ static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32
+ uint32_t feature_low = 0, feature_high = 0;
+ int ret = 0;
+
++ if (!smu->pm_enabled)
++ return ret;
+ if (feature_id >= 0 && feature_id < 31)
+ feature_low = (1 << feature_id);
+ else if (feature_id > 31 && feature_id < 63)
+@@ -793,10 +804,13 @@ static int smu_v11_0_system_features_control(struct smu_context *smu,
+ uint32_t feature_mask[2];
+ int ret = 0;
+
+- ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
+- SMU_MSG_DisableAllSmuFeatures));
+- if (ret)
+- return ret;
++ if (smu->pm_enabled) {
++ ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
++ SMU_MSG_DisableAllSmuFeatures));
++ if (ret)
++ return ret;
++ }
++
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ if (ret)
+ return ret;
+@@ -813,6 +827,8 @@ static int smu_v11_0_notify_display_change(struct smu_context *smu)
+ {
+ int ret = 0;
+
++ if (!smu->pm_enabled)
++ return ret;
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT))
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
+
+@@ -825,6 +841,8 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
+ {
+ int ret = 0;
+
++ if (!smu->pm_enabled)
++ return ret;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
+ clock_select << 16);
+ if (ret) {
+@@ -1101,6 +1119,8 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ TEMP_RANGE_MAX};
+ struct amdgpu_device *adev = smu->adev;
+
++ if (!smu->pm_enabled)
++ return ret;
+ smu_v11_0_get_thermal_range(smu, &range);
+
+ if (smu->smu_table.thermal_controller_type) {
+@@ -1336,6 +1356,8 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ PPCLK_e clk_select = 0;
+ uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
+
++ if (!smu->pm_enabled)
++ return -EINVAL;
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ switch (clk_type) {
+ case amd_pp_dcef_clock:
+@@ -1619,7 +1641,7 @@ static int smu_v11_0_get_power_profile_mode(struct smu_context *smu, char *buf)
+ "PD_Data_error_rate_coeff"};
+ int result = 0;
+
+- if (!buf)
++ if (!smu->pm_enabled || !buf)
+ return -EINVAL;
+
+ size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
+@@ -1706,6 +1728,8 @@ static int smu_v11_0_set_power_profile_mode(struct smu_context *smu, long *input
+
+ smu->power_profile_mode = input[size];
+
++ if (!smu->pm_enabled)
++ return ret;
+ if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+ pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
+ return -EINVAL;
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-30 21:56:01 +0000