diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1967-drm-amd-display-add-null-checks-and-set-update-flags.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1967-drm-amd-display-add-null-checks-and-set-update-flags.patch | 189 |
1 files changed, 189 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1967-drm-amd-display-add-null-checks-and-set-update-flags.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1967-drm-amd-display-add-null-checks-and-set-update-flags.patch new file mode 100644 index 00000000..75d20804 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1967-drm-amd-display-add-null-checks-and-set-update-flags.patch @@ -0,0 +1,189 @@ +From 843381a18f3004706ab25183e5155fa2ae491bf4 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Mon, 8 Apr 2019 14:56:29 -0400 +Subject: [PATCH 1967/2940] drm/amd/display: add null checks and set update + flags + +* add plane state null checks +* add and set update surface flags + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++++++ + .../gpu/drm/amd/display/dc/core/dc_resource.c | 1 - + drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 +++++------- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 ++ + .../gpu/drm/amd/display/dc/inc/core_types.h | 20 +++++++++++++++++++ + 6 files changed, 35 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index fd57fd1faccb..6d65526bce64 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1370,6 +1370,9 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa + if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) + update_flags->bits.global_alpha_change = 1; + ++ if (u->plane_info->sdr_white_level != u->surface->sdr_white_level) ++ update_flags->bits.sdr_white_level = 1; ++ + if (u->plane_info->dcc.enable != u->surface->dcc.enable + || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks + || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch) +@@ -1473,6 +1476,9 @@ static enum surface_update_type det_surface_update(const struct dc *dc, + + update_flags->raw = 0; // Reset all flags + ++ if (u->flip_addr) ++ update_flags->bits.addr_update = 1; ++ + if (!is_surface_in_context(context, u->surface)) { + update_flags->bits.new_plane = 1; + return UPDATE_TYPE_FULL; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 58ce7a6b914c..36346f6ceb9a 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -2501,7 +2501,6 @@ void dc_resource_state_copy_construct( + + if (cur_pipe->bottom_pipe) + cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; +- + } + + for (i = 0; i < dst_ctx->stream_count; i++) { +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 35f50431892f..8795e29ea888 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -555,12 +555,14 @@ struct dc_plane_status { + union surface_update_flags { + + struct { ++ uint32_t addr_update:1; + /* Medium updates */ + uint32_t dcc_change:1; + uint32_t color_space_change:1; + uint32_t horizontal_mirror_change:1; + uint32_t per_pixel_alpha_change:1; + uint32_t global_alpha_change:1; ++ uint32_t sdr_white_level:1; + uint32_t rotation_change:1; + uint32_t swizzle_change:1; + uint32_t scaling_change:1; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 2aa6da562d37..58d3fd742eab 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1754,7 +1754,7 @@ static void dcn10_program_output_csc(struct dc *dc, + + bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) + { +- if (pipe_ctx->plane_state->visible) ++ if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) + return true; + if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) + return true; +@@ -1763,7 +1763,7 @@ bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) + + bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) + { +- if (pipe_ctx->plane_state->visible) ++ if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) + return true; + if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) + return true; +@@ -1772,7 +1772,7 @@ bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) + + bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) + { +- if (pipe_ctx->plane_state->visible) ++ if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible) + return true; + if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) + return true; +@@ -1918,7 +1918,7 @@ static uint16_t fixed_point_to_int_frac( + return result; + } + +-void build_prescale_params(struct dc_bias_and_scale *bias_and_scale, ++void dcn10_build_prescale_params(struct dc_bias_and_scale *bias_and_scale, + const struct dc_plane_state *plane_state) + { + if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN +@@ -1951,7 +1951,7 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) + plane_state->color_space); + + //set scale and bias registers +- build_prescale_params(&bns_params, plane_state); ++ dcn10_build_prescale_params(&bns_params, plane_state); + if (dpp->funcs->dpp_program_bias_and_scale) + dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); + } +@@ -2640,9 +2640,6 @@ static void dcn10_wait_for_mpcc_disconnect( + res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); + pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; + hubp->funcs->set_blank(hubp, true); +- /*DC_LOG_ERROR(dc->ctx->logger, +- "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n", +- i);*/ + } + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +index 4b3b27a5d23b..ef94d6b15843 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +@@ -83,6 +83,8 @@ struct pipe_ctx *find_top_pipe_for_stream( + + int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx); + ++void dcn10_build_prescale_params(struct dc_bias_and_scale *bias_and_scale, ++ const struct dc_plane_state *plane_state); + void lock_all_pipes(struct dc *dc, + struct dc_state *context, + bool lock); +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 6f5ab05d6467..d61efa068c9a 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -212,6 +212,25 @@ struct plane_resource { + struct dcn_fe_bandwidth bw; + }; + ++union pipe_update_flags { ++ struct { ++ uint32_t enable : 1; ++ uint32_t disable : 1; ++ uint32_t odm : 1; ++ uint32_t global_sync : 1; ++ uint32_t opp_changed : 1; ++ uint32_t tg_changed : 1; ++ uint32_t mpcc : 1; ++ uint32_t dppclk : 1; ++ uint32_t hubp_interdependent : 1; ++ uint32_t hubp_rq_dlg_ttu : 1; ++ uint32_t gamut_remap : 1; ++ uint32_t scaler : 1; ++ uint32_t viewport : 1; ++ } bits; ++ uint32_t raw; ++}; ++ + struct pipe_ctx { + struct dc_plane_state *plane_state; + struct dc_stream_state *stream; +@@ -234,6 +253,7 @@ struct pipe_ctx { + struct _vcs_dpi_display_rq_regs_st rq_regs; + struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; + #endif ++ union pipe_update_flags update_flags; + }; + + struct resource_context { +-- +2.17.1 + |