aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1954-drm-amd-display-Add-ASICREV_IS_PICASSO.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1954-drm-amd-display-Add-ASICREV_IS_PICASSO.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1954-drm-amd-display-Add-ASICREV_IS_PICASSO.patch39
1 files changed, 39 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1954-drm-amd-display-Add-ASICREV_IS_PICASSO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1954-drm-amd-display-Add-ASICREV_IS_PICASSO.patch
new file mode 100644
index 00000000..c54ecb95
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1954-drm-amd-display-Add-ASICREV_IS_PICASSO.patch
@@ -0,0 +1,39 @@
+From 848ff68af9873a5c2aa382efdd5a1f9fe1c3f165 Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Tue, 14 May 2019 09:05:37 -0400
+Subject: [PATCH 1954/2940] drm/amd/display: Add ASICREV_IS_PICASSO
+
+[WHY]
+We only want to load DMCU FW on Picasso and Raven 2, not on Raven 1.
+
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index 1a9b7507784f..072d8d7debf5 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -139,13 +139,14 @@
+ #define RAVEN1_F0 0xF0
+ #define RAVEN_UNKNOWN 0xFF
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+-#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
+-#endif /* DCN1_01 */
+ #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
+ #define RAVEN1_F0 0xF0
+ #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
+
++#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
++#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
++#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
++#endif /* DCN1_01 */
+
+ #define FAMILY_RV 142 /* DCN 1*/
+
+--
+2.17.1
+