diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1925-drm-amdgpu-RLC-to-program-regs-for-Vega10-SR-IOV.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1925-drm-amdgpu-RLC-to-program-regs-for-Vega10-SR-IOV.patch | 369 |
1 files changed, 369 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1925-drm-amdgpu-RLC-to-program-regs-for-Vega10-SR-IOV.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1925-drm-amdgpu-RLC-to-program-regs-for-Vega10-SR-IOV.patch new file mode 100644 index 00000000..45b181cf --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1925-drm-amdgpu-RLC-to-program-regs-for-Vega10-SR-IOV.patch @@ -0,0 +1,369 @@ +From 6d0ab929be9cae1306153f431673f0c69cb668b4 Mon Sep 17 00:00:00 2001 +From: Trigger Huang <Trigger.Huang@amd.com> +Date: Thu, 2 May 2019 20:33:49 +0800 +Subject: [PATCH 1925/2940] drm/amdgpu: RLC to program regs for Vega10 SR-IOV + +Under Vega10 SR-IOV, with new RLC's new feature, VF should call RLC +to program some registers if supported + +Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 100 +++++++++++------------ + drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 20 ++--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 12 ++- + 3 files changed, 70 insertions(+), 62 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 2a19dd24b82c..354d0feb545a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1837,7 +1837,7 @@ static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh + else + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); + +- WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); ++ WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); + } + + static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) +@@ -1905,8 +1905,8 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) + for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { + soc15_grbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ +- WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); +- WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); ++ WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); ++ WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); + } + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +@@ -1917,7 +1917,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) + u32 tmp; + int i; + +- WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); ++ WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); + + gfx_v9_0_tiling_mode_table_init(adev); + +@@ -1964,7 +1964,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) + */ + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + +- WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, ++ WREG32_SOC15_RLC(GC, 0, mmPA_SC_FIFO_SIZE, + (adev->gfx.config.sc_prim_fifo_size_frontend << + PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_prim_fifo_size_backend << +@@ -2031,11 +2031,11 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, + static void gfx_v9_0_init_csb(struct amdgpu_device *adev) + { + /* csib */ +- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), ++ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), + adev->gfx.rlc.clear_state_gpu_addr >> 32); +- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), ++ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), + adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); +- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), ++ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), + adev->gfx.rlc.clear_state_size); + } + +@@ -2505,7 +2505,7 @@ static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + adev->gfx.gfx_ring[i].sched.ready = false; + } +- WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); ++ WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); + udelay(50); + } + +@@ -2703,9 +2703,9 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) + int i; + + if (enable) { +- WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); + } else { +- WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, ++ WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, + (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); + for (i = 0; i < adev->gfx.num_compute_rings; i++) + adev->gfx.compute_ring[i].sched.ready = false; +@@ -2766,9 +2766,9 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) + tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); + tmp &= 0xffffff00; + tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); +- WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); ++ WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); + tmp |= 0x80; +- WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); ++ WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); + } + + static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) +@@ -2986,67 +2986,67 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) + /* disable wptr polling */ + WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); + +- WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, + mqd->cp_hqd_eop_base_addr_lo); +- WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, + mqd->cp_hqd_eop_base_addr_hi); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ +- WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, + mqd->cp_hqd_eop_control); + + /* enable doorbell? */ +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, + mqd->cp_hqd_pq_doorbell_control); + + /* disable the queue if it's active */ + if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { +- WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); + for (j = 0; j < adev->usec_timeout; j++) { + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } +- WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, + mqd->cp_hqd_dequeue_request); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, + mqd->cp_hqd_pq_rptr); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, + mqd->cp_hqd_pq_wptr_lo); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, + mqd->cp_hqd_pq_wptr_hi); + } + + /* set the pointer to the MQD */ +- WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, ++ WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, + mqd->cp_mqd_base_addr_lo); +- WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, ++ WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, + mqd->cp_mqd_base_addr_hi); + + /* set MQD vmid to 0 */ +- WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, ++ WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, + mqd->cp_mqd_control); + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, + mqd->cp_hqd_pq_base_lo); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, + mqd->cp_hqd_pq_base_hi); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, + mqd->cp_hqd_pq_control); + + /* set the wb address whether it's enabled or not */ +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, + mqd->cp_hqd_pq_rptr_report_addr_lo); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, + mqd->cp_hqd_pq_rptr_report_addr_hi); + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, + mqd->cp_hqd_pq_wptr_poll_addr_lo); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, + mqd->cp_hqd_pq_wptr_poll_addr_hi); + + /* enable the doorbell if requested */ +@@ -3061,19 +3061,19 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) + mqd->cp_hqd_pq_doorbell_control); + + /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, + mqd->cp_hqd_pq_wptr_lo); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, + mqd->cp_hqd_pq_wptr_hi); + + /* set the vmid for the queue */ +- WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); + +- WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, + mqd->cp_hqd_persistent_state); + + /* activate the queue */ +- WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, + mqd->cp_hqd_active); + + if (ring->use_doorbell) +@@ -3090,7 +3090,7 @@ static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) + /* disable the queue if it's active */ + if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { + +- WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); + + for (j = 0; j < adev->usec_timeout; j++) { + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) +@@ -3102,21 +3102,21 @@ static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) + DRM_DEBUG("KIQ dequeue request failed.\n"); + + /* Manual disable if dequeue request times out */ +- WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); + } + +- WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, + 0); + } + +- WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0); +- WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0); +- WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); +- WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); + + return 0; + } +@@ -4576,8 +4576,8 @@ static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev, + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + +- WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority); +- WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority); ++ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority); + + soc15_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +index f2eb96c506c0..4c5df304adbd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +@@ -66,12 +66,12 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) + uint64_t value; + + /* Program the AGP BAR */ +- WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); +- WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); +- WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); + + /* Program the system aperture low logical page number. */ +- WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, + min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); + + if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8) +@@ -81,11 +81,11 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) + * workaround that increase system aperture high address (add 1) + * to get rid of the VM fault and hardware hang. + */ +- WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + max((adev->gmc.fb_end >> 18) + 0x1, + adev->gmc.agp_end >> 18)); + else +- WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); + + /* Set default page address. */ +@@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) + MTYPE, MTYPE_UC);/* XXX for emulation. */ + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); + +- WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); + } + + static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) +@@ -262,9 +262,9 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) + * VF copy registers so vbios post doesn't program them, for + * SRIOV driver need to program them + */ +- WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE, + adev->gmc.vram_start >> 24); +- WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP, + adev->gmc.vram_end >> 24); + } + +@@ -298,7 +298,7 @@ void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) + MC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, + 0); +- WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); ++ WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); + + /* Setup L2 cache */ + WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 1f7a56e01ff9..7bedc02b8d7a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -232,7 +232,7 @@ void soc15_grbm_select(struct amdgpu_device *adev, + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); + +- WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); ++ WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); + } + + static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) +@@ -387,7 +387,15 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, + tmp &= ~(entry->and_mask); + tmp |= entry->or_mask; + } +- WREG32(reg, tmp); ++ ++ if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || ++ reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || ++ reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || ++ reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) ++ WREG32_RLC(reg, tmp); ++ else ++ WREG32(reg, tmp); ++ + } + + } +-- +2.17.1 + |