diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1923-drm-amdgpu-Skip-setting-some-regs-under-Vega10-VF.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1923-drm-amdgpu-Skip-setting-some-regs-under-Vega10-VF.patch | 178 |
1 files changed, 178 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1923-drm-amdgpu-Skip-setting-some-regs-under-Vega10-VF.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1923-drm-amdgpu-Skip-setting-some-regs-under-Vega10-VF.patch new file mode 100644 index 00000000..796123fa --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1923-drm-amdgpu-Skip-setting-some-regs-under-Vega10-VF.patch @@ -0,0 +1,178 @@ +From ef982bfb1ebf9c6317647207dded5ddf081b5caa Mon Sep 17 00:00:00 2001 +From: Trigger Huang <Trigger.Huang@amd.com> +Date: Mon, 4 Mar 2019 12:30:58 +0800 +Subject: [PATCH 1923/2940] drm/amdgpu: Skip setting some regs under Vega10 VF + +For Vega10 SR-IOV VF, skip setting some regs due to: +1, host will program them +2, avoid VF register programming violations + +Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++++++++------ + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++ + drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 25 ++++++++++++++++++++----- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 14 ++++++++------ + drivers/gpu/drm/amd/amdgpu/soc15.c | 16 +++++++++++----- + 5 files changed, 50 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 382c8d3c82da..2a19dd24b82c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -308,12 +308,14 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_VEGA10: +- soc15_program_register_sequence(adev, +- golden_settings_gc_9_0, +- ARRAY_SIZE(golden_settings_gc_9_0)); +- soc15_program_register_sequence(adev, +- golden_settings_gc_9_0_vg10, +- ARRAY_SIZE(golden_settings_gc_9_0_vg10)); ++ if (!amdgpu_virt_support_skip_setting(adev)) { ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_9_0, ++ ARRAY_SIZE(golden_settings_gc_9_0)); ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_9_0_vg10, ++ ARRAY_SIZE(golden_settings_gc_9_0_vg10)); ++ } + break; + case CHIP_VEGA12: + soc15_program_register_sequence(adev, +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 0dd8fac10515..69c8de9f8b58 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -1093,6 +1093,9 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) + + switch (adev->asic_type) { + case CHIP_VEGA10: ++ if (amdgpu_virt_support_skip_setting(adev)) ++ break; ++ /* fall through */ + case CHIP_VEGA20: + soc15_program_register_sequence(adev, + golden_settings_mmhub_1_0_0, +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +index 95cffc8fddb4..a91a7a29a8cb 100644 +--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +@@ -106,6 +106,9 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); + ++ if (amdgpu_virt_support_skip_setting(adev)) ++ return; ++ + /* Set default page address. */ + value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + + adev->vm_manager.vram_base_offset; +@@ -151,6 +154,9 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) + { + uint32_t tmp; + ++ if (amdgpu_virt_support_skip_setting(adev)) ++ return; ++ + /* Setup L2 cache */ + tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); +@@ -197,6 +203,9 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) + + static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) + { ++ if (amdgpu_virt_support_skip_setting(adev)) ++ return; ++ + WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, + 0XFFFFFFFF); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, +@@ -333,11 +342,13 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) + 0); + WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); + +- /* Setup L2 cache */ +- tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); +- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); +- WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); +- WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); ++ if (!amdgpu_virt_support_skip_setting(adev)) { ++ /* Setup L2 cache */ ++ tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); ++ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); ++ WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); ++ WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); ++ } + } + + /** +@@ -349,6 +360,10 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) + void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) + { + u32 tmp; ++ ++ if (amdgpu_virt_support_skip_setting(adev)) ++ return; ++ + tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index c139e8db8d95..9daaa12fdb3e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -210,12 +210,14 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_VEGA10: +- soc15_program_register_sequence(adev, +- golden_settings_sdma_4, +- ARRAY_SIZE(golden_settings_sdma_4)); +- soc15_program_register_sequence(adev, +- golden_settings_sdma_vg10, +- ARRAY_SIZE(golden_settings_sdma_vg10)); ++ if (!amdgpu_virt_support_skip_setting(adev)) { ++ soc15_program_register_sequence(adev, ++ golden_settings_sdma_4, ++ ARRAY_SIZE(golden_settings_sdma_4)); ++ soc15_program_register_sequence(adev, ++ golden_settings_sdma_vg10, ++ ARRAY_SIZE(golden_settings_sdma_vg10)); ++ } + break; + case CHIP_VEGA12: + soc15_program_register_sequence(adev, +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 43b64d2237cf..1f7a56e01ff9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -1023,11 +1023,17 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev) + int i; + struct amdgpu_ring *ring; + +- for (i = 0; i < adev->sdma.num_instances; i++) { +- ring = &adev->sdma.instance[i].ring; +- adev->nbio_funcs->sdma_doorbell_range(adev, i, +- ring->use_doorbell, ring->doorbell_index, +- adev->doorbell_index.sdma_doorbell_range); ++ /* Two reasons to skip ++ * 1, Host driver already programmed them ++ * 2, To avoid registers program violations in SR-IOV ++ */ ++ if (!amdgpu_virt_support_skip_setting(adev)) { ++ for (i = 0; i < adev->sdma.num_instances; i++) { ++ ring = &adev->sdma.instance[i].ring; ++ adev->nbio_funcs->sdma_doorbell_range(adev, i, ++ ring->use_doorbell, ring->doorbell_index, ++ adev->doorbell_index.sdma_doorbell_range); ++ } + } + + adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, +-- +2.17.1 + |