diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1922-drm-amdgpu-Support-PSP-VMR-ring-for-Vega10-VF.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1922-drm-amdgpu-Support-PSP-VMR-ring-for-Vega10-VF.patch | 201 |
1 files changed, 201 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1922-drm-amdgpu-Support-PSP-VMR-ring-for-Vega10-VF.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1922-drm-amdgpu-Support-PSP-VMR-ring-for-Vega10-VF.patch new file mode 100644 index 00000000..709a2e60 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1922-drm-amdgpu-Support-PSP-VMR-ring-for-Vega10-VF.patch @@ -0,0 +1,201 @@ +From dadcd4c016d264c31426f2cd7e65ff1b7bd35e84 Mon Sep 17 00:00:00 2001 +From: Trigger Huang <Trigger.Huang@amd.com> +Date: Mon, 25 Feb 2019 18:41:02 +0800 +Subject: [PATCH 1922/2940] drm/amdgpu: Support PSP VMR ring for Vega10 VF + +Add VMR ring support for Vega10 SR-IOV VF if PSP supported + +Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 131 +++++++++++++++++++------- + 1 file changed, 99 insertions(+), 32 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +index 143f0fae69d5..3f5827764df0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +@@ -50,6 +50,10 @@ MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); + + static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; + ++static bool psp_v3_1_support_vmr_ring(struct psp_context *psp); ++static int psp_v3_1_ring_stop(struct psp_context *psp, ++ enum psp_ring_type ring_type); ++ + static int psp_v3_1_init_microcode(struct psp_context *psp) + { + struct amdgpu_device *adev = psp->adev; +@@ -296,27 +300,57 @@ static int psp_v3_1_ring_create(struct psp_context *psp, + + psp_v3_1_reroute_ih(psp); + +- /* Write low address of the ring to C2PMSG_69 */ +- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); +- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); +- /* Write high address of the ring to C2PMSG_70 */ +- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); +- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); +- /* Write size of ring to C2PMSG_71 */ +- psp_ring_reg = ring->ring_size; +- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); +- /* Write the ring initialization command to C2PMSG_64 */ +- psp_ring_reg = ring_type; +- psp_ring_reg = psp_ring_reg << 16; +- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); +- +- /* there might be handshake issue with hardware which needs delay */ +- mdelay(20); +- +- /* Wait for response flag (bit 31) in C2PMSG_64 */ +- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), +- 0x80000000, 0x8000FFFF, false); ++ if (psp_v3_1_support_vmr_ring(psp)) { ++ ret = psp_v3_1_ring_stop(psp, ring_type); ++ if (ret) { ++ DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n"); ++ return ret; ++ } ++ ++ /* Write low address of the ring to C2PMSG_102 */ ++ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); ++ /* Write high address of the ring to C2PMSG_103 */ ++ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); ++ /* No size initialization for sriov */ ++ /* Write the ring initialization command to C2PMSG_101 */ ++ psp_ring_reg = ring_type; ++ psp_ring_reg = psp_ring_reg << 16; ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); ++ ++ /* there might be hardware handshake issue which needs delay */ ++ mdelay(20); ++ ++ /* Wait for response flag (bit 31) in C2PMSG_101 */ ++ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, ++ mmMP0_SMN_C2PMSG_101), 0x80000000, ++ 0x8000FFFF, false); ++ } else { ++ ++ /* Write low address of the ring to C2PMSG_69 */ ++ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); ++ /* Write high address of the ring to C2PMSG_70 */ ++ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); ++ /* Write size of ring to C2PMSG_71 */ ++ psp_ring_reg = ring->ring_size; ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); ++ /* Write the ring initialization command to C2PMSG_64 */ ++ psp_ring_reg = ring_type; ++ psp_ring_reg = psp_ring_reg << 16; ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); ++ ++ /* there might be hardware handshake issue which needs delay */ ++ mdelay(20); ++ ++ /* Wait for response flag (bit 31) in C2PMSG_64 */ ++ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, ++ mmMP0_SMN_C2PMSG_64), 0x80000000, ++ 0x8000FFFF, false); + ++ } + return ret; + } + +@@ -327,16 +361,31 @@ static int psp_v3_1_ring_stop(struct psp_context *psp, + unsigned int psp_ring_reg = 0; + struct amdgpu_device *adev = psp->adev; + +- /* Write the ring destroy command to C2PMSG_64 */ +- psp_ring_reg = 3 << 16; +- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); +- +- /* there might be handshake issue with hardware which needs delay */ +- mdelay(20); +- +- /* Wait for response flag (bit 31) in C2PMSG_64 */ +- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), +- 0x80000000, 0x80000000, false); ++ if (psp_v3_1_support_vmr_ring(psp)) { ++ /* Write the Destroy GPCOM ring command to C2PMSG_101 */ ++ psp_ring_reg = GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING; ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); ++ ++ /* there might be handshake issue which needs delay */ ++ mdelay(20); ++ ++ /* Wait for response flag (bit 31) in C2PMSG_101 */ ++ ret = psp_wait_for(psp, ++ SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), ++ 0x80000000, 0x80000000, false); ++ } else { ++ /* Write the ring destroy command to C2PMSG_64 */ ++ psp_ring_reg = 3 << 16; ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); ++ ++ /* there might be handshake issue which needs delay */ ++ mdelay(20); ++ ++ /* Wait for response flag (bit 31) in C2PMSG_64 */ ++ ret = psp_wait_for(psp, ++ SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), ++ 0x80000000, 0x80000000, false); ++ } + + return ret; + } +@@ -375,7 +424,10 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp, + uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; + + /* KM (GPCOM) prepare write pointer */ +- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); ++ if (psp_v3_1_support_vmr_ring(psp)) ++ psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); ++ else ++ psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); + + /* Update KM RB frame pointer to new frame */ + /* write_frame ptr increments by size of rb_frame in bytes */ +@@ -404,7 +456,13 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp, + + /* Update the write Pointer in DWORDs */ + psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; +- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); ++ if (psp_v3_1_support_vmr_ring(psp)) { ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); ++ /* send interrupt to PSP for SRIOV ring write pointer update */ ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, ++ GFX_CTRL_CMD_ID_CONSUME_CMD); ++ } else ++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); + + return 0; + } +@@ -574,6 +632,14 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp) + return 0; + } + ++static bool psp_v3_1_support_vmr_ring(struct psp_context *psp) ++{ ++ if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version >= 0x80455) ++ return true; ++ ++ return false; ++} ++ + static const struct psp_funcs psp_v3_1_funcs = { + .init_microcode = psp_v3_1_init_microcode, + .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, +@@ -586,6 +652,7 @@ static const struct psp_funcs psp_v3_1_funcs = { + .compare_sram_data = psp_v3_1_compare_sram_data, + .smu_reload_quirk = psp_v3_1_smu_reload_quirk, + .mode1_reset = psp_v3_1_mode1_reset, ++ .support_vmr_ring = psp_v3_1_support_vmr_ring, + }; + + void psp_v3_1_set_psp_funcs(struct psp_context *psp) +-- +2.17.1 + |