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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1921-drm-amdgpu-call-psp-to-program-ih-cntl-in-SR-IOV.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1921-drm-amdgpu-call-psp-to-program-ih-cntl-in-SR-IOV.patch173
1 files changed, 173 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1921-drm-amdgpu-call-psp-to-program-ih-cntl-in-SR-IOV.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1921-drm-amdgpu-call-psp-to-program-ih-cntl-in-SR-IOV.patch
new file mode 100644
index 00000000..40a5e4eb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1921-drm-amdgpu-call-psp-to-program-ih-cntl-in-SR-IOV.patch
@@ -0,0 +1,173 @@
+From 036352bd302ea77fe8704d4d3b127f8d1355e1f7 Mon Sep 17 00:00:00 2001
+From: Trigger Huang <Trigger.Huang@amd.com>
+Date: Sun, 28 Apr 2019 18:03:17 +0800
+Subject: [PATCH 1921/2940] drm/amdgpu: call psp to program ih cntl in SR-IOV
+
+call psp to program ih cntl in SR-IOV if supported
+
+Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 91 +++++++++++++++++++++++---
+ 1 file changed, 82 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+index 8d89ab7f0ae8..5f54acc70fec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+@@ -48,14 +48,29 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
+
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
++ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
++ return;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
++ }
+ adev->irq.ih.enabled = true;
+
+ if (adev->irq.ih1.ring_size) {
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+ RB_ENABLE, 1);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
++ ih_rb_cntl)) {
++ DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
++ return;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
++ }
+ adev->irq.ih1.enabled = true;
+ }
+
+@@ -63,7 +78,15 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+ RB_ENABLE, 1);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
++ ih_rb_cntl)) {
++ DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
++ return;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
++ }
+ adev->irq.ih2.enabled = true;
+ }
+ }
+@@ -81,7 +104,15 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
+
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
++ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
++ return;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
++ }
++
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
+@@ -92,7 +123,15 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+ RB_ENABLE, 0);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
++ ih_rb_cntl)) {
++ DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
++ return;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
++ }
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+@@ -104,7 +143,16 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+ RB_ENABLE, 0);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
++ ih_rb_cntl)) {
++ DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
++ return;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
++ }
++
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+@@ -187,7 +235,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
+ !!adev->irq.msi_enabled);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
++
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
++ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
++ return -ETIMEDOUT;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
++ }
+
+ /* set the writeback address whether it's enabled or not */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
+@@ -214,7 +270,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ WPTR_OVERFLOW_ENABLE, 0);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ RB_FULL_DRAIN_ENABLE, 1);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
++ ih_rb_cntl)) {
++ DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
++ return -ETIMEDOUT;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
++ }
+
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+@@ -232,7 +296,16 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
++
++ if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
++ ih_rb_cntl)) {
++ DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
++ return -ETIMEDOUT;
++ }
++ } else {
++ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
++ }
+
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 02:05:45 +0000