diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1885-drm-amd-display-fix-multi-display-seamless-boot-case.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1885-drm-amd-display-fix-multi-display-seamless-boot-case.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1885-drm-amd-display-fix-multi-display-seamless-boot-case.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1885-drm-amd-display-fix-multi-display-seamless-boot-case.patch new file mode 100644 index 00000000..f6404f3f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1885-drm-amd-display-fix-multi-display-seamless-boot-case.patch @@ -0,0 +1,68 @@ +From 97f9b43a5247db7d88c74c50c5a4ccf66ed100fa Mon Sep 17 00:00:00 2001 +From: Anthony Koo <anthony.koo@amd.com> +Date: Fri, 12 Apr 2019 21:23:45 -0400 +Subject: [PATCH 1885/2940] drm/amd/display: fix multi display seamless boot + case + +[Why] +There is a scenario that causes eDP to become blank if +there are multiple displays connected, and the external +display is set as the primary display such that the first +flip comes to the external display. + +In this scenario, we call our optimize function before +the eDP even has a chance to flip. + +[How] +There is a check that prevents bandwidth optimize from +occurring before first flip is complete on the seamless boot +display. +But actually it assumed the seamless boot display is the +first one to flip. But in this scenario it is not. +Modify the check to ensure the steam with the seamless +boot flag set is the one that has completed the first flip. + +Change-Id: I0a7337077eaa8530e7c01ea75b7b2326159bc48d +Signed-off-by: Anthony Koo <anthony.koo@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 102af2d2b84c..03abbf6ce596 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1150,9 +1150,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + const struct dc_link *link = context->streams[i]->link; + struct dc_stream_status *status; + +- if (context->streams[i]->apply_seamless_boot_optimization) +- context->streams[i]->apply_seamless_boot_optimization = false; +- + if (!context->streams[i]->mode_changed) + continue; + +@@ -1804,10 +1801,15 @@ static void commit_planes_for_stream(struct dc *dc, + if (dc->optimize_seamless_boot && surface_count > 0) { + /* Optimize seamless boot flag keeps clocks and watermarks high until + * first flip. After first flip, optimization is required to lower +- * bandwidth. ++ * bandwidth. Important to note that it is expected UEFI will ++ * only light up a single display on POST, therefore we only expect ++ * one stream with seamless boot flag set. + */ +- dc->optimize_seamless_boot = false; +- dc->optimized_required = true; ++ if (stream->apply_seamless_boot_optimization) { ++ stream->apply_seamless_boot_optimization = false; ++ dc->optimize_seamless_boot = false; ++ dc->optimized_required = true; ++ } + } + + if (update_type == UPDATE_TYPE_FULL && !dc->optimize_seamless_boot) { +-- +2.17.1 + |