diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1874-drm-amdgpu-Reorganize-amdgpu_gmc_flush_gpu_tlb-for-k.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1874-drm-amdgpu-Reorganize-amdgpu_gmc_flush_gpu_tlb-for-k.patch | 211 |
1 files changed, 211 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1874-drm-amdgpu-Reorganize-amdgpu_gmc_flush_gpu_tlb-for-k.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1874-drm-amdgpu-Reorganize-amdgpu_gmc_flush_gpu_tlb-for-k.patch new file mode 100644 index 00000000..e4d49093 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1874-drm-amdgpu-Reorganize-amdgpu_gmc_flush_gpu_tlb-for-k.patch @@ -0,0 +1,211 @@ +From 48d66eb7a62f14699795c7f7a259e86a72267ce3 Mon Sep 17 00:00:00 2001 +From: Yong Zhao <Yong.Zhao@amd.com> +Date: Fri, 12 Oct 2018 17:17:05 -0400 +Subject: [PATCH 1874/2940] drm/amdgpu: Reorganize amdgpu_gmc_flush_gpu_tlb() + for kfd to use +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add a flush_type parameter to that series of functions. + +Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> +Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 4 ++-- + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 5 +++-- + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5 +++-- + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 ++++++++++---------- + 6 files changed, 22 insertions(+), 20 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +index 11fea28f8ad3..9a212aa4c177 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +@@ -248,7 +248,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, + } + mb(); + amdgpu_asic_flush_hdp(adev, NULL); +- amdgpu_gmc_flush_gpu_tlb(adev, 0); ++ amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); + return 0; + } + +@@ -331,7 +331,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, + + mb(); + amdgpu_asic_flush_hdp(adev, NULL); +- amdgpu_gmc_flush_gpu_tlb(adev, 0); ++ amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); + return 0; + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +index 13479c3e6bfb..e43036cefb64 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +@@ -90,7 +90,7 @@ struct amdgpu_vmhub { + struct amdgpu_gmc_funcs { + /* flush the vm tlb via mmio */ + void (*flush_gpu_tlb)(struct amdgpu_device *adev, +- uint32_t vmid); ++ uint32_t vmid, uint32_t flush_type); + /* flush the vm tlb via ring */ + uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, + uint64_t pd_addr); +@@ -180,7 +180,7 @@ struct amdgpu_gmc { + struct ras_common_if *ras_if; + }; + +-#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid)) ++#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type)) + #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) + #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) + #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +index 38abcefda4e9..2edb7fc84398 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +@@ -359,7 +359,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) + return 0; + } + +-static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) ++static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, ++ uint32_t vmid, uint32_t flush_type) + { + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); + } +@@ -567,7 +568,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) + else + gmc_v6_0_set_fault_enable_default(adev, true); + +- gmc_v6_0_flush_gpu_tlb(adev, 0); ++ gmc_v6_0_flush_gpu_tlb(adev, 0, 0); + dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", + (unsigned)(adev->gmc.gart_size >> 20), + (unsigned long long)table_addr); +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +index 3796cf6e8bc5..655bc4690958 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +@@ -430,7 +430,8 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) + * + * Flush the TLB for the requested page table (CIK). + */ +-static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) ++static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, ++ uint32_t vmid, uint32_t flush_type) + { + /* bits 0-15 are the VM contexts0-15 */ + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); +@@ -673,7 +674,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) + WREG32(mmCHUB_CONTROL, tmp); + } + +- gmc_v7_0_flush_gpu_tlb(adev, 0); ++ gmc_v7_0_flush_gpu_tlb(adev, 0, 0); + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + (unsigned)(adev->gmc.gart_size >> 20), + (unsigned long long)table_addr); +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +index 2f459a434cde..a27a5ae75438 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +@@ -638,7 +638,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) + * Flush the TLB for the requested page table (VI). + */ + static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, +- uint32_t vmid) ++ uint32_t vmid, uint32_t flush_type) + { + /* bits 0-15 are the VM contexts0-15 */ + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); +@@ -923,7 +923,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) + else + gmc_v8_0_set_fault_enable_default(adev, true); + +- gmc_v8_0_flush_gpu_tlb(adev, 0); ++ gmc_v8_0_flush_gpu_tlb(adev, 0, 0); + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + (unsigned)(adev->gmc.gart_size >> 20), + (unsigned long long)table_addr); +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 3927fbb11c0d..842ab8a1fbd1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -373,14 +373,14 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) + adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; + } + +-static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid) ++static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, ++ uint32_t flush_type) + { + u32 req = 0; + +- /* invalidate using legacy mode on vmid*/ + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); +- req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); ++ req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); +@@ -442,24 +442,24 @@ static signed long amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev, + */ + + /** +- * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback ++ * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush ++ * @flush_type: the flush type + * +- * Flush the TLB for the requested page table. ++ * Flush the TLB for the requested page table using certain type. + */ + static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, +- uint32_t vmid) ++ uint32_t vmid, uint32_t flush_type) + { +- /* Use register 17 for GART */ + const unsigned eng = 17; + unsigned i, j; + int r; + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &adev->vmhub[i]; +- u32 tmp = gmc_v9_0_get_invalidate_req(vmid); ++ u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); + + if (adev->gfx.kiq.ring.sched.ready && + (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && +@@ -509,7 +509,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, + { + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; +- uint32_t req = gmc_v9_0_get_invalidate_req(vmid); ++ uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); + unsigned eng = ring->vm_inv_eng; + + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), +@@ -1220,7 +1220,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + + gfxhub_v1_0_set_fault_enable_default(adev, value); + mmhub_v1_0_set_fault_enable_default(adev, value); +- gmc_v9_0_flush_gpu_tlb(adev, 0); ++ gmc_v9_0_flush_gpu_tlb(adev, 0, 0); + + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + (unsigned)(adev->gmc.gart_size >> 20), +-- +2.17.1 + |