diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1871-Revert-drm-amdgpu-display-Replace-CONFIG_DRM_AMD_DC_.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1871-Revert-drm-amdgpu-display-Replace-CONFIG_DRM_AMD_DC_.patch | 529 |
1 files changed, 529 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1871-Revert-drm-amdgpu-display-Replace-CONFIG_DRM_AMD_DC_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1871-Revert-drm-amdgpu-display-Replace-CONFIG_DRM_AMD_DC_.patch new file mode 100644 index 00000000..2a357f1d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1871-Revert-drm-amdgpu-display-Replace-CONFIG_DRM_AMD_DC_.patch @@ -0,0 +1,529 @@ +From 0647ad7134953635b24be8a1037a6fefe210f5d2 Mon Sep 17 00:00:00 2001 +From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com> +Date: Thu, 16 Aug 2018 15:44:38 -0400 +Subject: [PATCH 1871/2940] Revert "drm/amdgpu/display: Replace + CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86" +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This reverts commit 8624c3c4dbfe24fc6740687236a2e196f5f4bfb0. + +We need CONFIG_DRM_AMD_DC_DCN1_0 to guard code that is using fp math. + +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> +Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- + drivers/gpu/drm/amd/display/dc/Makefile | 2 +- + .../display/dc/bios/command_table_helper2.c | 2 +- + drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 +- + drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++--- + .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 +- + .../gpu/drm/amd/display/dc/core/dc_resource.c | 12 +++++------ + drivers/gpu/drm/amd/display/dc/dc.h | 2 +- + .../drm/amd/display/dc/dce/dce_clock_source.h | 2 +- + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +++--- + .../amd/display/dc/dce/dce_stream_encoder.c | 20 +++++++++---------- + .../display/dc/dce110/dce110_hw_sequencer.c | 2 +- + drivers/gpu/drm/amd/display/dc/gpio/Makefile | 2 +- + .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 ++-- + .../drm/amd/display/dc/gpio/hw_translate.c | 4 ++-- + .../gpu/drm/amd/display/dc/inc/core_types.h | 6 +++--- + drivers/gpu/drm/amd/display/dc/irq/Makefile | 2 +- + .../gpu/drm/amd/display/dc/irq/irq_service.c | 2 +- + drivers/gpu/drm/amd/display/dc/os_types.h | 2 +- + 20 files changed, 45 insertions(+), 45 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 80a8ab9e19a2..4f3a9bb24412 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -2432,7 +2432,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) + case CHIP_VEGA10: + case CHIP_VEGA12: + case CHIP_VEGA20: +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: + case CHIP_PICASSO: + #endif +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 312e1fc71b47..6363cf04f41d 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -62,7 +62,7 @@ + #include <drm/drm_fb_helper.h> + #include <drm/drm_edid.h> + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "ivsrcid/irqsrcs_dcn_1_0.h" + + #include "dcn/dcn_1_0_offset.h" +@@ -1615,7 +1615,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) + return 0; + } + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* Register IRQ sources and initialize IRQ callbacks */ + static int dcn10_register_irq_handlers(struct amdgpu_device *adev) + { +@@ -2199,7 +2199,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) + goto fail; + } + break; +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: + case CHIP_PICASSO: + if (dcn10_register_irq_handlers(dm->adev)) { +@@ -2433,7 +2433,7 @@ static int dm_early_init(void *handle) + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + break; +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: + case CHIP_PICASSO: + adev->mode_info.num_crtc = 4; +diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile +index 327967d190ad..b8ddb4acccdb 100644 +--- a/drivers/gpu/drm/amd/display/dc/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/Makefile +@@ -25,7 +25,7 @@ + + DC_LIBS = basics bios calcs dce gpio irq virtual + +-ifdef CONFIG_X86 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + DC_LIBS += dcn10 dml + endif + +diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +index 1cc471c9afae..8196f3bb10c7 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +@@ -55,7 +55,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( + case DCE_VERSION_11_22: + *h = dal_cmd_tbl_helper_dce112_get_table2(); + return true; +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + *h = dal_cmd_tbl_helper_dce112_get_table2(); + return true; +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile +index 416500e51b8d..95f332ee3e7e 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile +@@ -38,7 +38,7 @@ CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare + + BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o + +-ifdef CONFIG_X86 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o + endif + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 0f04e6ec58e9..d7a47c6fdef2 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -638,7 +638,7 @@ static void destruct(struct dc *dc) + kfree(dc->bw_dceip); + dc->bw_dceip = NULL; + +-#ifdef CONFIG_X86 ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + kfree(dc->dcn_soc); + dc->dcn_soc = NULL; + +@@ -654,7 +654,7 @@ static bool construct(struct dc *dc, + struct dc_context *dc_ctx; + struct bw_calcs_dceip *dc_dceip; + struct bw_calcs_vbios *dc_vbios; +-#ifdef CONFIG_X86 ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box *dcn_soc; + struct dcn_ip_params *dcn_ip; + #endif +@@ -679,7 +679,7 @@ static bool construct(struct dc *dc, + } + + dc->bw_vbios = dc_vbios; +-#ifdef CONFIG_X86 ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL); + if (!dcn_soc) { + dm_error("%s: failed to create dcn_soc\n", __func__); +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +index 2d1bbe5092eb..5903e7822f98 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +@@ -347,7 +347,7 @@ void context_clock_trace( + struct dc *dc, + struct dc_state *context) + { +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + DC_LOGGER_INIT(dc->ctx->logger); + CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" + "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n", +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index eb43ecdc867c..eac7186e4f08 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -43,7 +43,7 @@ + #include "dce100/dce100_resource.h" + #include "dce110/dce110_resource.h" + #include "dce112/dce112_resource.h" +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/dcn10_resource.h" + #endif + #include "dce120/dce120_resource.h" +@@ -90,7 +90,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) + else + dc_version = DCE_VERSION_12_0; + break; +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case FAMILY_RV: + dc_version = DCN_VERSION_1_0; + #if defined(CONFIG_DRM_AMD_DC_DCN1_01) +@@ -145,7 +145,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, + init_data->num_virtual_links, dc); + break; + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + #if defined(CONFIG_DRM_AMD_DC_DCN1_01) + case DCN_VERSION_1_01: +@@ -1175,7 +1175,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( + + } + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + static int acquire_first_split_pipe( + struct resource_context *res_ctx, + const struct resource_pool *pool, +@@ -1249,7 +1249,7 @@ bool dc_add_plane_to_context( + + free_pipe = acquire_free_pipe_for_stream(context, pool, stream); + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (!free_pipe) { + int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); + if (pipe_idx >= 0) +@@ -1987,7 +1987,7 @@ enum dc_status resource_map_pool_resources( + /* acquire new resources */ + pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); + +-#ifdef CONFIG_X86 ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + if (pipe_idx < 0) + pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 7b040da89925..428175e05b12 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -395,7 +395,7 @@ struct dc { + /* Inputs into BW and WM calculations. */ + struct bw_calcs_dceip *bw_dceip; + struct bw_calcs_vbios *bw_vbios; +-#ifdef CONFIG_X86 ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box *dcn_soc; + struct dcn_ip_params *dcn_ip; + struct display_mode_lib dml; +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +index b8e0e2c2c465..1ed7695a76d3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +@@ -55,7 +55,7 @@ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + + #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +index 5729fdb77732..818536eea00a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +@@ -315,7 +315,7 @@ static void dce_get_psr_wait_loop( + return; + } + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + static void dcn10_get_dmcu_version(struct dmcu *dmcu) + { + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); +@@ -734,7 +734,7 @@ static const struct dmcu_funcs dce_funcs = { + .is_dmcu_initialized = dce_is_dmcu_initialized + }; + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + static const struct dmcu_funcs dcn10_funcs = { + .dmcu_init = dcn10_dmcu_init, + .load_iram = dcn10_dmcu_load_iram, +@@ -786,7 +786,7 @@ struct dmcu *dce_dmcu_create( + return &dmcu_dce->base; + } + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct dmcu *dcn10_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +index d87d78f87af0..d612e544d4a5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +@@ -135,7 +135,7 @@ static void dce110_update_generic_info_packet( + AFMT_GENERIC0_UPDATE, (packet_index == 0), + AFMT_GENERIC2_UPDATE, (packet_index == 2)); + } +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(AFMT_VBI_PACKET_CONTROL1)) { + switch (packet_index) { + case 0: +@@ -229,7 +229,7 @@ static void dce110_update_hdmi_info_packet( + HDMI_GENERIC1_SEND, send, + HDMI_GENERIC1_LINE, line); + break; +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case 4: + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, +@@ -275,7 +275,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( + enum dc_color_space output_color_space, + uint32_t enable_sdp_splitting) + { +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + uint32_t h_active_start; + uint32_t v_active_start; + uint32_t misc0 = 0; +@@ -327,7 +327,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( + if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) + REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->DP_VID_N_MUL) + REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); + #endif +@@ -338,7 +338,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( + break; + } + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_MSA_MISC)) + misc1 = REG_READ(DP_MSA_MISC); + #endif +@@ -372,7 +372,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( + /* set dynamic range and YCbCr range */ + + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + switch (crtc_timing->display_color_depth) { + case COLOR_DEPTH_666: + colorimetry_bpc = 0; +@@ -451,7 +451,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( + DP_DYN_RANGE, dynamic_range_rgb, + DP_YCBCR_RANGE, dynamic_range_ycbcr); + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_MSA_COLORIMETRY)) + REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); + +@@ -486,7 +486,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( + hw_crtc_timing.v_front_porch; + + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* start at begining of left border */ + if (REG(DP_MSA_TIMING_PARAM2)) + REG_SET_2(DP_MSA_TIMING_PARAM2, 0, +@@ -783,7 +783,7 @@ static void dce110_stream_encoder_update_hdmi_info_packets( + dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); + } + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->HDMI_DB_DISABLE) { + /* for bring up, disable dp double TODO */ + if (REG(HDMI_DB_CONTROL)) +@@ -821,7 +821,7 @@ static void dce110_stream_encoder_stop_hdmi_info_packets( + HDMI_GENERIC1_LINE, 0, + HDMI_GENERIC1_SEND, 0); + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* stop generic packets 2 & 3 on HDMI */ + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index d683a4720769..7ac50ab1b762 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1224,7 +1224,7 @@ static void program_scaler(const struct dc *dc, + { + struct tg_color color = {0}; + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* TOFPGA */ + if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) + return; +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile +index b9d9930a4974..562ee189d780 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile +@@ -61,7 +61,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) + ############################################################################### + # DCN 1x + ############################################################################### +-ifdef CONFIG_X86 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o + + AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10)) +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +index f4c91490d261..c2028c4744a6 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +@@ -43,7 +43,7 @@ + #include "dce80/hw_factory_dce80.h" + #include "dce110/hw_factory_dce110.h" + #include "dce120/hw_factory_dce120.h" +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/hw_factory_dcn10.h" + #endif + +@@ -82,7 +82,7 @@ bool dal_hw_factory_init( + case DCE_VERSION_12_1: + dal_hw_factory_dce120_init(factory); + return true; +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + dal_hw_factory_dcn10_init(factory); + return true; +diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +index aebf3a93ff4a..236ca28784a9 100644 +--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c ++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +@@ -43,7 +43,7 @@ + #include "dce80/hw_translate_dce80.h" + #include "dce110/hw_translate_dce110.h" + #include "dce120/hw_translate_dce120.h" +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/hw_translate_dcn10.h" + #endif + +@@ -79,7 +79,7 @@ bool dal_hw_translate_init( + case DCE_VERSION_12_1: + dal_hw_translate_dce120_init(translate); + return true; +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + dal_hw_translate_dcn10_init(translate); + return true; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 8cbd3b57f7a2..6f5ab05d6467 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -33,7 +33,7 @@ + #include "dc_bios_types.h" + #include "mem_input.h" + #include "hubp.h" +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "mpc.h" + #endif + +@@ -228,7 +228,7 @@ struct pipe_ctx { + struct pipe_ctx *top_pipe; + struct pipe_ctx *bottom_pipe; + +-#ifdef CONFIG_X86 ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct _vcs_dpi_display_dlg_regs_st dlg_regs; + struct _vcs_dpi_display_ttu_regs_st ttu_regs; + struct _vcs_dpi_display_rq_regs_st rq_regs; +@@ -297,7 +297,7 @@ struct dc_state { + + /* Note: these are big structures, do *not* put on stack! */ + struct dm_pp_display_configuration pp_display_cfg; +-#ifdef CONFIG_X86 ++#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_bw_internal_vars dcn_bw_vars; + #endif + +diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile +index a76ee600ecee..498515aad4a5 100644 +--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile +@@ -60,7 +60,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) + ############################################################################### + # DCN 1x + ############################################################################### +-ifdef CONFIG_X86 ++ifdef CONFIG_DRM_AMD_DC_DCN1_0 + IRQ_DCN1 = irq_service_dcn10.o + + AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1)) +diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +index ae3fd0a235ba..604bea01fc13 100644 +--- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c ++++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +@@ -36,7 +36,7 @@ + #include "dce120/irq_service_dce120.h" + + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include "dcn10/irq_service_dcn10.h" + #endif + +diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h +index dbe02aab4e17..f20996e71274 100644 +--- a/drivers/gpu/drm/amd/display/dc/os_types.h ++++ b/drivers/gpu/drm/amd/display/dc/os_types.h +@@ -50,7 +50,7 @@ + + #define dm_vlog(fmt, args) vprintk(fmt, args) + +-#ifdef CONFIG_X86 ++#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #include <asm/fpu/api.h> + #endif + +-- +2.17.1 + |