diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1823-drm-amd-powerplay-raven-4k-60hz-dp-monitor-always-fl.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1823-drm-amd-powerplay-raven-4k-60hz-dp-monitor-always-fl.patch | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1823-drm-amd-powerplay-raven-4k-60hz-dp-monitor-always-fl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1823-drm-amd-powerplay-raven-4k-60hz-dp-monitor-always-fl.patch new file mode 100644 index 00000000..e48cf011 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1823-drm-amd-powerplay-raven-4k-60hz-dp-monitor-always-fl.patch @@ -0,0 +1,89 @@ +From a7076e088febaba8e441589c98ef48ea77e3ad83 Mon Sep 17 00:00:00 2001 +From: hersen wu <hersenxs.wu@amd.com> +Date: Wed, 3 Apr 2019 16:14:08 -0400 +Subject: [PATCH 1823/2940] drm/amd/powerplay: raven 4k@60hz dp monitor always + flicking + +[WHY] clock unit mis-match between caller DC and SMU interface. + dc pass lock in mhz. the same unit as smu. no covert is needed. + +[HOW] remove covert_10k_to_mhz in smu interface + this fixes corruption issue with 4k @60 display and stutter + mode enable + +Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> +Signed-off-by: hersen wu <hersenxs.wu@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + .../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 17 ++++++----------- + include/uapi/linux/kfd_ioctl.h | 7 +++++++ + 2 files changed, 13 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +index 5f5dec9b97e2..9a595f7525e6 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +@@ -205,18 +205,13 @@ static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) + return 0; + } + +-static inline uint32_t convert_10k_to_mhz(uint32_t clock) +-{ +- return (clock + 99) / 100; +-} +- + static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) + { + struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); + + if (smu10_data->need_min_deep_sleep_dcefclk && +- smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) { +- smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock); ++ smu10_data->deep_sleep_dcefclk != clock) { ++ smu10_data->deep_sleep_dcefclk = clock; + smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetMinDeepSleepDcefclk, + smu10_data->deep_sleep_dcefclk); +@@ -229,8 +224,8 @@ static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t c + struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); + + if (smu10_data->dcf_actual_hard_min_freq && +- smu10_data->dcf_actual_hard_min_freq != convert_10k_to_mhz(clock)) { +- smu10_data->dcf_actual_hard_min_freq = convert_10k_to_mhz(clock); ++ smu10_data->dcf_actual_hard_min_freq != clock) { ++ smu10_data->dcf_actual_hard_min_freq = clock; + smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetHardMinDcefclkByFreq, + smu10_data->dcf_actual_hard_min_freq); +@@ -243,8 +238,8 @@ static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t cloc + struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); + + if (smu10_data->f_actual_hard_min_freq && +- smu10_data->f_actual_hard_min_freq != convert_10k_to_mhz(clock)) { +- smu10_data->f_actual_hard_min_freq = convert_10k_to_mhz(clock); ++ smu10_data->f_actual_hard_min_freq != clock) { ++ smu10_data->f_actual_hard_min_freq = clock; + smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetHardMinFclkByFreq, + smu10_data->f_actual_hard_min_freq); +diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h +index 71a87c36e2b6..e02346d26c59 100644 +--- a/include/uapi/linux/kfd_ioctl.h ++++ b/include/uapi/linux/kfd_ioctl.h +@@ -390,6 +390,13 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { + __u32 n_success; /* to/from KFD */ + }; + ++/* Register offset inside the remapped mmio page ++ */ ++enum kfd_mmio_remap { ++ KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, ++ KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, ++}; ++ + #define AMDKFD_IOCTL_BASE 'K' + #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) + #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) +-- +2.17.1 + |