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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1822-drm-amdgpu-Remap-hdp-coherency-registers.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1822-drm-amdgpu-Remap-hdp-coherency-registers.patch197
1 files changed, 197 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1822-drm-amdgpu-Remap-hdp-coherency-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1822-drm-amdgpu-Remap-hdp-coherency-registers.patch
new file mode 100644
index 00000000..99db195b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1822-drm-amdgpu-Remap-hdp-coherency-registers.patch
@@ -0,0 +1,197 @@
+From 93811cb3c190dee86fe629bc9bed2d586a86813f Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Thu, 4 Apr 2019 15:47:34 -0500
+Subject: [PATCH 1822/2940] drm/amdgpu: Remap hdp coherency registers
+
+Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
+to an empty page in mmio space. We will later map this page to process
+space so application can flush hdp. This can't be done properly at
+those registers' original location because it will expose more than
+desired registers to process space.
+
+v2: Use explicit register hole location
+v3: Moved remapped hdp registers into adev struct
+v4: Use more generic name for remapped page
+ Expose register offset in kfd_ioctl.h
+v5: Move hdp register remap function to nbio ip function
+v6: Fixed operator precedence issue and other bugs
+
+Change-Id: Ia8d27c0c9a082711d16bbf55602bf5712a47b6d6
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 15 ++++++++++++---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 15 ++++++++++++---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 11 +++++++++++
+ 4 files changed, 42 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index dcc54022579f..b458019e4cea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -655,6 +655,11 @@ struct nbio_hdp_flush_reg {
+ u32 ref_and_mask_sdma1;
+ };
+
++struct amdgpu_mmio_remap {
++ u32 reg_offset;
++ resource_size_t bus_addr;
++};
++
+ struct amdgpu_nbio_funcs {
+ const struct nbio_hdp_flush_reg *hdp_flush_reg;
+ u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
+@@ -682,6 +687,7 @@ struct amdgpu_nbio_funcs {
+ void (*ih_control)(struct amdgpu_device *adev);
+ void (*init_registers)(struct amdgpu_device *adev);
+ void (*detect_hw_virt)(struct amdgpu_device *adev);
++ void (*remap_hdp_registers)(struct amdgpu_device *adev);
+ };
+
+ struct amdgpu_df_funcs {
+@@ -804,6 +810,7 @@ struct amdgpu_device {
+ void __iomem *rmmio;
+ /* protects concurrent MM_INDEX/DATA based register access */
+ spinlock_t mmio_idx_lock;
++ struct amdgpu_mmio_remap rmmio_remap;
+ /* protects concurrent SMC based register access */
+ spinlock_t smc_idx_lock;
+ amdgpu_rreg_t smc_rreg;
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+index 150ca8e4fd7c..f73fb25ba242 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+@@ -29,6 +29,7 @@
+ #include "nbio/nbio_7_0_sh_mask.h"
+ #include "nbio/nbio_7_0_smn.h"
+ #include "vega10_enum.h"
++#include <uapi/linux/kfd_ioctl.h>
+
+ #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
+
+@@ -36,6 +37,14 @@
+ #define mmRCC_DEV0_EPF0_STRAP0_VG20 0x0011
+ #define mmRCC_DEV0_EPF0_STRAP0_VG20_BASE_IDX 2
+
++static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
++{
++ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
++ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
++}
++
+ static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
+ {
+ u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+@@ -64,10 +73,9 @@ static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring)
+ {
+ if (!ring || !ring->funcs->emit_wreg)
+- WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++ WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ else
+- amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+- NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
++ amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ }
+
+ static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
+@@ -299,4 +307,5 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
+ .ih_control = nbio_v7_0_ih_control,
+ .init_registers = nbio_v7_0_init_registers,
+ .detect_hw_virt = nbio_v7_0_detect_hw_virt,
++ .remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index c69d51598cfe..bfaaa327ae3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -27,9 +27,18 @@
+ #include "nbio/nbio_7_4_offset.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
+ #include "nbio/nbio_7_4_0_smn.h"
++#include <uapi/linux/kfd_ioctl.h>
+
+ #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
+
++static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
++{
++ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
++ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
++}
++
+ static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
+ {
+ u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+@@ -53,10 +62,9 @@ static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring)
+ {
+ if (!ring || !ring->funcs->emit_wreg)
+- WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++ WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ else
+- amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+- NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
++ amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ }
+
+ static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
+@@ -262,4 +270,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .ih_control = nbio_v7_4_ih_control,
+ .init_registers = nbio_v7_4_init_registers,
+ .detect_hw_virt = nbio_v7_4_detect_hw_virt,
++ .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 1788fb938aed..278ccd65a8d2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -44,6 +44,7 @@
+ #include "smuio/smuio_9_0_offset.h"
+ #include "smuio/smuio_9_0_sh_mask.h"
+ #include "nbio/nbio_7_0_default.h"
++#include "nbio/nbio_7_0_offset.h"
+ #include "nbio/nbio_7_0_sh_mask.h"
+ #include "nbio/nbio_7_0_smn.h"
+ #include "mp/mp_9_0_offset.h"
+@@ -64,6 +65,7 @@
+ #include "dce_virtual.h"
+ #include "mxgpu_ai.h"
+ #include "amdgpu_smu.h"
++#include <uapi/linux/kfd_ioctl.h>
+
+ #define mmMP0_MISC_CGTT_CTRL0 0x01b9
+ #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
+@@ -783,8 +785,11 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+
+ static int soc15_common_early_init(void *handle)
+ {
++#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
++ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
++ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ adev->smc_rreg = NULL;
+ adev->smc_wreg = NULL;
+ adev->pcie_rreg = &soc15_pcie_rreg;
+@@ -1013,6 +1018,12 @@ static int soc15_common_hw_init(void *handle)
+ soc15_program_aspm(adev);
+ /* setup nbio registers */
+ adev->nbio_funcs->init_registers(adev);
++ /* remap HDP registers to a hole in mmio space,
++ * for the purpose of expose those registers
++ * to process space
++ */
++ if (adev->nbio_funcs->remap_hdp_registers)
++ adev->nbio_funcs->remap_hdp_registers(adev);
+ /* enable the doorbell aperture */
+ soc15_enable_doorbell_aperture(adev, true);
+ /* HW doorbell routing policy: doorbell writing not
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-30 21:49:16 +0000