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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1450-drm-amd-powerplay-add-apply_clock_adjust_rules-for-S.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1450-drm-amd-powerplay-add-apply_clock_adjust_rules-for-S.patch180
1 files changed, 180 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1450-drm-amd-powerplay-add-apply_clock_adjust_rules-for-S.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1450-drm-amd-powerplay-add-apply_clock_adjust_rules-for-S.patch
new file mode 100644
index 00000000..4ea21c16
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/1450-drm-amd-powerplay-add-apply_clock_adjust_rules-for-S.patch
@@ -0,0 +1,180 @@
+From f51aa833d9945a9e9711581a9655c478179ce4fa Mon Sep 17 00:00:00 2001
+From: Chengming Gui <Jack.Gui@amd.com>
+Date: Fri, 18 Jan 2019 09:47:23 +0800
+Subject: [PATCH 1450/2940] drm/amd/powerplay: add apply_clock_adjust_rules for
+ SMU11.
+
+add apply_clock_adjust_rules to support sys interface for SMU11.
+
+Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 151 +++++++++++++++++++++
+ 1 file changed, 151 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 0b13c9319fa9..7f351c80f04e 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -1418,6 +1418,157 @@ static int vega20_display_config_changed(struct smu_context *smu)
+ return ret;
+ }
+
++static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
++{
++ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
++ struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
++ struct vega20_single_dpm_table *dpm_table;
++ bool vblank_too_short = false;
++ bool disable_mclk_switching;
++ uint32_t i, latency;
++
++ disable_mclk_switching = ((1 < smu->display_config->num_display) &&
++ !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
++ latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
++
++ /* gfxclk */
++ dpm_table = &(dpm_ctx->gfx_table);
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++
++ if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ }
++
++ /* memclk */
++ dpm_table = &(dpm_ctx->mem_table);
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++
++ if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ }
++
++ /* honour DAL's UCLK Hardmin */
++ if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
++ dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
++
++ /* Hardmin is dependent on displayconfig */
++ if (disable_mclk_switching) {
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
++ if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
++ if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
++ break;
++ }
++ }
++ }
++ }
++
++ if (smu->display_config->nb_pstate_switch_disable)
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++
++#if 0
++ /* vclk */
++ dpm_table = &(dpm_ctx->vclk_table);
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++
++ if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ }
++
++ /* dclk */
++ dpm_table = &(dpm_ctx->dclk_table);
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++
++ if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ }
++#endif
++
++ /* socclk */
++ dpm_table = &(dpm_ctx->soc_table);
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++
++ if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ }
++
++#if 0
++ /* eclk */
++ dpm_table = &(dpm_ctx->eclk_table);
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
++ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++
++ if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
++ }
++
++ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ }
++#endif
++ return 0;
++}
++
+ static const struct pptable_funcs vega20_ppt_funcs = {
+ .alloc_dpm_context = vega20_allocate_dpm_context,
+ .store_powerplay_table = vega20_store_powerplay_table,
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-30 23:35:44 +0000