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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4081-drm-amd-pp-Print-out-voltage-clock-range-in-sysfs.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4081-drm-amd-pp-Print-out-voltage-clock-range-in-sysfs.patch111
1 files changed, 111 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4081-drm-amd-pp-Print-out-voltage-clock-range-in-sysfs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4081-drm-amd-pp-Print-out-voltage-clock-range-in-sysfs.patch
new file mode 100644
index 00000000..1f7fef74
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4081-drm-amd-pp-Print-out-voltage-clock-range-in-sysfs.patch
@@ -0,0 +1,111 @@
+From 810c85d222049c3f2a1fae605d5c43803daee7f1 Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Thu, 19 Apr 2018 10:39:17 +0800
+Subject: [PATCH 4081/4131] drm/amd/pp: Print out voltage/clock range in sysfs
+
+when user cat pp_od_clk_voltage
+add display info about the sclk/mclk/vddc range that user can overdrive
+output as:
+OD_SCLK:
+0: 300MHz 900mV
+1: 400MHz 912mV
+2: 500MHz 925mV
+3: 600MHz 937mV
+4: 700MHz 950mV
+5: 800MHz 975mV
+6: 900MHz 987mV
+7: 1000MHz 1000mV
+OD_MCLK:
+0: 300MHz 900mV
+1: 1500MHz 912mV
+OD_RANGE:
+SCLK: 300MHz 1200MHz
+MCLK: 300MHz 1500MHz
+VDDC: 700mV 1200mV
+
+also
+1. remove unnecessary whitespace before a quoted newline
+2. change unit of frequency Mhz to MHz
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 1 +
+ drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 26 ++++++++++++++++++------
+ 3 files changed, 22 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 1167766..16fac65 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -437,6 +437,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
+ if (adev->powerplay.pp_funcs->print_clock_levels) {
+ size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
+ size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
++ size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
+ return size;
+ } else {
+ return snprintf(buf, PAGE_SIZE, "\n");
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 01969b1..06f08f3 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -94,6 +94,7 @@ enum pp_clock_type {
+ PP_PCIE,
+ OD_SCLK,
+ OD_MCLK,
++ OD_RANGE,
+ };
+
+ enum amd_pp_sensors {
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 19e0f51..5d53a63 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -4333,22 +4333,36 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
+ break;
+ case OD_SCLK:
+ if (hwmgr->od_enabled) {
+- size = sprintf(buf, "%s: \n", "OD_SCLK");
++ size = sprintf(buf, "%s:\n", "OD_SCLK");
+ for (i = 0; i < odn_sclk_table->num_of_pl; i++)
+- size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+- i, odn_sclk_table->entries[i].clock / 100,
++ size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
++ i, odn_sclk_table->entries[i].clock/100,
+ odn_sclk_table->entries[i].vddc);
+ }
+ break;
+ case OD_MCLK:
+ if (hwmgr->od_enabled) {
+- size = sprintf(buf, "%s: \n", "OD_MCLK");
++ size = sprintf(buf, "%s:\n", "OD_MCLK");
+ for (i = 0; i < odn_mclk_table->num_of_pl; i++)
+- size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+- i, odn_mclk_table->entries[i].clock / 100,
++ size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
++ i, odn_mclk_table->entries[i].clock/100,
+ odn_mclk_table->entries[i].vddc);
+ }
+ break;
++ case OD_RANGE:
++ if (hwmgr->od_enabled) {
++ size = sprintf(buf, "%s:\n", "OD_RANGE");
++ size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
++ data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
++ hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
++ size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
++ data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
++ hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
++ size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
++ data->odn_dpm_table.min_vddc,
++ data->odn_dpm_table.max_vddc);
++ }
++ break;
+ default:
+ break;
+ }
+--
+2.7.4
+