diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4079-drm-amd-pp-Refine-the-OD-state-checking-code-in-smu7.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4079-drm-amd-pp-Refine-the-OD-state-checking-code-in-smu7.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4079-drm-amd-pp-Refine-the-OD-state-checking-code-in-smu7.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4079-drm-amd-pp-Refine-the-OD-state-checking-code-in-smu7.patch new file mode 100644 index 00000000..b18c6620 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4079-drm-amd-pp-Refine-the-OD-state-checking-code-in-smu7.patch @@ -0,0 +1,50 @@ +From fdcbb4a30327944bcc4f35f2a335a9902837d5b5 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Wed, 18 Apr 2018 18:43:19 +0800 +Subject: [PATCH 4079/4131] drm/amd/pp: Refine the OD state checking code in + smu7 + +if vddc restore to default value, driver clear the +bit of DPMTABLE_OD_UPDATE_VDDC and need to repopulate sclk +and mclk table. + +1. Remove variable i checking code. +2. move clear DPMTABLE_OD_UPDATE_VDDC bit to the end of the + function to avoid sclk table will not be updated. + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 9130807..c9d523b 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -4681,10 +4681,6 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) + return; + } + } +- if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { +- data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; +- data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; +- } + + dep_table = table_info->vdd_dep_on_sclk; + odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); +@@ -4694,9 +4690,9 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) + return; + } + } +- if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { ++ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { + data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; +- data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; ++ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; + } + } + +-- +2.7.4 + |