diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4059-drm-amd-pp-Adding-set_watermarks_for_clocks_ranges-f.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4059-drm-amd-pp-Adding-set_watermarks_for_clocks_ranges-f.patch | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4059-drm-amd-pp-Adding-set_watermarks_for_clocks_ranges-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4059-drm-amd-pp-Adding-set_watermarks_for_clocks_ranges-f.patch new file mode 100644 index 00000000..1ba1b009 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4059-drm-amd-pp-Adding-set_watermarks_for_clocks_ranges-f.patch @@ -0,0 +1,66 @@ +From 7470f095633b673c88cd9b510579ea36a3f7ca49 Mon Sep 17 00:00:00 2001 +From: Mikita Lipski <mikita.lipski@amd.com> +Date: Tue, 10 Apr 2018 13:45:00 -0400 +Subject: [PATCH 4059/4131] drm/amd/pp: Adding set_watermarks_for_clocks_ranges + for SMU10 + +The function is never implemented for raven on linux. +It follows similair implementation as on windows. + +SMU still needs to notify SMC and copy WM table, which is added +here. But on other Asics such as Vega this step is not implemented. + +Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> +Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 13 +++++++++++++ + drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h | 1 + + 2 files changed, 14 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +index 1c19cd9..f8b6c94 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +@@ -1083,6 +1083,18 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, + return ret; + } + ++static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, ++ struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) ++{ ++ struct smu10_hwmgr *data = hwmgr->backend; ++ Watermarks_t *table = &(data->water_marks_table); ++ int result = 0; ++ ++ smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges); ++ smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false); ++ data->water_marks_exist = true; ++ return result; ++} + static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr) + { + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub); +@@ -1112,6 +1124,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = { + .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks, + .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency, + .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage, ++ .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges, + .get_max_high_clocks = smu10_get_max_high_clocks, + .read_sensor = smu10_read_sensor, + .set_active_display_count = smu10_set_active_display_count, +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h +index 175c3a5..f68b218 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h +@@ -290,6 +290,7 @@ struct smu10_hwmgr { + bool vcn_dpg_mode; + + bool gfx_off_controled_by_driver; ++ bool water_marks_exist; + Watermarks_t water_marks_table; + struct smu10_clock_voltage_information clock_vol_info; + DpmClocks_t clock_table; +-- +2.7.4 + |