diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4055-drm-amd-pp-Implement-force_clock_level-for-RV.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4055-drm-amd-pp-Implement-force_clock_level-for-RV.patch | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4055-drm-amd-pp-Implement-force_clock_level-for-RV.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4055-drm-amd-pp-Implement-force_clock_level-for-RV.patch new file mode 100644 index 00000000..34705f10 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/4055-drm-amd-pp-Implement-force_clock_level-for-RV.patch @@ -0,0 +1,73 @@ +From d8ee64e82e51fbafe771f4a860efb522a08cb178 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Tue, 8 May 2018 14:20:25 +0800 +Subject: [PATCH 4055/4131] drm/amd/pp: Implement force_clock_level for RV + +under manual dpm mode, user can set gfx/mem clock +through sysfs pp_dpm_sclk/mclk on Rv. + +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 45 +++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +index 6ab1a57..b1c3a7c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +@@ -757,6 +757,51 @@ static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr, + static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, uint32_t mask) + { ++ struct smu10_hwmgr *data = hwmgr->backend; ++ struct smu10_voltage_dependency_table *mclk_table = ++ data->clock_vol_info.vdd_dep_on_fclk; ++ uint32_t low, high; ++ ++ low = mask ? (ffs(mask) - 1) : 0; ++ high = mask ? (fls(mask) - 1) : 0; ++ ++ switch (type) { ++ case PP_SCLK: ++ if (low > 2 || high > 2) { ++ pr_info("Currently sclk only support 3 levels on RV\n"); ++ return -EINVAL; ++ } ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetHardMinGfxClk, ++ low == 2 ? data->gfx_max_freq_limit/100 : ++ low == 1 ? SMU10_UMD_PSTATE_GFXCLK : ++ data->gfx_min_freq_limit/100); ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetSoftMaxGfxClk, ++ high == 0 ? data->gfx_min_freq_limit/100 : ++ high == 1 ? SMU10_UMD_PSTATE_GFXCLK : ++ data->gfx_max_freq_limit/100); ++ break; ++ ++ case PP_MCLK: ++ if (low > mclk_table->count - 1 || high > mclk_table->count - 1) ++ return -EINVAL; ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetHardMinFclkByFreq, ++ mclk_table->entries[low].clk/100); ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetSoftMaxFclkByFreq, ++ mclk_table->entries[high].clk/100); ++ break; ++ ++ case PP_PCIE: ++ default: ++ break; ++ } + return 0; + } + +-- +2.7.4 + |