diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3996-drm-amd-display-Program-v_total_min-max-after-v_tota.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3996-drm-amd-display-Program-v_total_min-max-after-v_tota.patch | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3996-drm-amd-display-Program-v_total_min-max-after-v_tota.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3996-drm-amd-display-Program-v_total_min-max-after-v_tota.patch new file mode 100644 index 00000000..7a5f2a6a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3996-drm-amd-display-Program-v_total_min-max-after-v_tota.patch @@ -0,0 +1,109 @@ +From 440b27a5dee1c6a731576eb0d966fddd049b97fa Mon Sep 17 00:00:00 2001 +From: Anthony Koo <Anthony.Koo@amd.com> +Date: Thu, 15 Mar 2018 13:46:50 -0400 +Subject: [PATCH 3996/4131] drm/amd/display: Program v_total_min/max after + v_total_cntl + +Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +--- + .../drm/amd/display/dc/dce110/dce110_timing_generator.c | 16 ++++++++-------- + .../drm/amd/display/dc/dce120/dce120_timing_generator.c | 12 ++++++------ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 12 ++++++------ + 3 files changed, 20 insertions(+), 20 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +index be71539..1b2fe0d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +@@ -431,14 +431,6 @@ void dce110_timing_generator_set_drr( + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_SET_V_TOTAL_MIN_MASK); +- set_reg_field_value(v_total_min, +- 0, +- CRTC_V_TOTAL_MIN, +- CRTC_V_TOTAL_MIN); +- set_reg_field_value(v_total_max, +- 0, +- CRTC_V_TOTAL_MAX, +- CRTC_V_TOTAL_MAX); + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, +@@ -447,6 +439,14 @@ void dce110_timing_generator_set_drr( + 0, + CRTC_V_TOTAL_CONTROL, + CRTC_V_TOTAL_MAX_SEL); ++ set_reg_field_value(v_total_min, ++ 0, ++ CRTC_V_TOTAL_MIN, ++ CRTC_V_TOTAL_MIN); ++ set_reg_field_value(v_total_max, ++ 0, ++ CRTC_V_TOTAL_MAX, ++ CRTC_V_TOTAL_MAX); + set_reg_field_value(v_total_cntl, + 0, + CRTC_V_TOTAL_CONTROL, +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +index 7bee781..2ea490f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +@@ -570,12 +570,6 @@ void dce120_timing_generator_set_drr( + 0x180); + + } else { +- CRTC_REG_UPDATE( +- CRTC0_CRTC_V_TOTAL_MIN, +- CRTC_V_TOTAL_MIN, 0); +- CRTC_REG_UPDATE( +- CRTC0_CRTC_V_TOTAL_MAX, +- CRTC_V_TOTAL_MAX, 0); + CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5, + FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0, + FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0, +@@ -583,6 +577,12 @@ void dce120_timing_generator_set_drr( + FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0, + FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0); + CRTC_REG_UPDATE( ++ CRTC0_CRTC_V_TOTAL_MIN, ++ CRTC_V_TOTAL_MIN, 0); ++ CRTC_REG_UPDATE( ++ CRTC0_CRTC_V_TOTAL_MAX, ++ CRTC_V_TOTAL_MAX, 0); ++ CRTC_REG_UPDATE( + CRTC0_CRTC_STATIC_SCREEN_CONTROL, + CRTC_STATIC_SCREEN_EVENT_MASK, + 0); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +index f56eac0..dc92130 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +@@ -855,17 +855,17 @@ void optc1_set_drr( + OTG_SET_V_TOTAL_MIN_MASK_EN, 0, + OTG_SET_V_TOTAL_MIN_MASK, 0); + } else { +- REG_SET(OTG_V_TOTAL_MIN, 0, +- OTG_V_TOTAL_MIN, 0); +- +- REG_SET(OTG_V_TOTAL_MAX, 0, +- OTG_V_TOTAL_MAX, 0); +- + REG_UPDATE_4(OTG_V_TOTAL_CONTROL, + OTG_SET_V_TOTAL_MIN_MASK, 0, + OTG_V_TOTAL_MIN_SEL, 0, + OTG_V_TOTAL_MAX_SEL, 0, + OTG_FORCE_LOCK_ON_EVENT, 0); ++ ++ REG_SET(OTG_V_TOTAL_MIN, 0, ++ OTG_V_TOTAL_MIN, 0); ++ ++ REG_SET(OTG_V_TOTAL_MAX, 0, ++ OTG_V_TOTAL_MAX, 0); + } + } + +-- +2.7.4 + |