diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3966-drm-amdgpu-Delete-some-cgs-functions.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3966-drm-amdgpu-Delete-some-cgs-functions.patch | 475 |
1 files changed, 475 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3966-drm-amdgpu-Delete-some-cgs-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3966-drm-amdgpu-Delete-some-cgs-functions.patch new file mode 100644 index 00000000..ff0f1b4b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3966-drm-amdgpu-Delete-some-cgs-functions.patch @@ -0,0 +1,475 @@ +From bae5c21f32720f062faf74b3b3f1a4fb5f85d13a Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Thu, 22 Mar 2018 19:32:45 +0800 +Subject: [PATCH 3966/4131] drm/amdgpu: Delete some cgs functions + +Drop cgs wrappers that are no longer used. +1. cgs_rel_firmwar +2. cgs_is_virtualization_enabled +3. cgs_notify_dpm_enabled +4. cgs_atom_get_data_table +5. cgs_atom_get_cmd_table_revs +6. cgs_atom_exec_cmd_table +7. cgs_get_active_displays_info + +Change-Id: Ib9075a7643712da9f8b6123f9c5b6176229ace82 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 197 ------------------------------- + drivers/gpu/drm/amd/include/cgs_common.h | 139 ---------------------- + 2 files changed, 336 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +index 71a57b2..dc28fa6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +@@ -23,7 +23,6 @@ + */ + #include <linux/list.h> + #include <linux/slab.h> +-#include <linux/pci.h> + #include <drm/drmP.h> + #include <linux/firmware.h> + #include <drm/amdgpu_drm.h> +@@ -109,78 +108,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, + WARN(1, "Invalid indirect register space"); + } + +-static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device, +- enum cgs_resource_type resource_type, +- uint64_t size, +- uint64_t offset, +- uint64_t *resource_base) +-{ +- CGS_FUNC_ADEV; +- +- if (resource_base == NULL) +- return -EINVAL; +- +- switch (resource_type) { +- case CGS_RESOURCE_TYPE_MMIO: +- if (adev->rmmio_size == 0) +- return -ENOENT; +- if ((offset + size) > adev->rmmio_size) +- return -EINVAL; +- *resource_base = adev->rmmio_base; +- return 0; +- case CGS_RESOURCE_TYPE_DOORBELL: +- if (adev->doorbell.size == 0) +- return -ENOENT; +- if ((offset + size) > adev->doorbell.size) +- return -EINVAL; +- *resource_base = adev->doorbell.base; +- return 0; +- case CGS_RESOURCE_TYPE_FB: +- case CGS_RESOURCE_TYPE_IO: +- case CGS_RESOURCE_TYPE_ROM: +- default: +- return -EINVAL; +- } +-} +- +-static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device, +- unsigned table, uint16_t *size, +- uint8_t *frev, uint8_t *crev) +-{ +- CGS_FUNC_ADEV; +- uint16_t data_start; +- +- if (amdgpu_atom_parse_data_header( +- adev->mode_info.atom_context, table, size, +- frev, crev, &data_start)) +- return (uint8_t*)adev->mode_info.atom_context->bios + +- data_start; +- +- return NULL; +-} +- +-static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table, +- uint8_t *frev, uint8_t *crev) +-{ +- CGS_FUNC_ADEV; +- +- if (amdgpu_atom_parse_cmd_header( +- adev->mode_info.atom_context, table, +- frev, crev)) +- return 0; +- +- return -EINVAL; +-} +- +-static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table, +- void *args) +-{ +- CGS_FUNC_ADEV; +- +- return amdgpu_atom_execute_table( +- adev->mode_info.atom_context, table, args); +-} +- + static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state) +@@ -223,7 +150,6 @@ static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device, + return r; + } + +- + static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) + { + CGS_FUNC_ADEV; +@@ -271,18 +197,6 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) + return result; + } + +-static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type) +-{ +- CGS_FUNC_ADEV; +- if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) { +- release_firmware(adev->pm.fw); +- adev->pm.fw = NULL; +- return 0; +- } +- /* cannot release other firmware because they are not created by cgs */ +- return -EINVAL; +-} +- + static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, + enum cgs_ucode_id type) + { +@@ -326,34 +240,6 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, + return fw_version; + } + +-static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device, +- bool en) +-{ +- CGS_FUNC_ADEV; +- +- if (adev->gfx.rlc.funcs->enter_safe_mode == NULL || +- adev->gfx.rlc.funcs->exit_safe_mode == NULL) +- return 0; +- +- if (en) +- adev->gfx.rlc.funcs->enter_safe_mode(adev); +- else +- adev->gfx.rlc.funcs->exit_safe_mode(adev); +- +- return 0; +-} +- +-static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device, +- bool lock) +-{ +- CGS_FUNC_ADEV; +- +- if (lock) +- mutex_lock(&adev->grbm_idx_mutex); +- else +- mutex_unlock(&adev->grbm_idx_mutex); +-} +- + static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, + enum cgs_ucode_id type, + struct cgs_firmware_info *info) +@@ -598,97 +484,14 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, + return 0; + } + +-static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device) +-{ +- CGS_FUNC_ADEV; +- return amdgpu_sriov_vf(adev); +-} +- +-static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, +- struct cgs_display_info *info) +-{ +- CGS_FUNC_ADEV; +- struct cgs_mode_info *mode_info; +- +- if (info == NULL) +- return -EINVAL; +- +- mode_info = info->mode_info; +- if (mode_info) +- /* if the displays are off, vblank time is max */ +- mode_info->vblank_time_us = 0xffffffff; +- +- if (!amdgpu_device_has_dc_support(adev)) { +- struct amdgpu_crtc *amdgpu_crtc; +- struct drm_device *ddev = adev->ddev; +- struct drm_crtc *crtc; +- uint32_t line_time_us, vblank_lines; +- +- if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { +- list_for_each_entry(crtc, +- &ddev->mode_config.crtc_list, head) { +- amdgpu_crtc = to_amdgpu_crtc(crtc); +- if (crtc->enabled) { +- info->active_display_mask |= (1 << amdgpu_crtc->crtc_id); +- info->display_count++; +- } +- if (mode_info != NULL && +- crtc->enabled && amdgpu_crtc->enabled && +- amdgpu_crtc->hw_mode.clock) { +- line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / +- amdgpu_crtc->hw_mode.clock; +- vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - +- amdgpu_crtc->hw_mode.crtc_vdisplay + +- (amdgpu_crtc->v_border * 2); +- mode_info->vblank_time_us = vblank_lines * line_time_us; +- mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); +- /* we have issues with mclk switching with refresh rates +- * over 120 hz on the non-DC code. +- */ +- if (mode_info->refresh_rate > 120) +- mode_info->vblank_time_us = 0; +- mode_info = NULL; +- } +- } +- } +- } else { +- info->display_count = adev->pm.pm_display_cfg.num_display; +- if (mode_info != NULL) { +- mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time; +- mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh; +- } +- } +- return 0; +-} +- +- +-static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled) +-{ +- CGS_FUNC_ADEV; +- +- adev->pm.dpm_enabled = enabled; +- +- return 0; +-} +- + static const struct cgs_ops amdgpu_cgs_ops = { + .read_register = amdgpu_cgs_read_register, + .write_register = amdgpu_cgs_write_register, + .read_ind_register = amdgpu_cgs_read_ind_register, + .write_ind_register = amdgpu_cgs_write_ind_register, +- .get_pci_resource = amdgpu_cgs_get_pci_resource, +- .atom_get_data_table = amdgpu_cgs_atom_get_data_table, +- .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs, +- .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table, + .get_firmware_info = amdgpu_cgs_get_firmware_info, +- .rel_firmware = amdgpu_cgs_rel_firmware, + .set_powergating_state = amdgpu_cgs_set_powergating_state, + .set_clockgating_state = amdgpu_cgs_set_clockgating_state, +- .get_active_displays_info = amdgpu_cgs_get_active_displays_info, +- .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled, +- .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled, +- .enter_safe_mode = amdgpu_cgs_enter_safe_mode, +- .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx, + }; + + struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) +diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h +index f2814ae..cab34a4 100644 +--- a/drivers/gpu/drm/amd/include/cgs_common.h ++++ b/drivers/gpu/drm/amd/include/cgs_common.h +@@ -76,17 +76,6 @@ enum cgs_ucode_id { + CGS_UCODE_ID_MAXIMUM, + }; + +-/* +- * enum cgs_resource_type - GPU resource type +- */ +-enum cgs_resource_type { +- CGS_RESOURCE_TYPE_MMIO = 0, +- CGS_RESOURCE_TYPE_FB, +- CGS_RESOURCE_TYPE_IO, +- CGS_RESOURCE_TYPE_DOORBELL, +- CGS_RESOURCE_TYPE_ROM, +-}; +- + /** + * struct cgs_firmware_info - Firmware information + */ +@@ -104,17 +93,6 @@ struct cgs_firmware_info { + bool is_kicker; + }; + +-struct cgs_mode_info { +- uint32_t refresh_rate; +- uint32_t vblank_time_us; +-}; +- +-struct cgs_display_info { +- uint32_t display_count; +- uint32_t active_display_mask; +- struct cgs_mode_info *mode_info; +-}; +- + typedef unsigned long cgs_handle_t; + + /** +@@ -170,73 +148,10 @@ typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs + #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ + cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) + +-/** +- * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) +- * @cgs_device: opaque device handle +- * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) +- * @size: size of the region +- * @offset: offset from the start of the region +- * @resource_base: base address (not including offset) returned +- * +- * Return: 0 on success, -errno otherwise +- */ +-typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, +- enum cgs_resource_type resource_type, +- uint64_t size, +- uint64_t offset, +- uint64_t *resource_base); +- +-/** +- * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table +- * @cgs_device: opaque device handle +- * @table: data table index +- * @size: size of the table (output, may be NULL) +- * @frev: table format revision (output, may be NULL) +- * @crev: table content revision (output, may be NULL) +- * +- * Return: Pointer to start of the table, or NULL on failure +- */ +-typedef const void *(*cgs_atom_get_data_table_t)( +- struct cgs_device *cgs_device, unsigned table, +- uint16_t *size, uint8_t *frev, uint8_t *crev); +- +-/** +- * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions +- * @cgs_device: opaque device handle +- * @table: data table index +- * @frev: table format revision (output, may be NULL) +- * @crev: table content revision (output, may be NULL) +- * +- * Return: 0 on success, -errno otherwise +- */ +-typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, +- uint8_t *frev, uint8_t *crev); +- +-/** +- * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table +- * @cgs_device: opaque device handle +- * @table: command table index +- * @args: arguments +- * +- * Return: 0 on success, -errno otherwise +- */ +-typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, +- unsigned table, void *args); +- +-/** +- * cgs_get_firmware_info - Get the firmware information from core driver +- * @cgs_device: opaque device handle +- * @type: the firmware type +- * @info: returend firmware information +- * +- * Return: 0 on success, -errno otherwise +- */ + typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, + enum cgs_ucode_id type, + struct cgs_firmware_info *info); + +-typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device, +- enum cgs_ucode_id type); + + typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, + enum amd_ip_block_type block_type, +@@ -246,43 +161,17 @@ typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state); + +-typedef int(*cgs_get_active_displays_info)( +- struct cgs_device *cgs_device, +- struct cgs_display_info *info); +- +-typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); +- +-typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); +- +-typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en); +- +-typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock); +- + struct cgs_ops { + /* MMIO access */ + cgs_read_register_t read_register; + cgs_write_register_t write_register; + cgs_read_ind_register_t read_ind_register; + cgs_write_ind_register_t write_ind_register; +- /* PCI resources */ +- cgs_get_pci_resource_t get_pci_resource; +- /* ATOM BIOS */ +- cgs_atom_get_data_table_t atom_get_data_table; +- cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; +- cgs_atom_exec_cmd_table_t atom_exec_cmd_table; + /* Firmware Info */ + cgs_get_firmware_info get_firmware_info; +- cgs_rel_firmware rel_firmware; + /* cg pg interface*/ + cgs_set_powergating_state set_powergating_state; + cgs_set_clockgating_state set_clockgating_state; +- /* display manager */ +- cgs_get_active_displays_info get_active_displays_info; +- /* notify dpm enabled */ +- cgs_notify_dpm_enabled notify_dpm_enabled; +- cgs_is_virtualization_enabled_t is_virtualization_enabled; +- cgs_enter_safe_mode enter_safe_mode; +- cgs_lock_grbm_idx lock_grbm_idx; + }; + + struct cgs_os_ops; /* To be define in OS-specific CGS header */ +@@ -309,40 +198,12 @@ struct cgs_device + #define cgs_write_ind_register(dev,space,index,value) \ + CGS_CALL(write_ind_register,dev,space,index,value) + +-#define cgs_atom_get_data_table(dev,table,size,frev,crev) \ +- CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) +-#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ +- CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) +-#define cgs_atom_exec_cmd_table(dev,table,args) \ +- CGS_CALL(atom_exec_cmd_table,dev,table,args) +- + #define cgs_get_firmware_info(dev, type, info) \ + CGS_CALL(get_firmware_info, dev, type, info) +-#define cgs_rel_firmware(dev, type) \ +- CGS_CALL(rel_firmware, dev, type) + #define cgs_set_powergating_state(dev, block_type, state) \ + CGS_CALL(set_powergating_state, dev, block_type, state) + #define cgs_set_clockgating_state(dev, block_type, state) \ + CGS_CALL(set_clockgating_state, dev, block_type, state) +-#define cgs_notify_dpm_enabled(dev, enabled) \ +- CGS_CALL(notify_dpm_enabled, dev, enabled) +- +-#define cgs_get_active_displays_info(dev, info) \ +- CGS_CALL(get_active_displays_info, dev, info) +- +-#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ +- resource_base) \ +- CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ +- resource_base) +- +-#define cgs_is_virtualization_enabled(cgs_device) \ +- CGS_CALL(is_virtualization_enabled, cgs_device) +- +-#define cgs_enter_safe_mode(cgs_device, en) \ +- CGS_CALL(enter_safe_mode, cgs_device, en) +- +-#define cgs_lock_grbm_idx(cgs_device, lock) \ +- CGS_CALL(lock_grbm_idx, cgs_device, lock) + + + #endif /* _CGS_COMMON_H */ +-- +2.7.4 + |