diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3941-drm-amd-display-Correct-print-types-in-DC_LOGS.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3941-drm-amd-display-Correct-print-types-in-DC_LOGS.patch | 239 |
1 files changed, 239 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3941-drm-amd-display-Correct-print-types-in-DC_LOGS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3941-drm-amd-display-Correct-print-types-in-DC_LOGS.patch new file mode 100644 index 00000000..63da5564 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3941-drm-amd-display-Correct-print-types-in-DC_LOGS.patch @@ -0,0 +1,239 @@ +From f0f8df3a0f38418d07307b739b9f0d7b772fdbc2 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Wed, 14 Mar 2018 11:19:15 -0400 +Subject: [PATCH 3941/4131] drm/amd/display: Correct print types in DC_LOGS + +Correct the types used for printing in logs. This is needed for adding +dynamic printing (LINUX), otherwise we get warnings. + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 74 +++++++++++----------- + drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 14 ++-- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +-- + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +- + .../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 2 +- + 5 files changed, 52 insertions(+), 50 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 4bb43a3..a102c19 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -1459,39 +1459,39 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) + void dcn_bw_sync_calcs_and_dml(struct dc *dc) + { + kernel_fpu_begin(); +- DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %d ns\n" +- "sr_enter_plus_exit_time: %d ns\n" +- "urgent_latency: %d ns\n" +- "write_back_latency: %d ns\n" +- "percent_of_ideal_drambw_received_after_urg_latency: %d %\n" ++ DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n" ++ "sr_enter_plus_exit_time: %f ns\n" ++ "urgent_latency: %f ns\n" ++ "write_back_latency: %f ns\n" ++ "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n" + "max_request_size: %d bytes\n" +- "dcfclkv_max0p9: %d kHz\n" +- "dcfclkv_nom0p8: %d kHz\n" +- "dcfclkv_mid0p72: %d kHz\n" +- "dcfclkv_min0p65: %d kHz\n" +- "max_dispclk_vmax0p9: %d kHz\n" +- "max_dispclk_vnom0p8: %d kHz\n" +- "max_dispclk_vmid0p72: %d kHz\n" +- "max_dispclk_vmin0p65: %d kHz\n" +- "max_dppclk_vmax0p9: %d kHz\n" +- "max_dppclk_vnom0p8: %d kHz\n" +- "max_dppclk_vmid0p72: %d kHz\n" +- "max_dppclk_vmin0p65: %d kHz\n" +- "socclk: %d kHz\n" +- "fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n" +- "fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n" +- "fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n" +- "fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n" +- "phyclkv_max0p9: %d kHz\n" +- "phyclkv_nom0p8: %d kHz\n" +- "phyclkv_mid0p72: %d kHz\n" +- "phyclkv_min0p65: %d kHz\n" +- "downspreading: %d %\n" ++ "dcfclkv_max0p9: %f kHz\n" ++ "dcfclkv_nom0p8: %f kHz\n" ++ "dcfclkv_mid0p72: %f kHz\n" ++ "dcfclkv_min0p65: %f kHz\n" ++ "max_dispclk_vmax0p9: %f kHz\n" ++ "max_dispclk_vnom0p8: %f kHz\n" ++ "max_dispclk_vmid0p72: %f kHz\n" ++ "max_dispclk_vmin0p65: %f kHz\n" ++ "max_dppclk_vmax0p9: %f kHz\n" ++ "max_dppclk_vnom0p8: %f kHz\n" ++ "max_dppclk_vmid0p72: %f kHz\n" ++ "max_dppclk_vmin0p65: %f kHz\n" ++ "socclk: %f kHz\n" ++ "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n" ++ "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n" ++ "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n" ++ "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n" ++ "phyclkv_max0p9: %f kHz\n" ++ "phyclkv_nom0p8: %f kHz\n" ++ "phyclkv_mid0p72: %f kHz\n" ++ "phyclkv_min0p65: %f kHz\n" ++ "downspreading: %f %%\n" + "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n" + "urgent_out_of_order_return_per_channel: %d Bytes\n" + "number_of_channels: %d\n" + "vmm_page_size: %d Bytes\n" +- "dram_clock_change_latency: %d ns\n" ++ "dram_clock_change_latency: %f ns\n" + "return_bus_width: %d Bytes\n", + dc->dcn_soc->sr_exit_time * 1000, + dc->dcn_soc->sr_enter_plus_exit_time * 1000, +@@ -1527,11 +1527,11 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) + dc->dcn_soc->vmm_page_size, + dc->dcn_soc->dram_clock_change_latency * 1000, + dc->dcn_soc->return_bus_width); +- DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %d\n" +- "det_buffer_size_in_kbyte: %d\n" +- "dpp_output_buffer_pixels: %d\n" +- "opp_output_buffer_lines: %d\n" +- "pixel_chunk_size_in_kbyte: %d\n" ++ DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n" ++ "det_buffer_size_in_kbyte: %f\n" ++ "dpp_output_buffer_pixels: %f\n" ++ "opp_output_buffer_lines: %f\n" ++ "pixel_chunk_size_in_kbyte: %f\n" + "pte_enable: %d\n" + "pte_chunk_size: %d kbytes\n" + "meta_chunk_size: %d kbytes\n" +@@ -1550,13 +1550,13 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) + "max_pscl_tolb_throughput: %d pixels/dppclk\n" + "max_lb_tovscl_throughput: %d pixels/dppclk\n" + "max_vscl_tohscl_throughput: %d pixels/dppclk\n" +- "max_hscl_ratio: %d\n" +- "max_vscl_ratio: %d\n" ++ "max_hscl_ratio: %f\n" ++ "max_vscl_ratio: %f\n" + "max_hscl_taps: %d\n" + "max_vscl_taps: %d\n" + "pte_buffer_size_in_requests: %d\n" +- "dispclk_ramping_margin: %d %\n" +- "under_scan_factor: %d %\n" ++ "dispclk_ramping_margin: %f %%\n" ++ "under_scan_factor: %f %%\n" + "max_inter_dcn_tile_repeaters: %d\n" + "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n" + "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n" +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +index 5a552cb3..71cc60f 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +@@ -72,8 +72,8 @@ void pre_surface_trace( + "plane_state->visible = %d;\n" + "plane_state->flip_immediate = %d;\n" + "plane_state->address.type = %d;\n" +- "plane_state->address.grph.addr.quad_part = 0x%X;\n" +- "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n" ++ "plane_state->address.grph.addr.quad_part = 0x%llX;\n" ++ "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n" + "plane_state->scaling_quality.h_taps = %d;\n" + "plane_state->scaling_quality.v_taps = %d;\n" + "plane_state->scaling_quality.h_taps_c = %d;\n" +@@ -192,8 +192,8 @@ void update_surface_trace( + SURFACE_TRACE("Update %d\n", i); + if (update->flip_addr) { + SURFACE_TRACE("flip_addr->address.type = %d;\n" +- "flip_addr->address.grph.addr.quad_part = 0x%X;\n" +- "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n" ++ "flip_addr->address.grph.addr.quad_part = 0x%llX;\n" ++ "flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n" + "flip_addr->flip_immediate = %d;\n", + update->flip_addr->address.type, + update->flip_addr->address.grph.addr.quad_part, +@@ -211,7 +211,8 @@ void update_surface_trace( + "plane_info->plane_size.grph.surface_size.width = %d;\n" + "plane_info->plane_size.grph.surface_size.x = %d;\n" + "plane_info->plane_size.grph.surface_size.y = %d;\n" +- "plane_info->rotation = %d;\n", ++ "plane_info->rotation = %d;\n" ++ "plane_info->stereo_format = %d;\n", + update->plane_info->color_space, + update->plane_info->input_tf, + update->plane_info->format, +@@ -371,6 +372,7 @@ void context_clock_trace( + context->bw.dcn.calc_clk.dppclk_khz, + context->bw.dcn.calc_clk.dcfclk_khz, + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, +- context->bw.dcn.calc_clk.fclk_khz); ++ context->bw.dcn.calc_clk.fclk_khz, ++ context->bw.dcn.calc_clk.socclk_khz); + #endif + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index 68c7196..65f2ce9b 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -2178,11 +2178,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) + link->mst_stream_alloc_table.stream_count); + + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { +- DC_LOG_MST("stream_enc[%d]: 0x%x " ++ DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].vcp_id: %d " + "stream[%d].slot_count: %d\n", + i, +- link->mst_stream_alloc_table.stream_allocations[i].stream_enc, ++ (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, + i, + link->mst_stream_alloc_table.stream_allocations[i].vcp_id, + i, +@@ -2268,11 +2268,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) + link->mst_stream_alloc_table.stream_count); + + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { +- DC_LOG_MST("stream_enc[%d]: 0x%x " ++ DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].vcp_id: %d " + "stream[%d].slot_count: %d\n", + i, +- link->mst_stream_alloc_table.stream_allocations[i].stream_enc, ++ (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, + i, + link->mst_stream_alloc_table.stream_allocations[i].vcp_id, + i, +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 075ab29..c621230 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -2777,13 +2777,13 @@ static void dce110_program_front_end_for_pipe( + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); + + DC_LOG_SURFACE( +- "Pipe:%d 0x%x: addr hi:0x%x, " ++ "Pipe:%d %p: addr hi:0x%x, " + "addr low:0x%x, " + "src: %d, %d, %d," + " %d; dst: %d, %d, %d, %d;" + "clip: %d, %d, %d, %d\n", + pipe_ctx->pipe_idx, +- pipe_ctx->plane_state, ++ (void *) pipe_ctx->plane_state, + pipe_ctx->plane_state->address.grph.addr.high_part, + pipe_ctx->plane_state->address.grph.addr.low_part, + pipe_ctx->plane_state->src_rect.x, +diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +index abd0095..b7256f5 100644 +--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c ++++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +@@ -527,7 +527,7 @@ static void construct( + REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); + + if (xtal_ref_div == 0) { +- DC_LOG_WARNING("Invalid base timer divider\n", ++ DC_LOG_WARNING("Invalid base timer divider [%s]\n", + __func__); + xtal_ref_div = 2; + } +-- +2.7.4 + |