diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3932-drm-amd-display-Implementing-new-bandwidth-registers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3932-drm-amd-display-Implementing-new-bandwidth-registers.patch | 234 |
1 files changed, 234 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3932-drm-amd-display-Implementing-new-bandwidth-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3932-drm-amd-display-Implementing-new-bandwidth-registers.patch new file mode 100644 index 00000000..ba03f287 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3932-drm-amd-display-Implementing-new-bandwidth-registers.patch @@ -0,0 +1,234 @@ +From 1bc31aa558d3388c6983032fc1a09ac7304e57ff Mon Sep 17 00:00:00 2001 +From: Mikita Lipski <mikita.lipski@amd.com> +Date: Wed, 21 Feb 2018 16:57:10 -0500 +Subject: [PATCH 3932/4131] drm/amd/display: Implementing new bandwidth + registers for DCE120 + +Registers are added and defined. +Programmed to default values. +Stutter level watermark register is being set to calculated value. +Urgent level registers are programmed to the same as urgency. +The programming of the registers is not expected to have any +functional difference in performance. + +Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 58 +++++++++++++++------- + drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 9 ++++ + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 3 ++ + .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 1 + + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 1 + + 5 files changed, 55 insertions(+), 17 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +index 0790f25..04fc86bb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +@@ -174,6 +174,25 @@ static void program_urgency_watermark( + URGENCY_HIGH_WATERMARK, urgency_high_wm); + } + ++static void dce120_program_urgency_watermark( ++ struct dce_mem_input *dce_mi, ++ uint32_t wm_select, ++ uint32_t urgency_low_wm, ++ uint32_t urgency_high_wm) ++{ ++ REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, ++ URGENCY_WATERMARK_MASK, wm_select); ++ ++ REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, ++ URGENCY_LOW_WATERMARK, urgency_low_wm, ++ URGENCY_HIGH_WATERMARK, urgency_high_wm); ++ ++ REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, ++ URGENT_LEVEL_LOW_WATERMARK, urgency_low_wm, ++ URGENT_LEVEL_HIGH_WATERMARK, urgency_high_wm); ++ ++} ++ + static void program_nbp_watermark( + struct dce_mem_input *dce_mi, + uint32_t wm_select, +@@ -209,23 +228,27 @@ static void program_nbp_watermark( + static void program_stutter_watermark( + struct dce_mem_input *dce_mi, + uint32_t wm_select, +- uint32_t stutter_mark) ++ uint32_t stutter_mark, ++ uint32_t stutter_entry) + { + REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, + STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select); + + if (REG(DPG_PIPE_STUTTER_CONTROL2)) +- REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, +- STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); ++ REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2, ++ STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark, ++ STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry); + else +- REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, +- STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); ++ REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, ++ STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark, ++ STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry); + } + + static void dce_mi_program_display_marks( + struct mem_input *mi, + struct dce_watermarks nbp, +- struct dce_watermarks stutter, ++ struct dce_watermarks stutter_exit, ++ struct dce_watermarks stutter_enter, + struct dce_watermarks urgent, + uint32_t total_dest_line_time_ns) + { +@@ -243,26 +266,27 @@ static void dce_mi_program_display_marks( + program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */ + program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */ + +- program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */ +- program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */ ++ program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark, stutter_enter.a_mark); /* set a */ ++ program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark, stutter_enter.d_mark); /* set d */ + } + + static void dce120_mi_program_display_marks(struct mem_input *mi, + struct dce_watermarks nbp, +- struct dce_watermarks stutter, ++ struct dce_watermarks stutter_exit, ++ struct dce_watermarks stutter_entry, + struct dce_watermarks urgent, + uint32_t total_dest_line_time_ns) + { + struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi); + uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1; + +- program_urgency_watermark(dce_mi, 0, /* set a */ ++ dce120_program_urgency_watermark(dce_mi, 0, /* set a */ + urgent.a_mark, total_dest_line_time_ns); +- program_urgency_watermark(dce_mi, 1, /* set b */ ++ dce120_program_urgency_watermark(dce_mi, 1, /* set b */ + urgent.b_mark, total_dest_line_time_ns); +- program_urgency_watermark(dce_mi, 2, /* set c */ ++ dce120_program_urgency_watermark(dce_mi, 2, /* set c */ + urgent.c_mark, total_dest_line_time_ns); +- program_urgency_watermark(dce_mi, 3, /* set d */ ++ dce120_program_urgency_watermark(dce_mi, 3, /* set d */ + urgent.d_mark, total_dest_line_time_ns); + + REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL, +@@ -273,10 +297,10 @@ static void dce120_mi_program_display_marks(struct mem_input *mi, + program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */ + program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */ + +- program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */ +- program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */ +- program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */ +- program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */ ++ program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark, stutter_entry.a_mark); /* set a */ ++ program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark, stutter_entry.b_mark); /* set b */ ++ program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark, stutter_entry.c_mark); /* set c */ ++ program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark, stutter_entry.d_mark); /* set d */ + } + + static void program_tiling( +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +index 05d39c0..e877e73 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +@@ -106,6 +106,7 @@ struct dce_mem_input_registers { + uint32_t DPG_PIPE_ARBITRATION_CONTROL1; + uint32_t DPG_WATERMARK_MASK_CONTROL; + uint32_t DPG_PIPE_URGENCY_CONTROL; ++ uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL; + uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL; + uint32_t DPG_PIPE_LOW_POWER_CONTROL; + uint32_t DPG_PIPE_STUTTER_CONTROL; +@@ -213,6 +214,11 @@ struct dce_mem_input_registers { + + #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ ++ SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\ ++ SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\ ++ SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\ ++ SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ ++ SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ + SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ +@@ -286,6 +292,8 @@ struct dce_mem_input_registers { + type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \ + type URGENCY_LOW_WATERMARK; \ + type URGENCY_HIGH_WATERMARK; \ ++ type URGENT_LEVEL_LOW_WATERMARK;\ ++ type URGENT_LEVEL_HIGH_WATERMARK;\ + type NB_PSTATE_CHANGE_ENABLE; \ + type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \ + type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \ +@@ -297,6 +305,7 @@ struct dce_mem_input_registers { + type STUTTER_ENABLE; \ + type STUTTER_IGNORE_FBC; \ + type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \ ++ type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \ + type DMIF_BUFFERS_ALLOCATED; \ + type DMIF_BUFFERS_ALLOCATION_COMPLETED; \ + type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\ +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 30dd62f..daa4673 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1539,6 +1539,7 @@ static void dce110_set_displaymarks( + pipe_ctx->plane_res.mi, + context->bw.dce.nbp_state_change_wm_ns[num_pipes], + context->bw.dce.stutter_exit_wm_ns[num_pipes], ++ context->bw.dce.stutter_entry_wm_ns[num_pipes], + context->bw.dce.urgent_wm_ns[num_pipes], + total_dest_line_time_ns); + if (i == underlay_idx) { +@@ -1564,6 +1565,7 @@ static void set_safe_displaymarks( + MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; + struct dce_watermarks nbp_marks = { + SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; ++ struct dce_watermarks min_marks = { 0, 0, 0, 0}; + + for (i = 0; i < MAX_PIPES; i++) { + if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) +@@ -1573,6 +1575,7 @@ static void set_safe_displaymarks( + res_ctx->pipe_ctx[i].plane_res.mi, + nbp_marks, + max_marks, ++ min_marks, + max_marks, + MAX_WATERMARK); + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +index 7bab8c6..0564c8e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +@@ -923,6 +923,7 @@ void dce_mem_input_v_program_display_marks( + struct mem_input *mem_input, + struct dce_watermarks nbp, + struct dce_watermarks stutter, ++ struct dce_watermarks stutter_enter, + struct dce_watermarks urgent, + uint32_t total_dest_line_time_ns) + { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +index 3e1e7e6..47f1dc5 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +@@ -104,6 +104,7 @@ struct mem_input_funcs { + struct mem_input *mem_input, + struct dce_watermarks nbp, + struct dce_watermarks stutter, ++ struct dce_watermarks stutter_enter, + struct dce_watermarks urgent, + uint32_t total_dest_line_time_ns); + +-- +2.7.4 + |