diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3926-drm-amd-display-add-mpc-to-dtn-log.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3926-drm-amd-display-add-mpc-to-dtn-log.patch | 143 |
1 files changed, 143 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3926-drm-amd-display-add-mpc-to-dtn-log.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3926-drm-amd-display-add-mpc-to-dtn-log.patch new file mode 100644 index 00000000..9f3dfd7d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3926-drm-amd-display-add-mpc-to-dtn-log.patch @@ -0,0 +1,143 @@ +From 5a0d587ddf25b4796fb4b3c85585bcc8ca60084f Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Wed, 24 Jan 2018 14:28:30 -0500 +Subject: [PATCH 3926/4131] drm/amd/display: add mpc to dtn log + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 31 ++++++++++++++++------ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 17 ++++++++++++ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 5 ++++ + drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 15 +++++++++++ + 4 files changed, 60 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 8b0f6b8..999190a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -121,20 +121,19 @@ void dcn10_log_hw_state(struct dc *dc) + + dcn10_log_hubbub_state(dc); + +- DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t " +- "rotation \t mirror \t sw_mode \t " +- "dcc_en \t blank_en \t ttu_dis \t underflow \t " +- "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n"); +- ++ DTN_INFO("HUBP: format addr_hi width height " ++ "rotation mirror sw_mode " ++ "dcc_en blank_en ttu_dis underflow " ++ "min_ttu_vblank qos_low_wm qos_high_wm\n"); + for (i = 0; i < pool->pipe_count; i++) { + struct hubp *hubp = pool->hubps[i]; + struct dcn_hubp_state s; + + hubp1_read_state(TO_DCN10_HUBP(hubp), &s); + +- DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t " +- "%xh \t %xh \t %xh \t " +- "%d \t %d \t %d \t %xh \t", ++ DTN_INFO("[%-2d]: %5xh %6xh %5d %6d " ++ "%7xh %5xh %6xh " ++ "%6d %8d %7d %8xh \t", + hubp->inst, + s.pixel_format, + s.inuse_addr_hi, +@@ -153,6 +152,22 @@ void dcn10_log_hw_state(struct dc *dc) + DTN_INFO("\n"); + } + DTN_INFO("\n"); ++ for (i = 0; i < pool->pipe_count; i++) { ++ struct output_pixel_processor *opp = pool->opps[i]; ++ struct mpcc *mpcc = opp->mpc_tree_params.opp_list; ++ struct mpcc_state s = {0}; ++ ++ while (mpcc) { ++ ASSERT(opp->mpc_tree_params.opp_id == opp->inst); ++ pool->mpc->funcs->read_mpcc_state(pool->mpc, mpcc->mpcc_id, &s); ++ DTN_INFO("[OPP%d - MPCC%d]: DPP%d MPCCBOT%x MODE:%d ALPHA_MODE:%d PREMULT:%d OVERLAP_ONLY:%d\n", ++ s.opp_id, mpcc->mpcc_id, s.dpp_id, s.bot_mpcc_id, ++ s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only); ++ mpcc = mpcc->mpcc_bot; ++ ASSERT(!mpcc || mpcc->mpcc_id == s.bot_mpcc_id); ++ } ++ } ++ DTN_INFO("\n"); + + DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t " + "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n"); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +index 179890b..29e15a9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +@@ -409,7 +409,24 @@ void mpc1_init_mpcc_list_from_hw( + } + } + ++void mpc1_read_mpcc_state( ++ struct mpc *mpc, ++ int mpcc_inst, ++ struct mpcc_state *s) ++{ ++ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); ++ ++ REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); ++ REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); ++ REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); ++ REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, ++ MPCC_ALPHA_BLND_MODE, &s->alpha_mode, ++ MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha, ++ MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->pre_multiplied_alpha); ++} ++ + const struct mpc_funcs dcn10_mpc_funcs = { ++ .read_mpcc_state = mpc1_read_mpcc_state, + .insert_plane = mpc1_insert_plane, + .remove_mpcc = mpc1_remove_mpcc, + .mpc_init = mpc1_mpc_init, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +index 267a299..d3d16c4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +@@ -183,4 +183,9 @@ struct mpcc *mpc1_get_mpcc_for_dpp( + struct mpc_tree *tree, + int dpp_id); + ++void mpc1_read_mpcc_state( ++ struct mpc *mpc, ++ int mpcc_inst, ++ struct mpcc_state *s); ++ + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +index 23a8d5e..5caacab 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +@@ -105,7 +105,22 @@ struct mpc { + struct mpcc mpcc_array[MAX_MPCC]; + }; + ++struct mpcc_state { ++ uint32_t opp_id; ++ uint32_t dpp_id; ++ uint32_t bot_mpcc_id; ++ uint32_t mode; ++ uint32_t alpha_mode; ++ uint32_t pre_multiplied_alpha; ++ uint32_t overlap_only; ++}; ++ + struct mpc_funcs { ++ void (*read_mpcc_state)( ++ struct mpc *mpc, ++ int mpcc_inst, ++ struct mpcc_state *s); ++ + /* + * Insert DPP into MPC tree based on specified blending position. + * Only used for planes that are part of blending chain for OPP output +-- +2.7.4 + |