diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3924-drm-amd-display-Rename-feature-specific-register-add.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3924-drm-amd-display-Rename-feature-specific-register-add.patch | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3924-drm-amd-display-Rename-feature-specific-register-add.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3924-drm-amd-display-Rename-feature-specific-register-add.patch new file mode 100644 index 00000000..822d217e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3924-drm-amd-display-Rename-feature-specific-register-add.patch @@ -0,0 +1,60 @@ +From c47220d0b4b46a3408117cc1dd410f0f5d695f67 Mon Sep 17 00:00:00 2001 +From: Nikola Cornij <nikola.cornij@amd.com> +Date: Fri, 9 Mar 2018 14:45:07 -0500 +Subject: [PATCH 3924/4131] drm/amd/display: Rename feature-specific register + address init macro + +Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +index c794ce4..e0d6d32 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +@@ -95,8 +95,8 @@ + SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ + SRI(HUBP_CLK_CNTL, HUBP, id) + +-/* Register address initialization macro for "generic" ASICs with full functionality */ +-#define HUBP_REG_LIST_DCN_GEN(id)\ ++/* Register address initialization macro for ASICs with VM */ ++#define HUBP_REG_LIST_DCN_VM(id)\ + SRI(NOM_PARAMETERS_0, HUBPREQ, id),\ + SRI(NOM_PARAMETERS_1, HUBPREQ, id),\ + SRI(NOM_PARAMETERS_2, HUBPREQ, id),\ +@@ -105,7 +105,7 @@ + + #define HUBP_REG_LIST_DCN10(id)\ + HUBP_REG_LIST_DCN(id),\ +- HUBP_REG_LIST_DCN_GEN(id),\ ++ HUBP_REG_LIST_DCN_VM(id),\ + SRI(PREFETCH_SETTINS, HUBPREQ, id),\ + SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ +@@ -361,8 +361,8 @@ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ + HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) + +-/* Mask/shift struct generation macro for "generic" ASICs with full functionality */ +-#define HUBP_MASK_SH_LIST_DCN_GEN(mask_sh)\ ++/* Mask/shift struct generation macro for ASICs with VM */ ++#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ +@@ -372,7 +372,7 @@ + + #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ + HUBP_MASK_SH_LIST_DCN(mask_sh),\ +- HUBP_MASK_SH_LIST_DCN_GEN(mask_sh),\ ++ HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ +-- +2.7.4 + |