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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3913-drm-amd-pp-clean-header-file-hwmgr.h.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3913-drm-amd-pp-clean-header-file-hwmgr.h.patch63
1 files changed, 63 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3913-drm-amd-pp-clean-header-file-hwmgr.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3913-drm-amd-pp-clean-header-file-hwmgr.h.patch
new file mode 100644
index 00000000..3cf78bea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3913-drm-amd-pp-clean-header-file-hwmgr.h.patch
@@ -0,0 +1,63 @@
+From 3bcae6b8d8dcdac839f7a082eb68df9c7bf1db77 Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Thu, 22 Mar 2018 14:38:37 +0800
+Subject: [PATCH 3913/4131] drm/amd/pp: clean header file hwmgr.h
+
+Change-Id: I5008f6f5d6c70ff2fb53cf2ca6cd7de9e9b59ebc
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 3 +++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 15 ++++++---------
+ 2 files changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
+index 6429dc2..d37d16e 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
+@@ -27,6 +27,9 @@ struct pp_atomctrl_voltage_table;
+ struct pp_hwmgr;
+ struct phm_ppt_v1_voltage_lookup_table;
+
++uint8_t convert_to_vid(uint16_t vddc);
++uint16_t convert_to_vddc(uint8_t vid);
++
+ extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
+ uint32_t index,
+ uint32_t value, uint32_t mask);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index d742d9d..17f811d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -39,9 +39,6 @@ struct pp_atomctrl_voltage_table;
+
+ #define VOLTAGE_SCALE 4
+
+-uint8_t convert_to_vid(uint16_t vddc);
+-uint16_t convert_to_vddc(uint8_t vid);
+-
+ enum DISPLAY_GAP {
+ DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
+ DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
+@@ -784,12 +781,12 @@ struct pp_hwmgr {
+ uint32_t workload_setting[Workload_Policy_Max];
+ };
+
+-extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
+-extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
+-extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
+-extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
+-extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
+-extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
++int hwmgr_early_init(struct pp_hwmgr *hwmgr);
++int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
++int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
++int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
++int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
++int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
+ enum amd_pp_task task_id,
+ enum amd_pm_state_type *user_state);
+
+--
+2.7.4
+