diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3876-drm-amdgpu-sdma4-add-sdma4_0_1-support-for-vega12-v3.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3876-drm-amdgpu-sdma4-add-sdma4_0_1-support-for-vega12-v3.patch | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3876-drm-amdgpu-sdma4-add-sdma4_0_1-support-for-vega12-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3876-drm-amdgpu-sdma4-add-sdma4_0_1-support-for-vega12-v3.patch new file mode 100644 index 00000000..cbbee734 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3876-drm-amdgpu-sdma4-add-sdma4_0_1-support-for-vega12-v3.patch @@ -0,0 +1,77 @@ +From 2ca81e69dc414a58bd8852455e42d9721089bf66 Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Mon, 12 Mar 2018 14:45:38 +0800 +Subject: [PATCH 3876/4131] drm/amdgpu/sdma4: add sdma4_0_1 support for vega12 + (v3) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add sdma golden setting for vega12. + +v2: switch to soc15_program_register_sequence for +golden register programming +v3: squash in unused declaration fix + +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index f34b63c..45841ba 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -86,6 +86,13 @@ static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) + }; + ++static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), ++ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), ++ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) ++}; ++ + static const struct soc15_reg_golden golden_settings_sdma_4_1[] = + { + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), +@@ -125,7 +132,12 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) + ARRAY_SIZE(golden_settings_sdma_vg10)); + break; + case CHIP_VEGA12: +- DRM_ERROR("todo: Missing SDMA4 golden settings for vega12\n"); ++ soc15_program_register_sequence(adev, ++ golden_settings_sdma_4, ++ ARRAY_SIZE(golden_settings_sdma_4)); ++ soc15_program_register_sequence(adev, ++ golden_settings_sdma_vg12, ++ ARRAY_SIZE(golden_settings_sdma_vg12)); + break; + case CHIP_RAVEN: + soc15_program_register_sequence(adev, +@@ -1638,7 +1650,7 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * +- * Copy GPU buffers using the DMA engine (VEGA10). ++ * Copy GPU buffers using the DMA engine (VEGA10/12). + * Used by the amdgpu ttm implementation to move pages if + * registered as the asic copy callback. + */ +@@ -1665,7 +1677,7 @@ static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * +- * Fill GPU buffers using the DMA engine (VEGA10). ++ * Fill GPU buffers using the DMA engine (VEGA10/12). + */ + static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, + uint32_t src_data, +-- +2.7.4 + |