diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3835-drm-amd-include-Add-ip-header-files-for-vega12.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3835-drm-amd-include-Add-ip-header-files-for-vega12.patch | 52564 |
1 files changed, 52564 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3835-drm-amd-include-Add-ip-header-files-for-vega12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3835-drm-amd-include-Add-ip-header-files-for-vega12.patch new file mode 100644 index 00000000..59e5b8c8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3835-drm-amd-include-Add-ip-header-files-for-vega12.patch @@ -0,0 +1,52564 @@ +From 9fca28c0416ab9e642471f137ae8ad8e327fcfdc Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Mon, 16 Oct 2017 18:09:14 +0800 +Subject: [PATCH 3835/4131] drm/amd/include: Add ip header files for vega12. + +Add ip header files for IPs with a delta for vg12: +GC, MMHUB, OSS + +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-By: Ken Wang <ken.wang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h | 7497 +++++ + .../drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h | 31160 +++++++++++++++++++ + .../include/asic_reg/mmhub/mmhub_9_3_0_offset.h | 1991 ++ + .../include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h | 10265 ++++++ + .../amd/include/asic_reg/oss/osssys_4_0_1_offset.h | 337 + + .../include/asic_reg/oss/osssys_4_0_1_sh_mask.h | 1249 + + 6 files changed, 52499 insertions(+) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h +new file mode 100644 +index 0000000..5ab240c +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h +@@ -0,0 +1,7497 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _gc_9_2_1_OFFSET_HEADER ++#define _gc_9_2_1_OFFSET_HEADER ++ ++ ++ ++// addressBlock: gc_grbmdec ++// base address: 0x8000 ++#define mmGRBM_CNTL 0x0000 ++#define mmGRBM_CNTL_BASE_IDX 0 ++#define mmGRBM_SKEW_CNTL 0x0001 ++#define mmGRBM_SKEW_CNTL_BASE_IDX 0 ++#define mmGRBM_STATUS2 0x0002 ++#define mmGRBM_STATUS2_BASE_IDX 0 ++#define mmGRBM_PWR_CNTL 0x0003 ++#define mmGRBM_PWR_CNTL_BASE_IDX 0 ++#define mmGRBM_STATUS 0x0004 ++#define mmGRBM_STATUS_BASE_IDX 0 ++#define mmGRBM_STATUS_SE0 0x0005 ++#define mmGRBM_STATUS_SE0_BASE_IDX 0 ++#define mmGRBM_STATUS_SE1 0x0006 ++#define mmGRBM_STATUS_SE1_BASE_IDX 0 ++#define mmGRBM_SOFT_RESET 0x0008 ++#define mmGRBM_SOFT_RESET_BASE_IDX 0 ++#define mmGRBM_GFX_CLKEN_CNTL 0x000c ++#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 ++#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d ++#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 ++#define mmGRBM_STATUS_SE2 0x000e ++#define mmGRBM_STATUS_SE2_BASE_IDX 0 ++#define mmGRBM_STATUS_SE3 0x000f ++#define mmGRBM_STATUS_SE3_BASE_IDX 0 ++#define mmGRBM_READ_ERROR 0x0016 ++#define mmGRBM_READ_ERROR_BASE_IDX 0 ++#define mmGRBM_READ_ERROR2 0x0017 ++#define mmGRBM_READ_ERROR2_BASE_IDX 0 ++#define mmGRBM_INT_CNTL 0x0018 ++#define mmGRBM_INT_CNTL_BASE_IDX 0 ++#define mmGRBM_TRAP_OP 0x0019 ++#define mmGRBM_TRAP_OP_BASE_IDX 0 ++#define mmGRBM_TRAP_ADDR 0x001a ++#define mmGRBM_TRAP_ADDR_BASE_IDX 0 ++#define mmGRBM_TRAP_ADDR_MSK 0x001b ++#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 ++#define mmGRBM_TRAP_WD 0x001c ++#define mmGRBM_TRAP_WD_BASE_IDX 0 ++#define mmGRBM_TRAP_WD_MSK 0x001d ++#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 ++#define mmGRBM_DSM_BYPASS 0x001e ++#define mmGRBM_DSM_BYPASS_BASE_IDX 0 ++#define mmGRBM_WRITE_ERROR 0x001f ++#define mmGRBM_WRITE_ERROR_BASE_IDX 0 ++#define mmGRBM_IOV_ERROR 0x0020 ++#define mmGRBM_IOV_ERROR_BASE_IDX 0 ++#define mmGRBM_CHIP_REVISION 0x0021 ++#define mmGRBM_CHIP_REVISION_BASE_IDX 0 ++#define mmGRBM_GFX_CNTL 0x0022 ++#define mmGRBM_GFX_CNTL_BASE_IDX 0 ++#define mmGRBM_RSMU_CFG 0x0023 ++#define mmGRBM_RSMU_CFG_BASE_IDX 0 ++#define mmGRBM_IH_CREDIT 0x0024 ++#define mmGRBM_IH_CREDIT_BASE_IDX 0 ++#define mmGRBM_PWR_CNTL2 0x0025 ++#define mmGRBM_PWR_CNTL2_BASE_IDX 0 ++#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026 ++#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 ++#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027 ++#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 ++#define mmGRBM_RSMU_READ_ERROR 0x0028 ++#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0 ++#define mmGRBM_CHICKEN_BITS 0x0029 ++#define mmGRBM_CHICKEN_BITS_BASE_IDX 0 ++#define mmGRBM_FENCE_RANGE0 0x002a ++#define mmGRBM_FENCE_RANGE0_BASE_IDX 0 ++#define mmGRBM_FENCE_RANGE1 0x002b ++#define mmGRBM_FENCE_RANGE1_BASE_IDX 0 ++#define mmGRBM_NOWHERE 0x003f ++#define mmGRBM_NOWHERE_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG0 0x0040 ++#define mmGRBM_SCRATCH_REG0_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG1 0x0041 ++#define mmGRBM_SCRATCH_REG1_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG2 0x0042 ++#define mmGRBM_SCRATCH_REG2_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG3 0x0043 ++#define mmGRBM_SCRATCH_REG3_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG4 0x0044 ++#define mmGRBM_SCRATCH_REG4_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG5 0x0045 ++#define mmGRBM_SCRATCH_REG5_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG6 0x0046 ++#define mmGRBM_SCRATCH_REG6_BASE_IDX 0 ++#define mmGRBM_SCRATCH_REG7 0x0047 ++#define mmGRBM_SCRATCH_REG7_BASE_IDX 0 ++ ++ ++// addressBlock: gc_cpdec ++// base address: 0x8200 ++#define mmCP_CPC_STATUS 0x0084 ++#define mmCP_CPC_STATUS_BASE_IDX 0 ++#define mmCP_CPC_BUSY_STAT 0x0085 ++#define mmCP_CPC_BUSY_STAT_BASE_IDX 0 ++#define mmCP_CPC_STALLED_STAT1 0x0086 ++#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0 ++#define mmCP_CPF_STATUS 0x0087 ++#define mmCP_CPF_STATUS_BASE_IDX 0 ++#define mmCP_CPF_BUSY_STAT 0x0088 ++#define mmCP_CPF_BUSY_STAT_BASE_IDX 0 ++#define mmCP_CPF_STALLED_STAT1 0x0089 ++#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0 ++#define mmCP_CPC_GRBM_FREE_COUNT 0x008b ++#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 ++#define mmCP_MEC_CNTL 0x008d ++#define mmCP_MEC_CNTL_BASE_IDX 0 ++#define mmCP_MEC_ME1_HEADER_DUMP 0x008e ++#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 ++#define mmCP_MEC_ME2_HEADER_DUMP 0x008f ++#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 ++#define mmCP_CPC_SCRATCH_INDEX 0x0090 ++#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0 ++#define mmCP_CPC_SCRATCH_DATA 0x0091 ++#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0 ++#define mmCP_CPF_GRBM_FREE_COUNT 0x0092 ++#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 ++#define mmCP_CPC_HALT_HYST_COUNT 0x00a7 ++#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 ++#define mmCP_CE_COMPARE_COUNT 0x00c0 ++#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0 ++#define mmCP_CE_DE_COUNT 0x00c1 ++#define mmCP_CE_DE_COUNT_BASE_IDX 0 ++#define mmCP_DE_CE_COUNT 0x00c2 ++#define mmCP_DE_CE_COUNT_BASE_IDX 0 ++#define mmCP_DE_LAST_INVAL_COUNT 0x00c3 ++#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 ++#define mmCP_DE_DE_COUNT 0x00c4 ++#define mmCP_DE_DE_COUNT_BASE_IDX 0 ++#define mmCP_STALLED_STAT3 0x019c ++#define mmCP_STALLED_STAT3_BASE_IDX 0 ++#define mmCP_STALLED_STAT1 0x019d ++#define mmCP_STALLED_STAT1_BASE_IDX 0 ++#define mmCP_STALLED_STAT2 0x019e ++#define mmCP_STALLED_STAT2_BASE_IDX 0 ++#define mmCP_BUSY_STAT 0x019f ++#define mmCP_BUSY_STAT_BASE_IDX 0 ++#define mmCP_STAT 0x01a0 ++#define mmCP_STAT_BASE_IDX 0 ++#define mmCP_ME_HEADER_DUMP 0x01a1 ++#define mmCP_ME_HEADER_DUMP_BASE_IDX 0 ++#define mmCP_PFP_HEADER_DUMP 0x01a2 ++#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0 ++#define mmCP_GRBM_FREE_COUNT 0x01a3 ++#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0 ++#define mmCP_CE_HEADER_DUMP 0x01a4 ++#define mmCP_CE_HEADER_DUMP_BASE_IDX 0 ++#define mmCP_PFP_INSTR_PNTR 0x01a5 ++#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0 ++#define mmCP_ME_INSTR_PNTR 0x01a6 ++#define mmCP_ME_INSTR_PNTR_BASE_IDX 0 ++#define mmCP_CE_INSTR_PNTR 0x01a7 ++#define mmCP_CE_INSTR_PNTR_BASE_IDX 0 ++#define mmCP_MEC1_INSTR_PNTR 0x01a8 ++#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0 ++#define mmCP_MEC2_INSTR_PNTR 0x01a9 ++#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0 ++#define mmCP_CSF_STAT 0x01b4 ++#define mmCP_CSF_STAT_BASE_IDX 0 ++#define mmCP_ME_CNTL 0x01b6 ++#define mmCP_ME_CNTL_BASE_IDX 0 ++#define mmCP_CNTX_STAT 0x01b8 ++#define mmCP_CNTX_STAT_BASE_IDX 0 ++#define mmCP_ME_PREEMPTION 0x01b9 ++#define mmCP_ME_PREEMPTION_BASE_IDX 0 ++#define mmCP_ROQ_THRESHOLDS 0x01bc ++#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0 ++#define mmCP_MEQ_STQ_THRESHOLD 0x01bd ++#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 ++#define mmCP_RB2_RPTR 0x01be ++#define mmCP_RB2_RPTR_BASE_IDX 0 ++#define mmCP_RB1_RPTR 0x01bf ++#define mmCP_RB1_RPTR_BASE_IDX 0 ++#define mmCP_RB0_RPTR 0x01c0 ++#define mmCP_RB0_RPTR_BASE_IDX 0 ++#define mmCP_RB_RPTR 0x01c0 ++#define mmCP_RB_RPTR_BASE_IDX 0 ++#define mmCP_RB_WPTR_DELAY 0x01c1 ++#define mmCP_RB_WPTR_DELAY_BASE_IDX 0 ++#define mmCP_RB_WPTR_POLL_CNTL 0x01c2 ++#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmCP_ROQ1_THRESHOLDS 0x01d5 ++#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0 ++#define mmCP_ROQ2_THRESHOLDS 0x01d6 ++#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0 ++#define mmCP_STQ_THRESHOLDS 0x01d7 ++#define mmCP_STQ_THRESHOLDS_BASE_IDX 0 ++#define mmCP_QUEUE_THRESHOLDS 0x01d8 ++#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0 ++#define mmCP_MEQ_THRESHOLDS 0x01d9 ++#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0 ++#define mmCP_ROQ_AVAIL 0x01da ++#define mmCP_ROQ_AVAIL_BASE_IDX 0 ++#define mmCP_STQ_AVAIL 0x01db ++#define mmCP_STQ_AVAIL_BASE_IDX 0 ++#define mmCP_ROQ2_AVAIL 0x01dc ++#define mmCP_ROQ2_AVAIL_BASE_IDX 0 ++#define mmCP_MEQ_AVAIL 0x01dd ++#define mmCP_MEQ_AVAIL_BASE_IDX 0 ++#define mmCP_CMD_INDEX 0x01de ++#define mmCP_CMD_INDEX_BASE_IDX 0 ++#define mmCP_CMD_DATA 0x01df ++#define mmCP_CMD_DATA_BASE_IDX 0 ++#define mmCP_ROQ_RB_STAT 0x01e0 ++#define mmCP_ROQ_RB_STAT_BASE_IDX 0 ++#define mmCP_ROQ_IB1_STAT 0x01e1 ++#define mmCP_ROQ_IB1_STAT_BASE_IDX 0 ++#define mmCP_ROQ_IB2_STAT 0x01e2 ++#define mmCP_ROQ_IB2_STAT_BASE_IDX 0 ++#define mmCP_STQ_STAT 0x01e3 ++#define mmCP_STQ_STAT_BASE_IDX 0 ++#define mmCP_STQ_WR_STAT 0x01e4 ++#define mmCP_STQ_WR_STAT_BASE_IDX 0 ++#define mmCP_MEQ_STAT 0x01e5 ++#define mmCP_MEQ_STAT_BASE_IDX 0 ++#define mmCP_CEQ1_AVAIL 0x01e6 ++#define mmCP_CEQ1_AVAIL_BASE_IDX 0 ++#define mmCP_CEQ2_AVAIL 0x01e7 ++#define mmCP_CEQ2_AVAIL_BASE_IDX 0 ++#define mmCP_CE_ROQ_RB_STAT 0x01e8 ++#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0 ++#define mmCP_CE_ROQ_IB1_STAT 0x01e9 ++#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0 ++#define mmCP_CE_ROQ_IB2_STAT 0x01ea ++#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0 ++ ++ ++// addressBlock: gc_padec ++// base address: 0x8800 ++#define mmVGT_VTX_VECT_EJECT_REG 0x022c ++#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 ++#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d ++#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 ++#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e ++#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 ++#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f ++#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 ++#define mmVGT_LAST_COPY_STATE 0x0230 ++#define mmVGT_LAST_COPY_STATE_BASE_IDX 0 ++#define mmVGT_CACHE_INVALIDATION 0x0231 ++#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0 ++#define mmVGT_STRMOUT_DELAY 0x0233 ++#define mmVGT_STRMOUT_DELAY_BASE_IDX 0 ++#define mmVGT_FIFO_DEPTHS 0x0234 ++#define mmVGT_FIFO_DEPTHS_BASE_IDX 0 ++#define mmVGT_GS_VERTEX_REUSE 0x0235 ++#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0 ++#define mmVGT_MC_LAT_CNTL 0x0236 ++#define mmVGT_MC_LAT_CNTL_BASE_IDX 0 ++#define mmIA_CNTL_STATUS 0x0237 ++#define mmIA_CNTL_STATUS_BASE_IDX 0 ++#define mmVGT_CNTL_STATUS 0x023c ++#define mmVGT_CNTL_STATUS_BASE_IDX 0 ++#define mmWD_CNTL_STATUS 0x023f ++#define mmWD_CNTL_STATUS_BASE_IDX 0 ++#define mmCC_GC_PRIM_CONFIG 0x0240 ++#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0 ++#define mmGC_USER_PRIM_CONFIG 0x0241 ++#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0 ++#define mmWD_QOS 0x0242 ++#define mmWD_QOS_BASE_IDX 0 ++#define mmWD_UTCL1_CNTL 0x0243 ++#define mmWD_UTCL1_CNTL_BASE_IDX 0 ++#define mmWD_UTCL1_STATUS 0x0244 ++#define mmWD_UTCL1_STATUS_BASE_IDX 0 ++#define mmIA_UTCL1_CNTL 0x0246 ++#define mmIA_UTCL1_CNTL_BASE_IDX 0 ++#define mmIA_UTCL1_STATUS 0x0247 ++#define mmIA_UTCL1_STATUS_BASE_IDX 0 ++#define mmVGT_SYS_CONFIG 0x0263 ++#define mmVGT_SYS_CONFIG_BASE_IDX 0 ++#define mmVGT_VS_MAX_WAVE_ID 0x0268 ++#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0 ++#define mmVGT_GS_MAX_WAVE_ID 0x0269 ++#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0 ++#define mmGFX_PIPE_CONTROL 0x026d ++#define mmGFX_PIPE_CONTROL_BASE_IDX 0 ++#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f ++#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 ++#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270 ++#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 ++#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271 ++#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 ++#define mmVGT_DMA_CONTROL 0x0272 ++#define mmVGT_DMA_CONTROL_BASE_IDX 0 ++#define mmVGT_DMA_LS_HS_CONFIG 0x0273 ++#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 ++#define mmWD_BUF_RESOURCE_1 0x0276 ++#define mmWD_BUF_RESOURCE_1_BASE_IDX 0 ++#define mmWD_BUF_RESOURCE_2 0x0277 ++#define mmWD_BUF_RESOURCE_2_BASE_IDX 0 ++#define mmPA_CL_CNTL_STATUS 0x0284 ++#define mmPA_CL_CNTL_STATUS_BASE_IDX 0 ++#define mmPA_CL_ENHANCE 0x0285 ++#define mmPA_CL_ENHANCE_BASE_IDX 0 ++#define mmPA_SU_CNTL_STATUS 0x0294 ++#define mmPA_SU_CNTL_STATUS_BASE_IDX 0 ++#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295 ++#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 ++#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0 ++#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 ++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1 ++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 ++#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2 ++#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 ++#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9 ++#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 ++#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc ++#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 ++#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd ++#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 ++#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce ++#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 ++#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf ++#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 ++#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0 ++#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 ++#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1 ++#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 ++#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2 ++#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 ++#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3 ++#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 ++#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4 ++#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 ++#define mmPA_SC_ENHANCE_2 0x02dc ++#define mmPA_SC_ENHANCE_2_BASE_IDX 0 ++#define mmPA_SC_FIFO_SIZE 0x02f3 ++#define mmPA_SC_FIFO_SIZE_BASE_IDX 0 ++#define mmPA_SC_IF_FIFO_SIZE 0x02f5 ++#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0 ++#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8 ++#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 ++#define mmPA_UTCL1_CNTL1 0x02f9 ++#define mmPA_UTCL1_CNTL1_BASE_IDX 0 ++#define mmPA_UTCL1_CNTL2 0x02fa ++#define mmPA_UTCL1_CNTL2_BASE_IDX 0 ++#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb ++#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 ++#define mmPA_SC_ENHANCE 0x02fc ++#define mmPA_SC_ENHANCE_BASE_IDX 0 ++#define mmPA_SC_ENHANCE_1 0x02fd ++#define mmPA_SC_ENHANCE_1_BASE_IDX 0 ++#define mmPA_SC_DSM_CNTL 0x02fe ++#define mmPA_SC_DSM_CNTL_BASE_IDX 0 ++#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff ++#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 ++ ++ ++// addressBlock: gc_sqdec ++// base address: 0x8c00 ++#define mmSQ_CONFIG 0x0300 ++#define mmSQ_CONFIG_BASE_IDX 0 ++#define mmSQC_CONFIG 0x0301 ++#define mmSQC_CONFIG_BASE_IDX 0 ++#define mmLDS_CONFIG 0x0302 ++#define mmLDS_CONFIG_BASE_IDX 0 ++#define mmSQ_RANDOM_WAVE_PRI 0x0303 ++#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0 ++#define mmSQ_REG_CREDITS 0x0304 ++#define mmSQ_REG_CREDITS_BASE_IDX 0 ++#define mmSQ_FIFO_SIZES 0x0305 ++#define mmSQ_FIFO_SIZES_BASE_IDX 0 ++#define mmSQ_DSM_CNTL 0x0306 ++#define mmSQ_DSM_CNTL_BASE_IDX 0 ++#define mmSQ_DSM_CNTL2 0x0307 ++#define mmSQ_DSM_CNTL2_BASE_IDX 0 ++#define mmSQ_RUNTIME_CONFIG 0x0308 ++#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0 ++#define mmSH_MEM_BASES 0x030a ++#define mmSH_MEM_BASES_BASE_IDX 0 ++#define mmSH_MEM_CONFIG 0x030d ++#define mmSH_MEM_CONFIG_BASE_IDX 0 ++#define mmCC_GC_SHADER_RATE_CONFIG 0x0312 ++#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 ++#define mmGC_USER_SHADER_RATE_CONFIG 0x0313 ++#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0 ++#define mmSQ_INTERRUPT_AUTO_MASK 0x0314 ++#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 ++#define mmSQ_INTERRUPT_MSG_CTRL 0x0315 ++#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 ++#define mmSQ_UTCL1_CNTL1 0x0317 ++#define mmSQ_UTCL1_CNTL1_BASE_IDX 0 ++#define mmSQ_UTCL1_CNTL2 0x0318 ++#define mmSQ_UTCL1_CNTL2_BASE_IDX 0 ++#define mmSQ_UTCL1_STATUS 0x0319 ++#define mmSQ_UTCL1_STATUS_BASE_IDX 0 ++#define mmSQ_SHADER_TBA_LO 0x031c ++#define mmSQ_SHADER_TBA_LO_BASE_IDX 0 ++#define mmSQ_SHADER_TBA_HI 0x031d ++#define mmSQ_SHADER_TBA_HI_BASE_IDX 0 ++#define mmSQ_SHADER_TMA_LO 0x031e ++#define mmSQ_SHADER_TMA_LO_BASE_IDX 0 ++#define mmSQ_SHADER_TMA_HI 0x031f ++#define mmSQ_SHADER_TMA_HI_BASE_IDX 0 ++#define mmSQC_DSM_CNTL 0x0320 ++#define mmSQC_DSM_CNTL_BASE_IDX 0 ++#define mmSQC_DSM_CNTLA 0x0321 ++#define mmSQC_DSM_CNTLA_BASE_IDX 0 ++#define mmSQC_DSM_CNTLB 0x0322 ++#define mmSQC_DSM_CNTLB_BASE_IDX 0 ++#define mmSQC_DSM_CNTL2 0x0325 ++#define mmSQC_DSM_CNTL2_BASE_IDX 0 ++#define mmSQC_DSM_CNTL2A 0x0326 ++#define mmSQC_DSM_CNTL2A_BASE_IDX 0 ++#define mmSQC_DSM_CNTL2B 0x0327 ++#define mmSQC_DSM_CNTL2B_BASE_IDX 0 ++#define mmSQ_REG_TIMESTAMP 0x0374 ++#define mmSQ_REG_TIMESTAMP_BASE_IDX 0 ++#define mmSQ_CMD_TIMESTAMP 0x0375 ++#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0 ++#define mmSQ_IND_INDEX 0x0378 ++#define mmSQ_IND_INDEX_BASE_IDX 0 ++#define mmSQ_IND_DATA 0x0379 ++#define mmSQ_IND_DATA_BASE_IDX 0 ++#define mmSQ_CMD 0x037b ++#define mmSQ_CMD_BASE_IDX 0 ++#define mmSQ_TIME_HI 0x037c ++#define mmSQ_TIME_HI_BASE_IDX 0 ++#define mmSQ_TIME_LO 0x037d ++#define mmSQ_TIME_LO_BASE_IDX 0 ++#define mmSQ_DS_0 0x037f ++#define mmSQ_DS_0_BASE_IDX 0 ++#define mmSQ_DS_1 0x037f ++#define mmSQ_DS_1_BASE_IDX 0 ++#define mmSQ_EXP_0 0x037f ++#define mmSQ_EXP_0_BASE_IDX 0 ++#define mmSQ_EXP_1 0x037f ++#define mmSQ_EXP_1_BASE_IDX 0 ++#define mmSQ_FLAT_0 0x037f ++#define mmSQ_FLAT_0_BASE_IDX 0 ++#define mmSQ_FLAT_1 0x037f ++#define mmSQ_FLAT_1_BASE_IDX 0 ++#define mmSQ_GLBL_0 0x037f ++#define mmSQ_GLBL_0_BASE_IDX 0 ++#define mmSQ_GLBL_1 0x037f ++#define mmSQ_GLBL_1_BASE_IDX 0 ++#define mmSQ_INST 0x037f ++#define mmSQ_INST_BASE_IDX 0 ++#define mmSQ_MIMG_0 0x037f ++#define mmSQ_MIMG_0_BASE_IDX 0 ++#define mmSQ_MIMG_1 0x037f ++#define mmSQ_MIMG_1_BASE_IDX 0 ++#define mmSQ_MTBUF_0 0x037f ++#define mmSQ_MTBUF_0_BASE_IDX 0 ++#define mmSQ_MTBUF_1 0x037f ++#define mmSQ_MTBUF_1_BASE_IDX 0 ++#define mmSQ_MUBUF_0 0x037f ++#define mmSQ_MUBUF_0_BASE_IDX 0 ++#define mmSQ_MUBUF_1 0x037f ++#define mmSQ_MUBUF_1_BASE_IDX 0 ++#define mmSQ_SCRATCH_0 0x037f ++#define mmSQ_SCRATCH_0_BASE_IDX 0 ++#define mmSQ_SCRATCH_1 0x037f ++#define mmSQ_SCRATCH_1_BASE_IDX 0 ++#define mmSQ_SMEM_0 0x037f ++#define mmSQ_SMEM_0_BASE_IDX 0 ++#define mmSQ_SMEM_1 0x037f ++#define mmSQ_SMEM_1_BASE_IDX 0 ++#define mmSQ_SOP1 0x037f ++#define mmSQ_SOP1_BASE_IDX 0 ++#define mmSQ_SOP2 0x037f ++#define mmSQ_SOP2_BASE_IDX 0 ++#define mmSQ_SOPC 0x037f ++#define mmSQ_SOPC_BASE_IDX 0 ++#define mmSQ_SOPK 0x037f ++#define mmSQ_SOPK_BASE_IDX 0 ++#define mmSQ_SOPP 0x037f ++#define mmSQ_SOPP_BASE_IDX 0 ++#define mmSQ_VINTRP 0x037f ++#define mmSQ_VINTRP_BASE_IDX 0 ++#define mmSQ_VOP1 0x037f ++#define mmSQ_VOP1_BASE_IDX 0 ++#define mmSQ_VOP2 0x037f ++#define mmSQ_VOP2_BASE_IDX 0 ++#define mmSQ_VOP3P_0 0x037f ++#define mmSQ_VOP3P_0_BASE_IDX 0 ++#define mmSQ_VOP3P_1 0x037f ++#define mmSQ_VOP3P_1_BASE_IDX 0 ++#define mmSQ_VOP3_0 0x037f ++#define mmSQ_VOP3_0_BASE_IDX 0 ++#define mmSQ_VOP3_0_SDST_ENC 0x037f ++#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0 ++#define mmSQ_VOP3_1 0x037f ++#define mmSQ_VOP3_1_BASE_IDX 0 ++#define mmSQ_VOPC 0x037f ++#define mmSQ_VOPC_BASE_IDX 0 ++#define mmSQ_VOP_DPP 0x037f ++#define mmSQ_VOP_DPP_BASE_IDX 0 ++#define mmSQ_VOP_SDWA 0x037f ++#define mmSQ_VOP_SDWA_BASE_IDX 0 ++#define mmSQ_VOP_SDWA_SDST_ENC 0x037f ++#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0 ++#define mmSQ_LB_CTR_CTRL 0x0398 ++#define mmSQ_LB_CTR_CTRL_BASE_IDX 0 ++#define mmSQ_LB_DATA0 0x0399 ++#define mmSQ_LB_DATA0_BASE_IDX 0 ++#define mmSQ_LB_DATA1 0x039a ++#define mmSQ_LB_DATA1_BASE_IDX 0 ++#define mmSQ_LB_DATA2 0x039b ++#define mmSQ_LB_DATA2_BASE_IDX 0 ++#define mmSQ_LB_DATA3 0x039c ++#define mmSQ_LB_DATA3_BASE_IDX 0 ++#define mmSQ_LB_CTR_SEL 0x039d ++#define mmSQ_LB_CTR_SEL_BASE_IDX 0 ++#define mmSQ_LB_CTR0_CU 0x039e ++#define mmSQ_LB_CTR0_CU_BASE_IDX 0 ++#define mmSQ_LB_CTR1_CU 0x039f ++#define mmSQ_LB_CTR1_CU_BASE_IDX 0 ++#define mmSQ_LB_CTR2_CU 0x03a0 ++#define mmSQ_LB_CTR2_CU_BASE_IDX 0 ++#define mmSQ_LB_CTR3_CU 0x03a1 ++#define mmSQ_LB_CTR3_CU_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0 ++#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1 ++#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1 ++#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1 ++#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0 ++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1 ++#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0 ++#define mmSQ_WREXEC_EXEC_HI 0x03b1 ++#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0 ++#define mmSQ_WREXEC_EXEC_LO 0x03b1 ++#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0 ++#define mmSQ_BUF_RSRC_WORD0 0x03c0 ++#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0 ++#define mmSQ_BUF_RSRC_WORD1 0x03c1 ++#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0 ++#define mmSQ_BUF_RSRC_WORD2 0x03c2 ++#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0 ++#define mmSQ_BUF_RSRC_WORD3 0x03c3 ++#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD0 0x03c4 ++#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD1 0x03c5 ++#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD2 0x03c6 ++#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD3 0x03c7 ++#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD4 0x03c8 ++#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD5 0x03c9 ++#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD6 0x03ca ++#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0 ++#define mmSQ_IMG_RSRC_WORD7 0x03cb ++#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0 ++#define mmSQ_IMG_SAMP_WORD0 0x03cc ++#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0 ++#define mmSQ_IMG_SAMP_WORD1 0x03cd ++#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0 ++#define mmSQ_IMG_SAMP_WORD2 0x03ce ++#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0 ++#define mmSQ_IMG_SAMP_WORD3 0x03cf ++#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0 ++#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0 ++#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0 ++#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1 ++#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0 ++#define mmSQ_M0_GPR_IDX_WORD 0x03d2 ++#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0 ++#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3 ++#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0 ++#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4 ++#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0 ++#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5 ++#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0 ++#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6 ++#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0 ++#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7 ++#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 ++#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8 ++#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 ++ ++ ++// addressBlock: gc_shsdec ++// base address: 0x9000 ++#define mmSX_DEBUG_1 0x0419 ++#define mmSX_DEBUG_1_BASE_IDX 0 ++#define mmSPI_PS_MAX_WAVE_ID 0x043a ++#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0 ++#define mmSPI_START_PHASE 0x043b ++#define mmSPI_START_PHASE_BASE_IDX 0 ++#define mmSPI_GFX_CNTL 0x043c ++#define mmSPI_GFX_CNTL_BASE_IDX 0 ++#define mmSPI_DSM_CNTL 0x0443 ++#define mmSPI_DSM_CNTL_BASE_IDX 0 ++#define mmSPI_DSM_CNTL2 0x0444 ++#define mmSPI_DSM_CNTL2_BASE_IDX 0 ++#define mmSPI_CONFIG_PS_CU_EN 0x0452 ++#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_CNTL 0x04aa ++#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab ++#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac ++#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad ++#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae ++#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af ++#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0 ++#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1 ++#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2 ++#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3 ++#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4 ++#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5 ++#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6 ++#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7 ++#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8 ++#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9 ++#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba ++#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb ++#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc ++#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd ++#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_9 0x04be ++#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf ++#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0 ++#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1 ++#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2 ++#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3 ++#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4 ++#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5 ++#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6 ++#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7 ++#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8 ++#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 ++#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9 ++#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 ++#define mmSPI_LB_CTR_CTRL 0x04d4 ++#define mmSPI_LB_CTR_CTRL_BASE_IDX 0 ++#define mmSPI_LB_CU_MASK 0x04d5 ++#define mmSPI_LB_CU_MASK_BASE_IDX 0 ++#define mmSPI_LB_DATA_REG 0x04d6 ++#define mmSPI_LB_DATA_REG_BASE_IDX 0 ++#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7 ++#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0 ++#define mmSPI_GDS_CREDITS 0x04d8 ++#define mmSPI_GDS_CREDITS_BASE_IDX 0 ++#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9 ++#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 ++#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da ++#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db ++#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3 ++#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 ++#define mmSPI_LB_DATA_WAVES 0x04e4 ++#define mmSPI_LB_DATA_WAVES_BASE_IDX 0 ++#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5 ++#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0 ++#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6 ++#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0 ++#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7 ++#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0 ++#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec ++#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 ++#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed ++#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 ++#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee ++#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 ++#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef ++#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 ++#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0 ++#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 ++#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1 ++#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 ++#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2 ++#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 ++#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3 ++#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 ++#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4 ++#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 ++#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5 ++#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 ++ ++ ++// addressBlock: gc_tpdec ++// base address: 0x9400 ++#define mmTD_CNTL 0x0525 ++#define mmTD_CNTL_BASE_IDX 0 ++#define mmTD_STATUS 0x0526 ++#define mmTD_STATUS_BASE_IDX 0 ++#define mmTD_DSM_CNTL 0x052f ++#define mmTD_DSM_CNTL_BASE_IDX 0 ++#define mmTD_DSM_CNTL2 0x0530 ++#define mmTD_DSM_CNTL2_BASE_IDX 0 ++#define mmTD_SCRATCH 0x0533 ++#define mmTD_SCRATCH_BASE_IDX 0 ++#define mmTA_CNTL 0x0541 ++#define mmTA_CNTL_BASE_IDX 0 ++#define mmTA_CNTL_AUX 0x0542 ++#define mmTA_CNTL_AUX_BASE_IDX 0 ++#define mmTA_RESERVED_010C 0x0543 ++#define mmTA_RESERVED_010C_BASE_IDX 0 ++#define mmTA_STATUS 0x0548 ++#define mmTA_STATUS_BASE_IDX 0 ++#define mmTA_SCRATCH 0x0564 ++#define mmTA_SCRATCH_BASE_IDX 0 ++ ++ ++// addressBlock: gc_gdsdec ++// base address: 0x9700 ++#define mmGDS_CONFIG 0x05c0 ++#define mmGDS_CONFIG_BASE_IDX 0 ++#define mmGDS_CNTL_STATUS 0x05c1 ++#define mmGDS_CNTL_STATUS_BASE_IDX 0 ++#define mmGDS_ENHANCE2 0x05c2 ++#define mmGDS_ENHANCE2_BASE_IDX 0 ++#define mmGDS_PROTECTION_FAULT 0x05c3 ++#define mmGDS_PROTECTION_FAULT_BASE_IDX 0 ++#define mmGDS_VM_PROTECTION_FAULT 0x05c4 ++#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0 ++#define mmGDS_DSM_CNTL 0x05ca ++#define mmGDS_DSM_CNTL_BASE_IDX 0 ++#define mmGDS_DSM_CNTL2 0x05cd ++#define mmGDS_DSM_CNTL2_BASE_IDX 0 ++#define mmGDS_WD_GDS_CSB 0x05ce ++#define mmGDS_WD_GDS_CSB_BASE_IDX 0 ++ ++ ++// addressBlock: gc_rbdec ++// base address: 0x9800 ++#define mmDB_DEBUG 0x060c ++#define mmDB_DEBUG_BASE_IDX 0 ++#define mmDB_DEBUG2 0x060d ++#define mmDB_DEBUG2_BASE_IDX 0 ++#define mmDB_DEBUG3 0x060e ++#define mmDB_DEBUG3_BASE_IDX 0 ++#define mmDB_DEBUG4 0x060f ++#define mmDB_DEBUG4_BASE_IDX 0 ++#define mmDB_CREDIT_LIMIT 0x0614 ++#define mmDB_CREDIT_LIMIT_BASE_IDX 0 ++#define mmDB_WATERMARKS 0x0615 ++#define mmDB_WATERMARKS_BASE_IDX 0 ++#define mmDB_SUBTILE_CONTROL 0x0616 ++#define mmDB_SUBTILE_CONTROL_BASE_IDX 0 ++#define mmDB_FREE_CACHELINES 0x0617 ++#define mmDB_FREE_CACHELINES_BASE_IDX 0 ++#define mmDB_FIFO_DEPTH1 0x0618 ++#define mmDB_FIFO_DEPTH1_BASE_IDX 0 ++#define mmDB_FIFO_DEPTH2 0x0619 ++#define mmDB_FIFO_DEPTH2_BASE_IDX 0 ++#define mmDB_EXCEPTION_CONTROL 0x061a ++#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0 ++#define mmDB_RING_CONTROL 0x061b ++#define mmDB_RING_CONTROL_BASE_IDX 0 ++#define mmDB_MEM_ARB_WATERMARKS 0x061c ++#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0 ++#define mmDB_RMI_CACHE_POLICY 0x061e ++#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0 ++#define mmDB_DFSM_CONFIG 0x0630 ++#define mmDB_DFSM_CONFIG_BASE_IDX 0 ++#define mmDB_DFSM_WATERMARK 0x0631 ++#define mmDB_DFSM_WATERMARK_BASE_IDX 0 ++#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632 ++#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 ++#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633 ++#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 ++#define mmDB_DFSM_WATCHDOG 0x0634 ++#define mmDB_DFSM_WATCHDOG_BASE_IDX 0 ++#define mmDB_DFSM_FLUSH_ENABLE 0x0635 ++#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 ++#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636 ++#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 ++#define mmCC_RB_REDUNDANCY 0x063c ++#define mmCC_RB_REDUNDANCY_BASE_IDX 0 ++#define mmCC_RB_BACKEND_DISABLE 0x063d ++#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0 ++#define mmGB_ADDR_CONFIG 0x063e ++#define mmGB_ADDR_CONFIG_BASE_IDX 0 ++#define mmGB_BACKEND_MAP 0x063f ++#define mmGB_BACKEND_MAP_BASE_IDX 0 ++#define mmGB_GPU_ID 0x0640 ++#define mmGB_GPU_ID_BASE_IDX 0 ++#define mmCC_RB_DAISY_CHAIN 0x0641 ++#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0 ++#define mmGB_ADDR_CONFIG_READ 0x0642 ++#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0 ++#define mmGB_TILE_MODE0 0x0644 ++#define mmGB_TILE_MODE0_BASE_IDX 0 ++#define mmGB_TILE_MODE1 0x0645 ++#define mmGB_TILE_MODE1_BASE_IDX 0 ++#define mmGB_TILE_MODE2 0x0646 ++#define mmGB_TILE_MODE2_BASE_IDX 0 ++#define mmGB_TILE_MODE3 0x0647 ++#define mmGB_TILE_MODE3_BASE_IDX 0 ++#define mmGB_TILE_MODE4 0x0648 ++#define mmGB_TILE_MODE4_BASE_IDX 0 ++#define mmGB_TILE_MODE5 0x0649 ++#define mmGB_TILE_MODE5_BASE_IDX 0 ++#define mmGB_TILE_MODE6 0x064a ++#define mmGB_TILE_MODE6_BASE_IDX 0 ++#define mmGB_TILE_MODE7 0x064b ++#define mmGB_TILE_MODE7_BASE_IDX 0 ++#define mmGB_TILE_MODE8 0x064c ++#define mmGB_TILE_MODE8_BASE_IDX 0 ++#define mmGB_TILE_MODE9 0x064d ++#define mmGB_TILE_MODE9_BASE_IDX 0 ++#define mmGB_TILE_MODE10 0x064e ++#define mmGB_TILE_MODE10_BASE_IDX 0 ++#define mmGB_TILE_MODE11 0x064f ++#define mmGB_TILE_MODE11_BASE_IDX 0 ++#define mmGB_TILE_MODE12 0x0650 ++#define mmGB_TILE_MODE12_BASE_IDX 0 ++#define mmGB_TILE_MODE13 0x0651 ++#define mmGB_TILE_MODE13_BASE_IDX 0 ++#define mmGB_TILE_MODE14 0x0652 ++#define mmGB_TILE_MODE14_BASE_IDX 0 ++#define mmGB_TILE_MODE15 0x0653 ++#define mmGB_TILE_MODE15_BASE_IDX 0 ++#define mmGB_TILE_MODE16 0x0654 ++#define mmGB_TILE_MODE16_BASE_IDX 0 ++#define mmGB_TILE_MODE17 0x0655 ++#define mmGB_TILE_MODE17_BASE_IDX 0 ++#define mmGB_TILE_MODE18 0x0656 ++#define mmGB_TILE_MODE18_BASE_IDX 0 ++#define mmGB_TILE_MODE19 0x0657 ++#define mmGB_TILE_MODE19_BASE_IDX 0 ++#define mmGB_TILE_MODE20 0x0658 ++#define mmGB_TILE_MODE20_BASE_IDX 0 ++#define mmGB_TILE_MODE21 0x0659 ++#define mmGB_TILE_MODE21_BASE_IDX 0 ++#define mmGB_TILE_MODE22 0x065a ++#define mmGB_TILE_MODE22_BASE_IDX 0 ++#define mmGB_TILE_MODE23 0x065b ++#define mmGB_TILE_MODE23_BASE_IDX 0 ++#define mmGB_TILE_MODE24 0x065c ++#define mmGB_TILE_MODE24_BASE_IDX 0 ++#define mmGB_TILE_MODE25 0x065d ++#define mmGB_TILE_MODE25_BASE_IDX 0 ++#define mmGB_TILE_MODE26 0x065e ++#define mmGB_TILE_MODE26_BASE_IDX 0 ++#define mmGB_TILE_MODE27 0x065f ++#define mmGB_TILE_MODE27_BASE_IDX 0 ++#define mmGB_TILE_MODE28 0x0660 ++#define mmGB_TILE_MODE28_BASE_IDX 0 ++#define mmGB_TILE_MODE29 0x0661 ++#define mmGB_TILE_MODE29_BASE_IDX 0 ++#define mmGB_TILE_MODE30 0x0662 ++#define mmGB_TILE_MODE30_BASE_IDX 0 ++#define mmGB_TILE_MODE31 0x0663 ++#define mmGB_TILE_MODE31_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE0 0x0664 ++#define mmGB_MACROTILE_MODE0_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE1 0x0665 ++#define mmGB_MACROTILE_MODE1_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE2 0x0666 ++#define mmGB_MACROTILE_MODE2_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE3 0x0667 ++#define mmGB_MACROTILE_MODE3_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE4 0x0668 ++#define mmGB_MACROTILE_MODE4_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE5 0x0669 ++#define mmGB_MACROTILE_MODE5_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE6 0x066a ++#define mmGB_MACROTILE_MODE6_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE7 0x066b ++#define mmGB_MACROTILE_MODE7_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE8 0x066c ++#define mmGB_MACROTILE_MODE8_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE9 0x066d ++#define mmGB_MACROTILE_MODE9_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE10 0x066e ++#define mmGB_MACROTILE_MODE10_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE11 0x066f ++#define mmGB_MACROTILE_MODE11_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE12 0x0670 ++#define mmGB_MACROTILE_MODE12_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE13 0x0671 ++#define mmGB_MACROTILE_MODE13_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE14 0x0672 ++#define mmGB_MACROTILE_MODE14_BASE_IDX 0 ++#define mmGB_MACROTILE_MODE15 0x0673 ++#define mmGB_MACROTILE_MODE15_BASE_IDX 0 ++#define mmCB_HW_CONTROL 0x0680 ++#define mmCB_HW_CONTROL_BASE_IDX 0 ++#define mmCB_HW_CONTROL_1 0x0681 ++#define mmCB_HW_CONTROL_1_BASE_IDX 0 ++#define mmCB_HW_CONTROL_2 0x0682 ++#define mmCB_HW_CONTROL_2_BASE_IDX 0 ++#define mmCB_HW_CONTROL_3 0x0683 ++#define mmCB_HW_CONTROL_3_BASE_IDX 0 ++#define mmCB_HW_MEM_ARBITER_RD 0x0686 ++#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0 ++#define mmCB_HW_MEM_ARBITER_WR 0x0687 ++#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0 ++#define mmCB_DCC_CONFIG 0x0688 ++#define mmCB_DCC_CONFIG_BASE_IDX 0 ++#define mmGC_USER_RB_REDUNDANCY 0x06de ++#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0 ++#define mmGC_USER_RB_BACKEND_DISABLE 0x06df ++#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 ++ ++ ++// addressBlock: gc_ea_gceadec2 ++// base address: 0x9c00 ++#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x0700 ++#define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++#define mmGCEA_DSM_CNTL 0x0708 ++#define mmGCEA_DSM_CNTL_BASE_IDX 0 ++#define mmGCEA_DSM_CNTLA 0x0709 ++#define mmGCEA_DSM_CNTLA_BASE_IDX 0 ++#define mmGCEA_DSM_CNTLB 0x070a ++#define mmGCEA_DSM_CNTLB_BASE_IDX 0 ++#define mmGCEA_DSM_CNTL2 0x070b ++#define mmGCEA_DSM_CNTL2_BASE_IDX 0 ++#define mmGCEA_DSM_CNTL2A 0x070c ++#define mmGCEA_DSM_CNTL2A_BASE_IDX 0 ++#define mmGCEA_DSM_CNTL2B 0x070d ++#define mmGCEA_DSM_CNTL2B_BASE_IDX 0 ++#define mmGCEA_TCC_XBR_CREDITS 0x070e ++#define mmGCEA_TCC_XBR_CREDITS_BASE_IDX 0 ++#define mmGCEA_TCC_XBR_MAXBURST 0x070f ++#define mmGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 ++#define mmGCEA_PROBE_CNTL 0x0710 ++#define mmGCEA_PROBE_CNTL_BASE_IDX 0 ++#define mmGCEA_PROBE_MAP 0x0711 ++#define mmGCEA_PROBE_MAP_BASE_IDX 0 ++#define mmGCEA_ERR_STATUS 0x0712 ++#define mmGCEA_ERR_STATUS_BASE_IDX 0 ++#define mmGCEA_MISC2 0x0713 ++#define mmGCEA_MISC2_BASE_IDX 0 ++#define mmGCEA_DRAM_BANK_ARB 0x0714 ++#define mmGCEA_DRAM_BANK_ARB_BASE_IDX 0 ++#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 0x0715 ++#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 ++#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 0x0716 ++#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 ++#define mmGCEA_SDP_BACKDOOR_DATACREDITS0 0x0717 ++#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 ++#define mmGCEA_SDP_BACKDOOR_DATACREDITS1 0x0718 ++#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 ++#define mmGCEA_SDP_BACKDOOR_MISCCREDITS 0x0719 ++#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 ++#define mmGCEA_SDP_ENABLE 0x071a ++#define mmGCEA_SDP_ENABLE_BASE_IDX 0 ++ ++ ++// addressBlock: gc_rmi_rmidec ++// base address: 0x9e00 ++#define mmRMI_GENERAL_CNTL 0x0780 ++#define mmRMI_GENERAL_CNTL_BASE_IDX 0 ++#define mmRMI_GENERAL_CNTL1 0x0781 ++#define mmRMI_GENERAL_CNTL1_BASE_IDX 0 ++#define mmRMI_GENERAL_STATUS 0x0782 ++#define mmRMI_GENERAL_STATUS_BASE_IDX 0 ++#define mmRMI_SUBBLOCK_STATUS0 0x0783 ++#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0 ++#define mmRMI_SUBBLOCK_STATUS1 0x0784 ++#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0 ++#define mmRMI_SUBBLOCK_STATUS2 0x0785 ++#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0 ++#define mmRMI_SUBBLOCK_STATUS3 0x0786 ++#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0 ++#define mmRMI_XBAR_CONFIG 0x0787 ++#define mmRMI_XBAR_CONFIG_BASE_IDX 0 ++#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788 ++#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0 ++#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789 ++#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0 ++#define mmRMI_DEMUX_CNTL 0x078a ++#define mmRMI_DEMUX_CNTL_BASE_IDX 0 ++#define mmRMI_UTCL1_CNTL1 0x078b ++#define mmRMI_UTCL1_CNTL1_BASE_IDX 0 ++#define mmRMI_UTCL1_CNTL2 0x078c ++#define mmRMI_UTCL1_CNTL2_BASE_IDX 0 ++#define mmRMI_UTC_UNIT_CONFIG 0x078d ++#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0 ++#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e ++#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0 ++#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f ++#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0 ++#define mmRMI_SCOREBOARD_CNTL 0x0790 ++#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0 ++#define mmRMI_SCOREBOARD_STATUS0 0x0791 ++#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0 ++#define mmRMI_SCOREBOARD_STATUS1 0x0792 ++#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0 ++#define mmRMI_SCOREBOARD_STATUS2 0x0793 ++#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0 ++#define mmRMI_XBAR_ARBITER_CONFIG 0x0794 ++#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0 ++#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795 ++#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0 ++#define mmRMI_CLOCK_CNTRL 0x0796 ++#define mmRMI_CLOCK_CNTRL_BASE_IDX 0 ++#define mmRMI_UTCL1_STATUS 0x0797 ++#define mmRMI_UTCL1_STATUS_BASE_IDX 0 ++#define mmRMI_SPARE 0x079e ++#define mmRMI_SPARE_BASE_IDX 0 ++#define mmRMI_SPARE_1 0x079f ++#define mmRMI_SPARE_1_BASE_IDX 0 ++#define mmRMI_SPARE_2 0x07a0 ++#define mmRMI_SPARE_2_BASE_IDX 0 ++ ++ ++// addressBlock: gc_utcl2_atcl2dec ++// base address: 0xa000 ++#define mmATC_L2_CNTL 0x0800 ++#define mmATC_L2_CNTL_BASE_IDX 0 ++#define mmATC_L2_CNTL2 0x0801 ++#define mmATC_L2_CNTL2_BASE_IDX 0 ++#define mmATC_L2_CACHE_DATA0 0x0804 ++#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 ++#define mmATC_L2_CACHE_DATA1 0x0805 ++#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 ++#define mmATC_L2_CACHE_DATA2 0x0806 ++#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 ++#define mmATC_L2_CNTL3 0x0807 ++#define mmATC_L2_CNTL3_BASE_IDX 0 ++#define mmATC_L2_STATUS 0x0808 ++#define mmATC_L2_STATUS_BASE_IDX 0 ++#define mmATC_L2_STATUS2 0x0809 ++#define mmATC_L2_STATUS2_BASE_IDX 0 ++#define mmATC_L2_MISC_CG 0x080a ++#define mmATC_L2_MISC_CG_BASE_IDX 0 ++#define mmATC_L2_MEM_POWER_LS 0x080b ++#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 ++#define mmATC_L2_CGTT_CLK_CTRL 0x080c ++#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 ++ ++ ++// addressBlock: gc_utcl2_vml2pfdec ++// base address: 0xa100 ++#define mmVM_L2_CNTL 0x0840 ++#define mmVM_L2_CNTL_BASE_IDX 0 ++#define mmVM_L2_CNTL2 0x0841 ++#define mmVM_L2_CNTL2_BASE_IDX 0 ++#define mmVM_L2_CNTL3 0x0842 ++#define mmVM_L2_CNTL3_BASE_IDX 0 ++#define mmVM_L2_STATUS 0x0843 ++#define mmVM_L2_STATUS_BASE_IDX 0 ++#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844 ++#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847 ++#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848 ++#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849 ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b ++#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c ++#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d ++#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 ++#define mmVM_L2_CNTL4 0x0857 ++#define mmVM_L2_CNTL4_BASE_IDX 0 ++#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858 ++#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 ++#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859 ++#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 ++#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a ++#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 ++#define mmVM_L2_CACHE_PARITY_CNTL 0x085b ++#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 ++#define mmVM_L2_CGTT_CLK_CTRL 0x085e ++#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 ++ ++ ++// addressBlock: gc_utcl2_vml2vcdec ++// base address: 0xa200 ++#define mmVM_CONTEXT0_CNTL 0x0880 ++#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT1_CNTL 0x0881 ++#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT2_CNTL 0x0882 ++#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT3_CNTL 0x0883 ++#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT4_CNTL 0x0884 ++#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT5_CNTL 0x0885 ++#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT6_CNTL 0x0886 ++#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT7_CNTL 0x0887 ++#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT8_CNTL 0x0888 ++#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT9_CNTL 0x0889 ++#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT10_CNTL 0x088a ++#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT11_CNTL 0x088b ++#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT12_CNTL 0x088c ++#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT13_CNTL 0x088d ++#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT14_CNTL 0x088e ++#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT15_CNTL 0x088f ++#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXTS_DISABLE 0x0890 ++#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_SEM 0x0891 ++#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_SEM 0x0892 ++#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_SEM 0x0893 ++#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_SEM 0x0894 ++#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_SEM 0x0895 ++#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_SEM 0x0896 ++#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_SEM 0x0897 ++#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_SEM 0x0898 ++#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_SEM 0x0899 ++#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_SEM 0x089a ++#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_SEM 0x089b ++#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_SEM 0x089c ++#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_SEM 0x089d ++#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_SEM 0x089e ++#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_SEM 0x089f ++#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_SEM 0x08a0 ++#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_SEM 0x08a1 ++#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_SEM 0x08a2 ++#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_REQ 0x08a3 ++#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_REQ 0x08a4 ++#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_REQ 0x08a5 ++#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_REQ 0x08a6 ++#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_REQ 0x08a7 ++#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_REQ 0x08a8 ++#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_REQ 0x08a9 ++#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_REQ 0x08aa ++#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_REQ 0x08ab ++#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_REQ 0x08ac ++#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_REQ 0x08ad ++#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_REQ 0x08ae ++#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_REQ 0x08af ++#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_REQ 0x08b0 ++#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_REQ 0x08b1 ++#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_REQ 0x08b2 ++#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_REQ 0x08b3 ++#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_REQ 0x08b4 ++#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_ACK 0x08b5 ++#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_ACK 0x08b6 ++#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_ACK 0x08b7 ++#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_ACK 0x08b8 ++#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_ACK 0x08b9 ++#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_ACK 0x08ba ++#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_ACK 0x08bb ++#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_ACK 0x08bc ++#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_ACK 0x08bd ++#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_ACK 0x08be ++#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_ACK 0x08bf ++#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_ACK 0x08c0 ++#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_ACK 0x08c1 ++#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_ACK 0x08c2 ++#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_ACK 0x08c3 ++#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_ACK 0x08c4 ++#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_ACK 0x08c5 ++#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_ACK 0x08c6 ++#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9 ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0 ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9 ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0 ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9 ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0 ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9 ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900 ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909 ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910 ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919 ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920 ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929 ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930 ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939 ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940 ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949 ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++ ++ ++// addressBlock: gc_utcl2_vmsharedpfdec ++// base address: 0xa590 ++#define mmMC_VM_NB_MMIOBASE 0x0964 ++#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 ++#define mmMC_VM_NB_MMIOLIMIT 0x0965 ++#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 ++#define mmMC_VM_NB_PCI_CTRL 0x0966 ++#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 ++#define mmMC_VM_NB_PCI_ARB 0x0967 ++#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 ++#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968 ++#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 ++#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969 ++#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 ++#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a ++#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 ++#define mmMC_VM_FB_OFFSET 0x096b ++#define mmMC_VM_FB_OFFSET_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 ++#define mmMC_VM_STEERING 0x096e ++#define mmMC_VM_STEERING_BASE_IDX 0 ++#define mmMC_SHARED_VIRT_RESET_REQ 0x096f ++#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmMC_MEM_POWER_LS 0x0970 ++#define mmMC_MEM_POWER_LS_BASE_IDX 0 ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971 ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972 ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 ++#define mmMC_VM_APT_CNTL 0x0973 ++#define mmMC_VM_APT_CNTL_BASE_IDX 0 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 ++#define mmMC_VM_XGMI_LFB_CNTL 0x0977 ++#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 ++#define mmMC_VM_XGMI_LFB_SIZE 0x0978 ++#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 ++ ++ ++// addressBlock: gc_utcl2_vmsharedvcdec ++// base address: 0xa600 ++#define mmMC_VM_FB_LOCATION_BASE 0x0980 ++#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 ++#define mmMC_VM_FB_LOCATION_TOP 0x0981 ++#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 ++#define mmMC_VM_AGP_TOP 0x0982 ++#define mmMC_VM_AGP_TOP_BASE_IDX 0 ++#define mmMC_VM_AGP_BOT 0x0983 ++#define mmMC_VM_AGP_BOT_BASE_IDX 0 ++#define mmMC_VM_AGP_BASE 0x0984 ++#define mmMC_VM_AGP_BASE_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985 ++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986 ++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB_CNTL 0x0987 ++#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: gc_ea_gceadec ++// base address: 0xa800 ++#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00 ++#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01 ++#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02 ++#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03 ++#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x0a04 ++#define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x0a05 ++#define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_LAZY 0x0a06 ++#define mmGCEA_DRAM_RD_LAZY_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_LAZY 0x0a07 ++#define mmGCEA_DRAM_WR_LAZY_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_CAM_CNTL 0x0a08 ++#define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_CAM_CNTL 0x0a09 ++#define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 ++#define mmGCEA_DRAM_PAGE_BURST 0x0a0a ++#define mmGCEA_DRAM_PAGE_BURST_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_PRI_AGE 0x0a0b ++#define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_PRI_AGE 0x0a0c ++#define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_PRI_QUEUING 0x0a0d ++#define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_PRI_QUEUING 0x0a0e ++#define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_PRI_FIXED 0x0a0f ++#define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_PRI_FIXED 0x0a10 ++#define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_PRI_URGENCY 0x0a11 ++#define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_PRI_URGENCY 0x0a12 ++#define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13 ++#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14 ++#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15 ++#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16 ++#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17 ++#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18 ++#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmGCEA_ADDRNORM_BASE_ADDR0 0x0a34 ++#define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0 ++#define mmGCEA_ADDRNORM_LIMIT_ADDR0 0x0a35 ++#define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 ++#define mmGCEA_ADDRNORM_BASE_ADDR1 0x0a36 ++#define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0 ++#define mmGCEA_ADDRNORM_LIMIT_ADDR1 0x0a37 ++#define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 ++#define mmGCEA_ADDRNORM_OFFSET_ADDR1 0x0a38 ++#define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 ++#define mmGCEA_ADDRNORMDRAM_HOLE_CNTL 0x0a43 ++#define mmGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 ++#define mmGCEA_ADDRNORMDRAM_TRICHANNEL_CFG 0x0a45 ++#define mmGCEA_ADDRNORMDRAM_TRICHANNEL_CFG_BASE_IDX 0 ++#define mmGCEA_ADDRDEC_BANK_CFG 0x0a47 ++#define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0 ++#define mmGCEA_ADDRDEC_MISC_CFG 0x0a48 ++#define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 0x0a49 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 0x0a4a ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 0x0a4b ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 0x0a4c ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 0x0a4d ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC 0x0a4e ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 0x0a4f ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 0x0a50 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 0x0a51 ++#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 ++#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a52 ++#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a5d ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a5e ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a5f ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a60 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a61 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a62 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a63 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a64 ++#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a65 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a66 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a67 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a68 ++#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a69 ++#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a6a ++#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a6b ++#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a6c ++#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a6d ++#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a6e ++#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a6f ++#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a70 ++#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_RM_SEL_CS01 0x0a71 ++#define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_RM_SEL_CS23 0x0a72 ++#define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a73 ++#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a74 ++#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a75 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a76 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a77 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a78 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a79 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a7a ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a7b ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a7c ++#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a7d ++#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a7e ++#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a7f ++#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a80 ++#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a81 ++#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a82 ++#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a83 ++#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a84 ++#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a85 ++#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a86 ++#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a87 ++#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a88 ++#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_RM_SEL_CS01 0x0a89 ++#define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_RM_SEL_CS23 0x0a8a ++#define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a8b ++#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a8c ++#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x0ad5 ++#define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x0ad6 ++#define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x0ad7 ++#define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x0ad8 ++#define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmGCEA_IO_RD_COMBINE_FLUSH 0x0ad9 ++#define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 ++#define mmGCEA_IO_WR_COMBINE_FLUSH 0x0ada ++#define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 ++#define mmGCEA_IO_GROUP_BURST 0x0adb ++#define mmGCEA_IO_GROUP_BURST_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_AGE 0x0adc ++#define mmGCEA_IO_RD_PRI_AGE_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_AGE 0x0add ++#define mmGCEA_IO_WR_PRI_AGE_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_QUEUING 0x0ade ++#define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_QUEUING 0x0adf ++#define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_FIXED 0x0ae0 ++#define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_FIXED 0x0ae1 ++#define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_URGENCY 0x0ae2 ++#define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_URGENCY 0x0ae3 ++#define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_URGENCY_MASK 0x0ae4 ++#define mmGCEA_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_URGENCY_MASK 0x0ae5 ++#define mmGCEA_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae6 ++#define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae7 ++#define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae8 ++#define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae9 ++#define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x0aea ++#define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x0aeb ++#define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmGCEA_SDP_ARB_DRAM 0x0aec ++#define mmGCEA_SDP_ARB_DRAM_BASE_IDX 0 ++#define mmGCEA_SDP_ARB_FINAL 0x0aee ++#define mmGCEA_SDP_ARB_FINAL_BASE_IDX 0 ++#define mmGCEA_SDP_DRAM_PRIORITY 0x0aef ++#define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0 ++#define mmGCEA_SDP_IO_PRIORITY 0x0af1 ++#define mmGCEA_SDP_IO_PRIORITY_BASE_IDX 0 ++#define mmGCEA_SDP_CREDITS 0x0af2 ++#define mmGCEA_SDP_CREDITS_BASE_IDX 0 ++#define mmGCEA_SDP_TAG_RESERVE0 0x0af3 ++#define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 ++#define mmGCEA_SDP_TAG_RESERVE1 0x0af4 ++#define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 ++#define mmGCEA_SDP_VCC_RESERVE0 0x0af5 ++#define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 ++#define mmGCEA_SDP_VCC_RESERVE1 0x0af6 ++#define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 ++#define mmGCEA_SDP_VCD_RESERVE0 0x0af7 ++#define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX 0 ++#define mmGCEA_SDP_VCD_RESERVE1 0x0af8 ++#define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX 0 ++#define mmGCEA_SDP_REQ_CNTL 0x0af9 ++#define mmGCEA_SDP_REQ_CNTL_BASE_IDX 0 ++#define mmGCEA_MISC 0x0afa ++#define mmGCEA_MISC_BASE_IDX 0 ++#define mmGCEA_LATENCY_SAMPLING 0x0afb ++#define mmGCEA_LATENCY_SAMPLING_BASE_IDX 0 ++#define mmGCEA_PERFCOUNTER_LO 0x0afc ++#define mmGCEA_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmGCEA_PERFCOUNTER_HI 0x0afd ++#define mmGCEA_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmGCEA_PERFCOUNTER0_CFG 0x0afe ++#define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmGCEA_PERFCOUNTER1_CFG 0x0aff ++#define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 ++ ++ ++// addressBlock: gc_tcdec ++// base address: 0xac00 ++#define mmTCP_INVALIDATE 0x0b00 ++#define mmTCP_INVALIDATE_BASE_IDX 0 ++#define mmTCP_STATUS 0x0b01 ++#define mmTCP_STATUS_BASE_IDX 0 ++#define mmTCP_CNTL 0x0b02 ++#define mmTCP_CNTL_BASE_IDX 0 ++#define mmTCP_CHAN_STEER_LO 0x0b03 ++#define mmTCP_CHAN_STEER_LO_BASE_IDX 0 ++#define mmTCP_CHAN_STEER_HI 0x0b04 ++#define mmTCP_CHAN_STEER_HI_BASE_IDX 0 ++#define mmTCP_ADDR_CONFIG 0x0b05 ++#define mmTCP_ADDR_CONFIG_BASE_IDX 0 ++#define mmTCP_CREDIT 0x0b06 ++#define mmTCP_CREDIT_BASE_IDX 0 ++#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16 ++#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 ++#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a ++#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 ++#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b ++#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0 ++#define mmTC_CFG_L1_STORE_POLICY 0x0b1c ++#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0 ++#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d ++#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0 ++#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e ++#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0 ++#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f ++#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0 ++#define mmTC_CFG_L2_STORE_POLICY1 0x0b20 ++#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0 ++#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21 ++#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0 ++#define mmTC_CFG_L1_VOLATILE 0x0b22 ++#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0 ++#define mmTC_CFG_L2_VOLATILE 0x0b23 ++#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0 ++#define mmTCI_STATUS 0x0b61 ++#define mmTCI_STATUS_BASE_IDX 0 ++#define mmTCI_CNTL_1 0x0b62 ++#define mmTCI_CNTL_1_BASE_IDX 0 ++#define mmTCI_CNTL_2 0x0b63 ++#define mmTCI_CNTL_2_BASE_IDX 0 ++#define mmTCC_CTRL 0x0b80 ++#define mmTCC_CTRL_BASE_IDX 0 ++#define mmTCC_CTRL2 0x0b81 ++#define mmTCC_CTRL2_BASE_IDX 0 ++#define mmTCC_REDUNDANCY 0x0b84 ++#define mmTCC_REDUNDANCY_BASE_IDX 0 ++#define mmTCC_EXE_DISABLE 0x0b85 ++#define mmTCC_EXE_DISABLE_BASE_IDX 0 ++#define mmTCC_DSM_CNTL 0x0b86 ++#define mmTCC_DSM_CNTL_BASE_IDX 0 ++#define mmTCC_DSM_CNTLA 0x0b87 ++#define mmTCC_DSM_CNTLA_BASE_IDX 0 ++#define mmTCC_DSM_CNTL2 0x0b88 ++#define mmTCC_DSM_CNTL2_BASE_IDX 0 ++#define mmTCC_DSM_CNTL2A 0x0b89 ++#define mmTCC_DSM_CNTL2A_BASE_IDX 0 ++#define mmTCC_DSM_CNTL2B 0x0b8a ++#define mmTCC_DSM_CNTL2B_BASE_IDX 0 ++#define mmTCC_WBINVL2 0x0b8b ++#define mmTCC_WBINVL2_BASE_IDX 0 ++#define mmTCC_SOFT_RESET 0x0b8c ++#define mmTCC_SOFT_RESET_BASE_IDX 0 ++#define mmTCA_CTRL 0x0bc0 ++#define mmTCA_CTRL_BASE_IDX 0 ++#define mmTCA_BURST_MASK 0x0bc1 ++#define mmTCA_BURST_MASK_BASE_IDX 0 ++#define mmTCA_BURST_CTRL 0x0bc2 ++#define mmTCA_BURST_CTRL_BASE_IDX 0 ++#define mmTCA_DSM_CNTL 0x0bc3 ++#define mmTCA_DSM_CNTL_BASE_IDX 0 ++#define mmTCA_DSM_CNTL2 0x0bc4 ++#define mmTCA_DSM_CNTL2_BASE_IDX 0 ++ ++ ++// addressBlock: gc_shdec ++// base address: 0xb000 ++#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07 ++#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_LO_PS 0x0c08 ++#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_HI_PS 0x0c09 ++#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a ++#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b ++#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c ++#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d ++#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e ++#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f ++#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10 ++#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11 ++#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12 ++#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13 ++#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14 ++#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15 ++#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16 ++#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17 ++#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18 ++#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19 ++#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a ++#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b ++#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c ++#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d ++#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e ++#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f ++#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20 ++#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21 ++#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22 ++#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23 ++#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24 ++#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25 ++#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26 ++#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27 ++#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28 ++#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29 ++#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a ++#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b ++#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46 ++#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0 ++#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47 ++#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_LO_VS 0x0c48 ++#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_HI_VS 0x0c49 ++#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a ++#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b ++#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c ++#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d ++#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e ++#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f ++#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50 ++#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51 ++#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52 ++#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53 ++#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54 ++#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55 ++#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56 ++#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57 ++#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58 ++#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59 ++#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a ++#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b ++#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c ++#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d ++#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e ++#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f ++#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60 ++#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61 ++#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62 ++#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63 ++#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64 ++#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65 ++#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66 ++#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67 ++#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68 ++#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69 ++#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a ++#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b ++#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c ++#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81 ++#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82 ++#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83 ++#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_LO_ES 0x0c84 ++#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_HI_ES 0x0c85 ++#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87 ++#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_LO_GS 0x0c88 ++#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_HI_GS 0x0c89 ++#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a ++#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b ++#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc ++#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd ++#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce ++#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf ++#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0 ++#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1 ++#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2 ++#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3 ++#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4 ++#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5 ++#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6 ++#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7 ++#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8 ++#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9 ++#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda ++#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb ++#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc ++#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd ++#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde ++#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf ++#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0 ++#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1 ++#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2 ++#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3 ++#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4 ++#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5 ++#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6 ++#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7 ++#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8 ++#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9 ++#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea ++#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb ++#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01 ++#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02 ++#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03 ++#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_LO_LS 0x0d04 ++#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_HI_LS 0x0d05 ++#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07 ++#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_LO_HS 0x0d08 ++#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_HI_HS 0x0d09 ++#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a ++#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 ++#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b ++#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c ++#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d ++#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e ++#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f ++#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10 ++#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11 ++#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12 ++#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13 ++#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14 ++#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15 ++#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16 ++#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17 ++#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18 ++#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19 ++#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a ++#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b ++#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c ++#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d ++#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e ++#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f ++#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20 ++#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21 ++#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22 ++#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23 ++#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24 ++#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25 ++#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26 ++#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27 ++#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28 ++#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29 ++#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a ++#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b ++#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c ++#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d ++#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e ++#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f ++#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50 ++#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51 ++#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52 ++#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53 ++#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54 ++#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55 ++#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56 ++#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57 ++#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58 ++#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59 ++#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a ++#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b ++#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c ++#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d ++#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e ++#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f ++#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60 ++#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61 ++#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62 ++#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63 ++#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64 ++#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65 ++#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66 ++#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67 ++#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68 ++#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69 ++#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a ++#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0 ++#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b ++#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0 ++#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00 ++#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 ++#define mmCOMPUTE_DIM_X 0x0e01 ++#define mmCOMPUTE_DIM_X_BASE_IDX 0 ++#define mmCOMPUTE_DIM_Y 0x0e02 ++#define mmCOMPUTE_DIM_Y_BASE_IDX 0 ++#define mmCOMPUTE_DIM_Z 0x0e03 ++#define mmCOMPUTE_DIM_Z_BASE_IDX 0 ++#define mmCOMPUTE_START_X 0x0e04 ++#define mmCOMPUTE_START_X_BASE_IDX 0 ++#define mmCOMPUTE_START_Y 0x0e05 ++#define mmCOMPUTE_START_Y_BASE_IDX 0 ++#define mmCOMPUTE_START_Z 0x0e06 ++#define mmCOMPUTE_START_Z_BASE_IDX 0 ++#define mmCOMPUTE_NUM_THREAD_X 0x0e07 ++#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0 ++#define mmCOMPUTE_NUM_THREAD_Y 0x0e08 ++#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 ++#define mmCOMPUTE_NUM_THREAD_Z 0x0e09 ++#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 ++#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a ++#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 ++#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b ++#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 ++#define mmCOMPUTE_PGM_LO 0x0e0c ++#define mmCOMPUTE_PGM_LO_BASE_IDX 0 ++#define mmCOMPUTE_PGM_HI 0x0e0d ++#define mmCOMPUTE_PGM_HI_BASE_IDX 0 ++#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e ++#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 ++#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f ++#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 ++#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10 ++#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 ++#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11 ++#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 ++#define mmCOMPUTE_PGM_RSRC1 0x0e12 ++#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0 ++#define mmCOMPUTE_PGM_RSRC2 0x0e13 ++#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0 ++#define mmCOMPUTE_VMID 0x0e14 ++#define mmCOMPUTE_VMID_BASE_IDX 0 ++#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15 ++#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16 ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17 ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 ++#define mmCOMPUTE_TMPRING_SIZE 0x0e18 ++#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0 ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19 ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a ++#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 ++#define mmCOMPUTE_RESTART_X 0x0e1b ++#define mmCOMPUTE_RESTART_X_BASE_IDX 0 ++#define mmCOMPUTE_RESTART_Y 0x0e1c ++#define mmCOMPUTE_RESTART_Y_BASE_IDX 0 ++#define mmCOMPUTE_RESTART_Z 0x0e1d ++#define mmCOMPUTE_RESTART_Z_BASE_IDX 0 ++#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e ++#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 ++#define mmCOMPUTE_MISC_RESERVED 0x0e1f ++#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0 ++#define mmCOMPUTE_DISPATCH_ID 0x0e20 ++#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0 ++#define mmCOMPUTE_THREADGROUP_ID 0x0e21 ++#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0 ++#define mmCOMPUTE_RELAUNCH 0x0e22 ++#define mmCOMPUTE_RELAUNCH_BASE_IDX 0 ++#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23 ++#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 ++#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24 ++#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 ++#define mmCOMPUTE_SHADER_CHKSUM 0x0e25 ++#define mmCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_0 0x0e40 ++#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_1 0x0e41 ++#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_2 0x0e42 ++#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_3 0x0e43 ++#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_4 0x0e44 ++#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_5 0x0e45 ++#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_6 0x0e46 ++#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_7 0x0e47 ++#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_8 0x0e48 ++#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_9 0x0e49 ++#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_10 0x0e4a ++#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_11 0x0e4b ++#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_12 0x0e4c ++#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_13 0x0e4d ++#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_14 0x0e4e ++#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0 ++#define mmCOMPUTE_USER_DATA_15 0x0e4f ++#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0 ++#define mmCOMPUTE_DISPATCH_END 0x0e7e ++#define mmCOMPUTE_DISPATCH_END_BASE_IDX 0 ++#define mmCOMPUTE_NOWHERE 0x0e7f ++#define mmCOMPUTE_NOWHERE_BASE_IDX 0 ++ ++ ++// addressBlock: gc_cppdec ++// base address: 0xc080 ++#define mmCP_DFY_CNTL 0x1020 ++#define mmCP_DFY_CNTL_BASE_IDX 0 ++#define mmCP_DFY_STAT 0x1021 ++#define mmCP_DFY_STAT_BASE_IDX 0 ++#define mmCP_DFY_ADDR_HI 0x1022 ++#define mmCP_DFY_ADDR_HI_BASE_IDX 0 ++#define mmCP_DFY_ADDR_LO 0x1023 ++#define mmCP_DFY_ADDR_LO_BASE_IDX 0 ++#define mmCP_DFY_DATA_0 0x1024 ++#define mmCP_DFY_DATA_0_BASE_IDX 0 ++#define mmCP_DFY_DATA_1 0x1025 ++#define mmCP_DFY_DATA_1_BASE_IDX 0 ++#define mmCP_DFY_DATA_2 0x1026 ++#define mmCP_DFY_DATA_2_BASE_IDX 0 ++#define mmCP_DFY_DATA_3 0x1027 ++#define mmCP_DFY_DATA_3_BASE_IDX 0 ++#define mmCP_DFY_DATA_4 0x1028 ++#define mmCP_DFY_DATA_4_BASE_IDX 0 ++#define mmCP_DFY_DATA_5 0x1029 ++#define mmCP_DFY_DATA_5_BASE_IDX 0 ++#define mmCP_DFY_DATA_6 0x102a ++#define mmCP_DFY_DATA_6_BASE_IDX 0 ++#define mmCP_DFY_DATA_7 0x102b ++#define mmCP_DFY_DATA_7_BASE_IDX 0 ++#define mmCP_DFY_DATA_8 0x102c ++#define mmCP_DFY_DATA_8_BASE_IDX 0 ++#define mmCP_DFY_DATA_9 0x102d ++#define mmCP_DFY_DATA_9_BASE_IDX 0 ++#define mmCP_DFY_DATA_10 0x102e ++#define mmCP_DFY_DATA_10_BASE_IDX 0 ++#define mmCP_DFY_DATA_11 0x102f ++#define mmCP_DFY_DATA_11_BASE_IDX 0 ++#define mmCP_DFY_DATA_12 0x1030 ++#define mmCP_DFY_DATA_12_BASE_IDX 0 ++#define mmCP_DFY_DATA_13 0x1031 ++#define mmCP_DFY_DATA_13_BASE_IDX 0 ++#define mmCP_DFY_DATA_14 0x1032 ++#define mmCP_DFY_DATA_14_BASE_IDX 0 ++#define mmCP_DFY_DATA_15 0x1033 ++#define mmCP_DFY_DATA_15_BASE_IDX 0 ++#define mmCP_DFY_CMD 0x1034 ++#define mmCP_DFY_CMD_BASE_IDX 0 ++#define mmCP_EOPQ_WAIT_TIME 0x1035 ++#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0 ++#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036 ++#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 ++#define mmCPC_INT_INFO 0x1037 ++#define mmCPC_INT_INFO_BASE_IDX 0 ++#define mmCP_VIRT_STATUS 0x1038 ++#define mmCP_VIRT_STATUS_BASE_IDX 0 ++#define mmCPC_INT_ADDR 0x1039 ++#define mmCPC_INT_ADDR_BASE_IDX 0 ++#define mmCPC_INT_PASID 0x103a ++#define mmCPC_INT_PASID_BASE_IDX 0 ++#define mmCP_GFX_ERROR 0x103b ++#define mmCP_GFX_ERROR_BASE_IDX 0 ++#define mmCPG_UTCL1_CNTL 0x103c ++#define mmCPG_UTCL1_CNTL_BASE_IDX 0 ++#define mmCPC_UTCL1_CNTL 0x103d ++#define mmCPC_UTCL1_CNTL_BASE_IDX 0 ++#define mmCPF_UTCL1_CNTL 0x103e ++#define mmCPF_UTCL1_CNTL_BASE_IDX 0 ++#define mmCP_AQL_SMM_STATUS 0x103f ++#define mmCP_AQL_SMM_STATUS_BASE_IDX 0 ++#define mmCP_RB0_BASE 0x1040 ++#define mmCP_RB0_BASE_BASE_IDX 0 ++#define mmCP_RB_BASE 0x1040 ++#define mmCP_RB_BASE_BASE_IDX 0 ++#define mmCP_RB0_CNTL 0x1041 ++#define mmCP_RB0_CNTL_BASE_IDX 0 ++#define mmCP_RB_CNTL 0x1041 ++#define mmCP_RB_CNTL_BASE_IDX 0 ++#define mmCP_RB_RPTR_WR 0x1042 ++#define mmCP_RB_RPTR_WR_BASE_IDX 0 ++#define mmCP_RB0_RPTR_ADDR 0x1043 ++#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0 ++#define mmCP_RB_RPTR_ADDR 0x1043 ++#define mmCP_RB_RPTR_ADDR_BASE_IDX 0 ++#define mmCP_RB0_RPTR_ADDR_HI 0x1044 ++#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmCP_RB_RPTR_ADDR_HI 0x1044 ++#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmCP_RB0_BUFSZ_MASK 0x1045 ++#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0 ++#define mmCP_RB_BUFSZ_MASK 0x1045 ++#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0 ++#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046 ++#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047 ++#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmGC_PRIV_MODE 0x1048 ++#define mmGC_PRIV_MODE_BASE_IDX 0 ++#define mmCP_INT_CNTL 0x1049 ++#define mmCP_INT_CNTL_BASE_IDX 0 ++#define mmCP_INT_STATUS 0x104a ++#define mmCP_INT_STATUS_BASE_IDX 0 ++#define mmCP_DEVICE_ID 0x104b ++#define mmCP_DEVICE_ID_BASE_IDX 0 ++#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c ++#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 ++#define mmCP_RING_PRIORITY_CNTS 0x104c ++#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0 ++#define mmCP_ME0_PIPE0_PRIORITY 0x104d ++#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 ++#define mmCP_RING0_PRIORITY 0x104d ++#define mmCP_RING0_PRIORITY_BASE_IDX 0 ++#define mmCP_ME0_PIPE1_PRIORITY 0x104e ++#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 ++#define mmCP_RING1_PRIORITY 0x104e ++#define mmCP_RING1_PRIORITY_BASE_IDX 0 ++#define mmCP_ME0_PIPE2_PRIORITY 0x104f ++#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 ++#define mmCP_RING2_PRIORITY 0x104f ++#define mmCP_RING2_PRIORITY_BASE_IDX 0 ++#define mmCP_FATAL_ERROR 0x1050 ++#define mmCP_FATAL_ERROR_BASE_IDX 0 ++#define mmCP_RB_VMID 0x1051 ++#define mmCP_RB_VMID_BASE_IDX 0 ++#define mmCP_ME0_PIPE0_VMID 0x1052 ++#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0 ++#define mmCP_ME0_PIPE1_VMID 0x1053 ++#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0 ++#define mmCP_RB0_WPTR 0x1054 ++#define mmCP_RB0_WPTR_BASE_IDX 0 ++#define mmCP_RB_WPTR 0x1054 ++#define mmCP_RB_WPTR_BASE_IDX 0 ++#define mmCP_RB0_WPTR_HI 0x1055 ++#define mmCP_RB0_WPTR_HI_BASE_IDX 0 ++#define mmCP_RB_WPTR_HI 0x1055 ++#define mmCP_RB_WPTR_HI_BASE_IDX 0 ++#define mmCP_RB1_WPTR 0x1056 ++#define mmCP_RB1_WPTR_BASE_IDX 0 ++#define mmCP_RB1_WPTR_HI 0x1057 ++#define mmCP_RB1_WPTR_HI_BASE_IDX 0 ++#define mmCP_RB2_WPTR 0x1058 ++#define mmCP_RB2_WPTR_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL 0x1059 ++#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a ++#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b ++#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 ++#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c ++#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 ++#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d ++#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 ++#define mmCPG_UTCL1_ERROR 0x105e ++#define mmCPG_UTCL1_ERROR_BASE_IDX 0 ++#define mmCPC_UTCL1_ERROR 0x105f ++#define mmCPC_UTCL1_ERROR_BASE_IDX 0 ++#define mmCP_RB1_BASE 0x1060 ++#define mmCP_RB1_BASE_BASE_IDX 0 ++#define mmCP_RB1_CNTL 0x1061 ++#define mmCP_RB1_CNTL_BASE_IDX 0 ++#define mmCP_RB1_RPTR_ADDR 0x1062 ++#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0 ++#define mmCP_RB1_RPTR_ADDR_HI 0x1063 ++#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmCP_RB2_BASE 0x1065 ++#define mmCP_RB2_BASE_BASE_IDX 0 ++#define mmCP_RB2_CNTL 0x1066 ++#define mmCP_RB2_CNTL_BASE_IDX 0 ++#define mmCP_RB2_RPTR_ADDR 0x1067 ++#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0 ++#define mmCP_RB2_RPTR_ADDR_HI 0x1068 ++#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmCP_RB0_ACTIVE 0x1069 ++#define mmCP_RB0_ACTIVE_BASE_IDX 0 ++#define mmCP_RB_ACTIVE 0x1069 ++#define mmCP_RB_ACTIVE_BASE_IDX 0 ++#define mmCP_INT_CNTL_RING0 0x106a ++#define mmCP_INT_CNTL_RING0_BASE_IDX 0 ++#define mmCP_INT_CNTL_RING1 0x106b ++#define mmCP_INT_CNTL_RING1_BASE_IDX 0 ++#define mmCP_INT_CNTL_RING2 0x106c ++#define mmCP_INT_CNTL_RING2_BASE_IDX 0 ++#define mmCP_INT_STATUS_RING0 0x106d ++#define mmCP_INT_STATUS_RING0_BASE_IDX 0 ++#define mmCP_INT_STATUS_RING1 0x106e ++#define mmCP_INT_STATUS_RING1_BASE_IDX 0 ++#define mmCP_INT_STATUS_RING2 0x106f ++#define mmCP_INT_STATUS_RING2_BASE_IDX 0 ++#define mmCP_PWR_CNTL 0x1078 ++#define mmCP_PWR_CNTL_BASE_IDX 0 ++#define mmCP_MEM_SLP_CNTL 0x1079 ++#define mmCP_MEM_SLP_CNTL_BASE_IDX 0 ++#define mmCP_ECC_FIRSTOCCURRENCE 0x107a ++#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 ++#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b ++#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 ++#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c ++#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 ++#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d ++#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 ++#define mmCP_PQ_WPTR_POLL_CNTL 0x1083 ++#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084 ++#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 ++#define mmCP_ME1_PIPE0_INT_CNTL 0x1085 ++#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME1_PIPE1_INT_CNTL 0x1086 ++#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME1_PIPE2_INT_CNTL 0x1087 ++#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME1_PIPE3_INT_CNTL 0x1088 ++#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME2_PIPE0_INT_CNTL 0x1089 ++#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME2_PIPE1_INT_CNTL 0x108a ++#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME2_PIPE2_INT_CNTL 0x108b ++#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME2_PIPE3_INT_CNTL 0x108c ++#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 ++#define mmCP_ME1_PIPE0_INT_STATUS 0x108d ++#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME1_PIPE1_INT_STATUS 0x108e ++#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME1_PIPE2_INT_STATUS 0x108f ++#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME1_PIPE3_INT_STATUS 0x1090 ++#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME2_PIPE0_INT_STATUS 0x1091 ++#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME2_PIPE1_INT_STATUS 0x1092 ++#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME2_PIPE2_INT_STATUS 0x1093 ++#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME2_PIPE3_INT_STATUS 0x1094 ++#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 ++#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099 ++#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 ++#define mmCP_ME1_PIPE0_PRIORITY 0x109a ++#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 ++#define mmCP_ME1_PIPE1_PRIORITY 0x109b ++#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 ++#define mmCP_ME1_PIPE2_PRIORITY 0x109c ++#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 ++#define mmCP_ME1_PIPE3_PRIORITY 0x109d ++#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 ++#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e ++#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 ++#define mmCP_ME2_PIPE0_PRIORITY 0x109f ++#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 ++#define mmCP_ME2_PIPE1_PRIORITY 0x10a0 ++#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 ++#define mmCP_ME2_PIPE2_PRIORITY 0x10a1 ++#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 ++#define mmCP_ME2_PIPE3_PRIORITY 0x10a2 ++#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 ++#define mmCP_CE_PRGRM_CNTR_START 0x10a3 ++#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0 ++#define mmCP_PFP_PRGRM_CNTR_START 0x10a4 ++#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 ++#define mmCP_ME_PRGRM_CNTR_START 0x10a5 ++#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0 ++#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6 ++#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 ++#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7 ++#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 ++#define mmCP_CE_INTR_ROUTINE_START 0x10a8 ++#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0 ++#define mmCP_PFP_INTR_ROUTINE_START 0x10a9 ++#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 ++#define mmCP_ME_INTR_ROUTINE_START 0x10aa ++#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0 ++#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab ++#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 ++#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac ++#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 ++#define mmCP_CONTEXT_CNTL 0x10ad ++#define mmCP_CONTEXT_CNTL_BASE_IDX 0 ++#define mmCP_MAX_CONTEXT 0x10ae ++#define mmCP_MAX_CONTEXT_BASE_IDX 0 ++#define mmCP_IQ_WAIT_TIME1 0x10af ++#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0 ++#define mmCP_IQ_WAIT_TIME2 0x10b0 ++#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0 ++#define mmCP_RB0_BASE_HI 0x10b1 ++#define mmCP_RB0_BASE_HI_BASE_IDX 0 ++#define mmCP_RB1_BASE_HI 0x10b2 ++#define mmCP_RB1_BASE_HI_BASE_IDX 0 ++#define mmCP_VMID_RESET 0x10b3 ++#define mmCP_VMID_RESET_BASE_IDX 0 ++#define mmCPC_INT_CNTL 0x10b4 ++#define mmCPC_INT_CNTL_BASE_IDX 0 ++#define mmCPC_INT_STATUS 0x10b5 ++#define mmCPC_INT_STATUS_BASE_IDX 0 ++#define mmCP_VMID_PREEMPT 0x10b6 ++#define mmCP_VMID_PREEMPT_BASE_IDX 0 ++#define mmCPC_INT_CNTX_ID 0x10b7 ++#define mmCPC_INT_CNTX_ID_BASE_IDX 0 ++#define mmCP_PQ_STATUS 0x10b8 ++#define mmCP_PQ_STATUS_BASE_IDX 0 ++#define mmCP_CPC_IC_BASE_LO 0x10b9 ++#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0 ++#define mmCP_CPC_IC_BASE_HI 0x10ba ++#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0 ++#define mmCP_CPC_IC_BASE_CNTL 0x10bb ++#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0 ++#define mmCP_CPC_IC_OP_CNTL 0x10bc ++#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0 ++#define mmCP_MEC1_F32_INT_DIS 0x10bd ++#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0 ++#define mmCP_MEC2_F32_INT_DIS 0x10be ++#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0 ++#define mmCP_VMID_STATUS 0x10bf ++#define mmCP_VMID_STATUS_BASE_IDX 0 ++ ++ ++// addressBlock: gc_cppdec2 ++// base address: 0xc600 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187 ++#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 ++#define mmCP_RB_DOORBELL_CLEAR 0x1188 ++#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0 ++#define mmCP_GFX_MQD_CONTROL 0x11a0 ++#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0 ++#define mmCP_GFX_MQD_BASE_ADDR 0x11a1 ++#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 ++#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2 ++#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 ++#define mmCP_RB_STATUS 0x11a3 ++#define mmCP_RB_STATUS_BASE_IDX 0 ++#define mmCPG_UTCL1_STATUS 0x11b4 ++#define mmCPG_UTCL1_STATUS_BASE_IDX 0 ++#define mmCPC_UTCL1_STATUS 0x11b5 ++#define mmCPC_UTCL1_STATUS_BASE_IDX 0 ++#define mmCPF_UTCL1_STATUS 0x11b6 ++#define mmCPF_UTCL1_STATUS_BASE_IDX 0 ++#define mmCP_SD_CNTL 0x11b7 ++#define mmCP_SD_CNTL_BASE_IDX 0 ++#define mmCP_SOFT_RESET_CNTL 0x11b9 ++#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0 ++#define mmCP_CPC_GFX_CNTL 0x11ba ++#define mmCP_CPC_GFX_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: gc_spipdec ++// base address: 0xc700 ++#define mmSPI_ARB_PRIORITY 0x11c0 ++#define mmSPI_ARB_PRIORITY_BASE_IDX 0 ++#define mmSPI_ARB_CYCLES_0 0x11c1 ++#define mmSPI_ARB_CYCLES_0_BASE_IDX 0 ++#define mmSPI_ARB_CYCLES_1 0x11c2 ++#define mmSPI_ARB_CYCLES_1_BASE_IDX 0 ++#define mmSPI_CDBG_SYS_GFX 0x11c3 ++#define mmSPI_CDBG_SYS_GFX_BASE_IDX 0 ++#define mmSPI_CDBG_SYS_HP3D 0x11c4 ++#define mmSPI_CDBG_SYS_HP3D_BASE_IDX 0 ++#define mmSPI_CDBG_SYS_CS0 0x11c5 ++#define mmSPI_CDBG_SYS_CS0_BASE_IDX 0 ++#define mmSPI_CDBG_SYS_CS1 0x11c6 ++#define mmSPI_CDBG_SYS_CS1_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7 ++#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8 ++#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9 ++#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca ++#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb ++#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc ++#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd ++#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce ++#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf ++#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 ++#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0 ++#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 ++#define mmSPI_GDBG_WAVE_CNTL 0x11d1 ++#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 ++#define mmSPI_GDBG_TRAP_CONFIG 0x11d2 ++#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 ++#define mmSPI_GDBG_TRAP_MASK 0x11d3 ++#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 ++#define mmSPI_GDBG_WAVE_CNTL2 0x11d4 ++#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 ++#define mmSPI_GDBG_WAVE_CNTL3 0x11d5 ++#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 ++#define mmSPI_GDBG_TRAP_DATA0 0x11d8 ++#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 ++#define mmSPI_GDBG_TRAP_DATA1 0x11d9 ++#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 ++#define mmSPI_COMPUTE_QUEUE_RESET 0x11db ++#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc ++#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd ++#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de ++#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df ++#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0 ++#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1 ++#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2 ++#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3 ++#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4 ++#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5 ++#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea ++#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb ++#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec ++#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed ++#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee ++#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef ++#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0 ++#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1 ++#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4 ++#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5 ++#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6 ++#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7 ++#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa ++#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0 ++#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb ++#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0 ++#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc ++#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 ++#define mmSPI_ARB_CNTL_0 0x11fd ++#define mmSPI_ARB_CNTL_0_BASE_IDX 0 ++ ++ ++// addressBlock: gc_cpphqddec ++// base address: 0xc800 ++#define mmCP_HQD_GFX_CONTROL 0x123e ++#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_GFX_STATUS 0x123f ++#define mmCP_HQD_GFX_STATUS_BASE_IDX 0 ++#define mmCP_HPD_ROQ_OFFSETS 0x1240 ++#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0 ++#define mmCP_HPD_STATUS0 0x1241 ++#define mmCP_HPD_STATUS0_BASE_IDX 0 ++#define mmCP_HPD_UTCL1_CNTL 0x1242 ++#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0 ++#define mmCP_HPD_UTCL1_ERROR 0x1243 ++#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0 ++#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244 ++#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 ++#define mmCP_MQD_BASE_ADDR 0x1245 ++#define mmCP_MQD_BASE_ADDR_BASE_IDX 0 ++#define mmCP_MQD_BASE_ADDR_HI 0x1246 ++#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0 ++#define mmCP_HQD_ACTIVE 0x1247 ++#define mmCP_HQD_ACTIVE_BASE_IDX 0 ++#define mmCP_HQD_VMID 0x1248 ++#define mmCP_HQD_VMID_BASE_IDX 0 ++#define mmCP_HQD_PERSISTENT_STATE 0x1249 ++#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0 ++#define mmCP_HQD_PIPE_PRIORITY 0x124a ++#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0 ++#define mmCP_HQD_QUEUE_PRIORITY 0x124b ++#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 ++#define mmCP_HQD_QUANTUM 0x124c ++#define mmCP_HQD_QUANTUM_BASE_IDX 0 ++#define mmCP_HQD_PQ_BASE 0x124d ++#define mmCP_HQD_PQ_BASE_BASE_IDX 0 ++#define mmCP_HQD_PQ_BASE_HI 0x124e ++#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0 ++#define mmCP_HQD_PQ_RPTR 0x124f ++#define mmCP_HQD_PQ_RPTR_BASE_IDX 0 ++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250 ++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 ++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251 ++#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 ++#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252 ++#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 ++#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253 ++#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 ++#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_PQ_CONTROL 0x1256 ++#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_IB_BASE_ADDR 0x1257 ++#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0 ++#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258 ++#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 ++#define mmCP_HQD_IB_RPTR 0x1259 ++#define mmCP_HQD_IB_RPTR_BASE_IDX 0 ++#define mmCP_HQD_IB_CONTROL 0x125a ++#define mmCP_HQD_IB_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_IQ_TIMER 0x125b ++#define mmCP_HQD_IQ_TIMER_BASE_IDX 0 ++#define mmCP_HQD_IQ_RPTR 0x125c ++#define mmCP_HQD_IQ_RPTR_BASE_IDX 0 ++#define mmCP_HQD_DEQUEUE_REQUEST 0x125d ++#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 ++#define mmCP_HQD_DMA_OFFLOAD 0x125e ++#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0 ++#define mmCP_HQD_OFFLOAD 0x125e ++#define mmCP_HQD_OFFLOAD_BASE_IDX 0 ++#define mmCP_HQD_SEMA_CMD 0x125f ++#define mmCP_HQD_SEMA_CMD_BASE_IDX 0 ++#define mmCP_HQD_MSG_TYPE 0x1260 ++#define mmCP_HQD_MSG_TYPE_BASE_IDX 0 ++#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261 ++#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 ++#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262 ++#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 ++#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263 ++#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 ++#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264 ++#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 ++#define mmCP_HQD_HQ_SCHEDULER0 0x1265 ++#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 ++#define mmCP_HQD_HQ_STATUS0 0x1265 ++#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0 ++#define mmCP_HQD_HQ_CONTROL0 0x1266 ++#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0 ++#define mmCP_HQD_HQ_SCHEDULER1 0x1266 ++#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 ++#define mmCP_MQD_CONTROL 0x1267 ++#define mmCP_MQD_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_HQ_STATUS1 0x1268 ++#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0 ++#define mmCP_HQD_HQ_CONTROL1 0x1269 ++#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0 ++#define mmCP_HQD_EOP_BASE_ADDR 0x126a ++#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 ++#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b ++#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 ++#define mmCP_HQD_EOP_CONTROL 0x126c ++#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_EOP_RPTR 0x126d ++#define mmCP_HQD_EOP_RPTR_BASE_IDX 0 ++#define mmCP_HQD_EOP_WPTR 0x126e ++#define mmCP_HQD_EOP_WPTR_BASE_IDX 0 ++#define mmCP_HQD_EOP_EVENTS 0x126f ++#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0 ++#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270 ++#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 ++#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271 ++#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 ++#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272 ++#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273 ++#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 ++#define mmCP_HQD_CNTL_STACK_SIZE 0x1274 ++#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 ++#define mmCP_HQD_WG_STATE_OFFSET 0x1275 ++#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 ++#define mmCP_HQD_CTX_SAVE_SIZE 0x1276 ++#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 ++#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277 ++#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 ++#define mmCP_HQD_ERROR 0x1278 ++#define mmCP_HQD_ERROR_BASE_IDX 0 ++#define mmCP_HQD_EOP_WPTR_MEM 0x1279 ++#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 ++#define mmCP_HQD_AQL_CONTROL 0x127a ++#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0 ++#define mmCP_HQD_PQ_WPTR_LO 0x127b ++#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0 ++#define mmCP_HQD_PQ_WPTR_HI 0x127c ++#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0 ++ ++ ++// addressBlock: gc_didtdec ++// base address: 0xca00 ++#define mmDIDT_IND_INDEX 0x1280 ++#define mmDIDT_IND_INDEX_BASE_IDX 0 ++#define mmDIDT_IND_DATA 0x1281 ++#define mmDIDT_IND_DATA_BASE_IDX 0 ++#define mmDIDT_INDEX_AUTO_INCR_EN 0x1282 ++#define mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0 ++ ++ ++// addressBlock: gc_gccacdec ++// base address: 0xca10 ++#define mmGC_CAC_CTRL_1 0x1284 ++#define mmGC_CAC_CTRL_1_BASE_IDX 0 ++#define mmGC_CAC_CTRL_2 0x1285 ++#define mmGC_CAC_CTRL_2_BASE_IDX 0 ++#define mmGC_CAC_INDEX_AUTO_INCR_EN 0x1286 ++#define mmGC_CAC_INDEX_AUTO_INCR_EN_BASE_IDX 0 ++#define mmGC_CAC_AGGR_LOWER 0x1287 ++#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0 ++#define mmGC_CAC_AGGR_UPPER 0x1288 ++#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0 ++#define mmPCC_PERF_COUNTER 0x128a ++#define mmPCC_PERF_COUNTER_BASE_IDX 0 ++#define mmGC_CAC_SOFT_CTRL 0x128d ++#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0 ++#define mmGC_DIDT_CTRL0 0x128e ++#define mmGC_DIDT_CTRL0_BASE_IDX 0 ++#define mmGC_DIDT_CTRL1 0x128f ++#define mmGC_DIDT_CTRL1_BASE_IDX 0 ++#define mmGC_DIDT_CTRL2 0x1290 ++#define mmGC_DIDT_CTRL2_BASE_IDX 0 ++#define mmGC_DIDT_WEIGHT 0x1291 ++#define mmGC_DIDT_WEIGHT_BASE_IDX 0 ++#define mmGC_EDC_CTRL 0x1293 ++#define mmGC_EDC_CTRL_BASE_IDX 0 ++#define mmGC_EDC_THRESHOLD 0x1294 ++#define mmGC_EDC_THRESHOLD_BASE_IDX 0 ++#define mmGC_DIDT_DROOP_CTRL 0x1298 ++#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0 ++#define mmGC_DIDT_DROOP_CTRL1 0x1299 ++#define mmGC_DIDT_DROOP_CTRL1_BASE_IDX 0 ++#define mmGC_EDC_DROOP_CTRL 0x129a ++#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0 ++#define mmGC_THROTTLE_CTRL 0x129b ++#define mmGC_THROTTLE_CTRL_BASE_IDX 0 ++#define mmGC_CAC_IND_INDEX 0x129c ++#define mmGC_CAC_IND_INDEX_BASE_IDX 0 ++#define mmGC_CAC_IND_DATA 0x129d ++#define mmGC_CAC_IND_DATA_BASE_IDX 0 ++#define mmSE_CAC_IND_INDEX 0x129e ++#define mmSE_CAC_IND_INDEX_BASE_IDX 0 ++#define mmSE_CAC_IND_DATA 0x129f ++#define mmSE_CAC_IND_DATA_BASE_IDX 0 ++ ++ ++// addressBlock: gc_tcpdec ++// base address: 0xca80 ++#define mmTCP_WATCH0_ADDR_H 0x12a0 ++#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0 ++#define mmTCP_WATCH0_ADDR_L 0x12a1 ++#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0 ++#define mmTCP_WATCH0_CNTL 0x12a2 ++#define mmTCP_WATCH0_CNTL_BASE_IDX 0 ++#define mmTCP_WATCH1_ADDR_H 0x12a3 ++#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0 ++#define mmTCP_WATCH1_ADDR_L 0x12a4 ++#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0 ++#define mmTCP_WATCH1_CNTL 0x12a5 ++#define mmTCP_WATCH1_CNTL_BASE_IDX 0 ++#define mmTCP_WATCH2_ADDR_H 0x12a6 ++#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0 ++#define mmTCP_WATCH2_ADDR_L 0x12a7 ++#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0 ++#define mmTCP_WATCH2_CNTL 0x12a8 ++#define mmTCP_WATCH2_CNTL_BASE_IDX 0 ++#define mmTCP_WATCH3_ADDR_H 0x12a9 ++#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0 ++#define mmTCP_WATCH3_ADDR_L 0x12aa ++#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 ++#define mmTCP_WATCH3_CNTL 0x12ab ++#define mmTCP_WATCH3_CNTL_BASE_IDX 0 ++#define mmTCP_GATCL1_CNTL 0x12b0 ++#define mmTCP_GATCL1_CNTL_BASE_IDX 0 ++#define mmTCP_GATCL1_DSM_CNTL 0x12b2 ++#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0 ++#define mmTCP_CNTL2 0x12b4 ++#define mmTCP_CNTL2_BASE_IDX 0 ++#define mmTCP_UTCL1_CNTL1 0x12b5 ++#define mmTCP_UTCL1_CNTL1_BASE_IDX 0 ++#define mmTCP_UTCL1_CNTL2 0x12b6 ++#define mmTCP_UTCL1_CNTL2_BASE_IDX 0 ++#define mmTCP_UTCL1_STATUS 0x12b7 ++#define mmTCP_UTCL1_STATUS_BASE_IDX 0 ++#define mmTCP_PERFCOUNTER_FILTER 0x12b9 ++#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 ++#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba ++#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0 ++ ++ ++// addressBlock: gc_gdspdec ++// base address: 0xcc00 ++#define mmGDS_VMID0_BASE 0x1300 ++#define mmGDS_VMID0_BASE_BASE_IDX 0 ++#define mmGDS_VMID0_SIZE 0x1301 ++#define mmGDS_VMID0_SIZE_BASE_IDX 0 ++#define mmGDS_VMID1_BASE 0x1302 ++#define mmGDS_VMID1_BASE_BASE_IDX 0 ++#define mmGDS_VMID1_SIZE 0x1303 ++#define mmGDS_VMID1_SIZE_BASE_IDX 0 ++#define mmGDS_VMID2_BASE 0x1304 ++#define mmGDS_VMID2_BASE_BASE_IDX 0 ++#define mmGDS_VMID2_SIZE 0x1305 ++#define mmGDS_VMID2_SIZE_BASE_IDX 0 ++#define mmGDS_VMID3_BASE 0x1306 ++#define mmGDS_VMID3_BASE_BASE_IDX 0 ++#define mmGDS_VMID3_SIZE 0x1307 ++#define mmGDS_VMID3_SIZE_BASE_IDX 0 ++#define mmGDS_VMID4_BASE 0x1308 ++#define mmGDS_VMID4_BASE_BASE_IDX 0 ++#define mmGDS_VMID4_SIZE 0x1309 ++#define mmGDS_VMID4_SIZE_BASE_IDX 0 ++#define mmGDS_VMID5_BASE 0x130a ++#define mmGDS_VMID5_BASE_BASE_IDX 0 ++#define mmGDS_VMID5_SIZE 0x130b ++#define mmGDS_VMID5_SIZE_BASE_IDX 0 ++#define mmGDS_VMID6_BASE 0x130c ++#define mmGDS_VMID6_BASE_BASE_IDX 0 ++#define mmGDS_VMID6_SIZE 0x130d ++#define mmGDS_VMID6_SIZE_BASE_IDX 0 ++#define mmGDS_VMID7_BASE 0x130e ++#define mmGDS_VMID7_BASE_BASE_IDX 0 ++#define mmGDS_VMID7_SIZE 0x130f ++#define mmGDS_VMID7_SIZE_BASE_IDX 0 ++#define mmGDS_VMID8_BASE 0x1310 ++#define mmGDS_VMID8_BASE_BASE_IDX 0 ++#define mmGDS_VMID8_SIZE 0x1311 ++#define mmGDS_VMID8_SIZE_BASE_IDX 0 ++#define mmGDS_VMID9_BASE 0x1312 ++#define mmGDS_VMID9_BASE_BASE_IDX 0 ++#define mmGDS_VMID9_SIZE 0x1313 ++#define mmGDS_VMID9_SIZE_BASE_IDX 0 ++#define mmGDS_VMID10_BASE 0x1314 ++#define mmGDS_VMID10_BASE_BASE_IDX 0 ++#define mmGDS_VMID10_SIZE 0x1315 ++#define mmGDS_VMID10_SIZE_BASE_IDX 0 ++#define mmGDS_VMID11_BASE 0x1316 ++#define mmGDS_VMID11_BASE_BASE_IDX 0 ++#define mmGDS_VMID11_SIZE 0x1317 ++#define mmGDS_VMID11_SIZE_BASE_IDX 0 ++#define mmGDS_VMID12_BASE 0x1318 ++#define mmGDS_VMID12_BASE_BASE_IDX 0 ++#define mmGDS_VMID12_SIZE 0x1319 ++#define mmGDS_VMID12_SIZE_BASE_IDX 0 ++#define mmGDS_VMID13_BASE 0x131a ++#define mmGDS_VMID13_BASE_BASE_IDX 0 ++#define mmGDS_VMID13_SIZE 0x131b ++#define mmGDS_VMID13_SIZE_BASE_IDX 0 ++#define mmGDS_VMID14_BASE 0x131c ++#define mmGDS_VMID14_BASE_BASE_IDX 0 ++#define mmGDS_VMID14_SIZE 0x131d ++#define mmGDS_VMID14_SIZE_BASE_IDX 0 ++#define mmGDS_VMID15_BASE 0x131e ++#define mmGDS_VMID15_BASE_BASE_IDX 0 ++#define mmGDS_VMID15_SIZE 0x131f ++#define mmGDS_VMID15_SIZE_BASE_IDX 0 ++#define mmGDS_GWS_VMID0 0x1320 ++#define mmGDS_GWS_VMID0_BASE_IDX 0 ++#define mmGDS_GWS_VMID1 0x1321 ++#define mmGDS_GWS_VMID1_BASE_IDX 0 ++#define mmGDS_GWS_VMID2 0x1322 ++#define mmGDS_GWS_VMID2_BASE_IDX 0 ++#define mmGDS_GWS_VMID3 0x1323 ++#define mmGDS_GWS_VMID3_BASE_IDX 0 ++#define mmGDS_GWS_VMID4 0x1324 ++#define mmGDS_GWS_VMID4_BASE_IDX 0 ++#define mmGDS_GWS_VMID5 0x1325 ++#define mmGDS_GWS_VMID5_BASE_IDX 0 ++#define mmGDS_GWS_VMID6 0x1326 ++#define mmGDS_GWS_VMID6_BASE_IDX 0 ++#define mmGDS_GWS_VMID7 0x1327 ++#define mmGDS_GWS_VMID7_BASE_IDX 0 ++#define mmGDS_GWS_VMID8 0x1328 ++#define mmGDS_GWS_VMID8_BASE_IDX 0 ++#define mmGDS_GWS_VMID9 0x1329 ++#define mmGDS_GWS_VMID9_BASE_IDX 0 ++#define mmGDS_GWS_VMID10 0x132a ++#define mmGDS_GWS_VMID10_BASE_IDX 0 ++#define mmGDS_GWS_VMID11 0x132b ++#define mmGDS_GWS_VMID11_BASE_IDX 0 ++#define mmGDS_GWS_VMID12 0x132c ++#define mmGDS_GWS_VMID12_BASE_IDX 0 ++#define mmGDS_GWS_VMID13 0x132d ++#define mmGDS_GWS_VMID13_BASE_IDX 0 ++#define mmGDS_GWS_VMID14 0x132e ++#define mmGDS_GWS_VMID14_BASE_IDX 0 ++#define mmGDS_GWS_VMID15 0x132f ++#define mmGDS_GWS_VMID15_BASE_IDX 0 ++#define mmGDS_OA_VMID0 0x1330 ++#define mmGDS_OA_VMID0_BASE_IDX 0 ++#define mmGDS_OA_VMID1 0x1331 ++#define mmGDS_OA_VMID1_BASE_IDX 0 ++#define mmGDS_OA_VMID2 0x1332 ++#define mmGDS_OA_VMID2_BASE_IDX 0 ++#define mmGDS_OA_VMID3 0x1333 ++#define mmGDS_OA_VMID3_BASE_IDX 0 ++#define mmGDS_OA_VMID4 0x1334 ++#define mmGDS_OA_VMID4_BASE_IDX 0 ++#define mmGDS_OA_VMID5 0x1335 ++#define mmGDS_OA_VMID5_BASE_IDX 0 ++#define mmGDS_OA_VMID6 0x1336 ++#define mmGDS_OA_VMID6_BASE_IDX 0 ++#define mmGDS_OA_VMID7 0x1337 ++#define mmGDS_OA_VMID7_BASE_IDX 0 ++#define mmGDS_OA_VMID8 0x1338 ++#define mmGDS_OA_VMID8_BASE_IDX 0 ++#define mmGDS_OA_VMID9 0x1339 ++#define mmGDS_OA_VMID9_BASE_IDX 0 ++#define mmGDS_OA_VMID10 0x133a ++#define mmGDS_OA_VMID10_BASE_IDX 0 ++#define mmGDS_OA_VMID11 0x133b ++#define mmGDS_OA_VMID11_BASE_IDX 0 ++#define mmGDS_OA_VMID12 0x133c ++#define mmGDS_OA_VMID12_BASE_IDX 0 ++#define mmGDS_OA_VMID13 0x133d ++#define mmGDS_OA_VMID13_BASE_IDX 0 ++#define mmGDS_OA_VMID14 0x133e ++#define mmGDS_OA_VMID14_BASE_IDX 0 ++#define mmGDS_OA_VMID15 0x133f ++#define mmGDS_OA_VMID15_BASE_IDX 0 ++#define mmGDS_GWS_RESET0 0x1344 ++#define mmGDS_GWS_RESET0_BASE_IDX 0 ++#define mmGDS_GWS_RESET1 0x1345 ++#define mmGDS_GWS_RESET1_BASE_IDX 0 ++#define mmGDS_GWS_RESOURCE_RESET 0x1346 ++#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0 ++#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348 ++#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 ++#define mmGDS_OA_RESET_MASK 0x1349 ++#define mmGDS_OA_RESET_MASK_BASE_IDX 0 ++#define mmGDS_OA_RESET 0x134a ++#define mmGDS_OA_RESET_BASE_IDX 0 ++#define mmGDS_ENHANCE 0x134b ++#define mmGDS_ENHANCE_BASE_IDX 0 ++#define mmGDS_OA_CGPG_RESTORE 0x134c ++#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0 ++#define mmGDS_CS_CTXSW_STATUS 0x134d ++#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0 ++#define mmGDS_CS_CTXSW_CNT0 0x134e ++#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_CS_CTXSW_CNT1 0x134f ++#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_CS_CTXSW_CNT2 0x1350 ++#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_CS_CTXSW_CNT3 0x1351 ++#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_GFX_CTXSW_STATUS 0x1352 ++#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0 ++#define mmGDS_VS_CTXSW_CNT0 0x1353 ++#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_VS_CTXSW_CNT1 0x1354 ++#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_VS_CTXSW_CNT2 0x1355 ++#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_VS_CTXSW_CNT3 0x1356 ++#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS0_CTXSW_CNT0 0x1357 ++#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS0_CTXSW_CNT1 0x1358 ++#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS0_CTXSW_CNT2 0x1359 ++#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS0_CTXSW_CNT3 0x135a ++#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS1_CTXSW_CNT0 0x135b ++#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS1_CTXSW_CNT1 0x135c ++#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS1_CTXSW_CNT2 0x135d ++#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS1_CTXSW_CNT3 0x135e ++#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS2_CTXSW_CNT0 0x135f ++#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS2_CTXSW_CNT1 0x1360 ++#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS2_CTXSW_CNT2 0x1361 ++#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS2_CTXSW_CNT3 0x1362 ++#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS3_CTXSW_CNT0 0x1363 ++#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS3_CTXSW_CNT1 0x1364 ++#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS3_CTXSW_CNT2 0x1365 ++#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS3_CTXSW_CNT3 0x1366 ++#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS4_CTXSW_CNT0 0x1367 ++#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS4_CTXSW_CNT1 0x1368 ++#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS4_CTXSW_CNT2 0x1369 ++#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS4_CTXSW_CNT3 0x136a ++#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS5_CTXSW_CNT0 0x136b ++#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS5_CTXSW_CNT1 0x136c ++#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS5_CTXSW_CNT2 0x136d ++#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS5_CTXSW_CNT3 0x136e ++#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS6_CTXSW_CNT0 0x136f ++#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS6_CTXSW_CNT1 0x1370 ++#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS6_CTXSW_CNT2 0x1371 ++#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS6_CTXSW_CNT3 0x1372 ++#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_PS7_CTXSW_CNT0 0x1373 ++#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_PS7_CTXSW_CNT1 0x1374 ++#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_PS7_CTXSW_CNT2 0x1375 ++#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_PS7_CTXSW_CNT3 0x1376 ++#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0 ++#define mmGDS_GS_CTXSW_CNT0 0x1377 ++#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0 ++#define mmGDS_GS_CTXSW_CNT1 0x1378 ++#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0 ++#define mmGDS_GS_CTXSW_CNT2 0x1379 ++#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0 ++#define mmGDS_GS_CTXSW_CNT3 0x137a ++#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0 ++ ++ ++// addressBlock: gc_rasdec ++// base address: 0xce00 ++#define mmRAS_SIGNATURE_CONTROL 0x1380 ++#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0 ++#define mmRAS_SIGNATURE_MASK 0x1381 ++#define mmRAS_SIGNATURE_MASK_BASE_IDX 0 ++#define mmRAS_SX_SIGNATURE0 0x1382 ++#define mmRAS_SX_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_SX_SIGNATURE1 0x1383 ++#define mmRAS_SX_SIGNATURE1_BASE_IDX 0 ++#define mmRAS_SX_SIGNATURE2 0x1384 ++#define mmRAS_SX_SIGNATURE2_BASE_IDX 0 ++#define mmRAS_SX_SIGNATURE3 0x1385 ++#define mmRAS_SX_SIGNATURE3_BASE_IDX 0 ++#define mmRAS_DB_SIGNATURE0 0x138b ++#define mmRAS_DB_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_PA_SIGNATURE0 0x138c ++#define mmRAS_PA_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_VGT_SIGNATURE0 0x138d ++#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_SQ_SIGNATURE0 0x138e ++#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE0 0x138f ++#define mmRAS_SC_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE1 0x1390 ++#define mmRAS_SC_SIGNATURE1_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE2 0x1391 ++#define mmRAS_SC_SIGNATURE2_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE3 0x1392 ++#define mmRAS_SC_SIGNATURE3_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE4 0x1393 ++#define mmRAS_SC_SIGNATURE4_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE5 0x1394 ++#define mmRAS_SC_SIGNATURE5_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE6 0x1395 ++#define mmRAS_SC_SIGNATURE6_BASE_IDX 0 ++#define mmRAS_SC_SIGNATURE7 0x1396 ++#define mmRAS_SC_SIGNATURE7_BASE_IDX 0 ++#define mmRAS_IA_SIGNATURE0 0x1397 ++#define mmRAS_IA_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_IA_SIGNATURE1 0x1398 ++#define mmRAS_IA_SIGNATURE1_BASE_IDX 0 ++#define mmRAS_SPI_SIGNATURE0 0x1399 ++#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_SPI_SIGNATURE1 0x139a ++#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0 ++#define mmRAS_TA_SIGNATURE0 0x139b ++#define mmRAS_TA_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_TD_SIGNATURE0 0x139c ++#define mmRAS_TD_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_CB_SIGNATURE0 0x139d ++#define mmRAS_CB_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_BCI_SIGNATURE0 0x139e ++#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0 ++#define mmRAS_BCI_SIGNATURE1 0x139f ++#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0 ++#define mmRAS_TA_SIGNATURE1 0x13a0 ++#define mmRAS_TA_SIGNATURE1_BASE_IDX 0 ++ ++ ++// addressBlock: gc_gfxdec0 ++// base address: 0x28000 ++#define mmDB_RENDER_CONTROL 0x0000 ++#define mmDB_RENDER_CONTROL_BASE_IDX 1 ++#define mmDB_COUNT_CONTROL 0x0001 ++#define mmDB_COUNT_CONTROL_BASE_IDX 1 ++#define mmDB_DEPTH_VIEW 0x0002 ++#define mmDB_DEPTH_VIEW_BASE_IDX 1 ++#define mmDB_RENDER_OVERRIDE 0x0003 ++#define mmDB_RENDER_OVERRIDE_BASE_IDX 1 ++#define mmDB_RENDER_OVERRIDE2 0x0004 ++#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1 ++#define mmDB_HTILE_DATA_BASE 0x0005 ++#define mmDB_HTILE_DATA_BASE_BASE_IDX 1 ++#define mmDB_HTILE_DATA_BASE_HI 0x0006 ++#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1 ++#define mmDB_DEPTH_SIZE 0x0007 ++#define mmDB_DEPTH_SIZE_BASE_IDX 1 ++#define mmDB_DEPTH_BOUNDS_MIN 0x0008 ++#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 ++#define mmDB_DEPTH_BOUNDS_MAX 0x0009 ++#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 ++#define mmDB_STENCIL_CLEAR 0x000a ++#define mmDB_STENCIL_CLEAR_BASE_IDX 1 ++#define mmDB_DEPTH_CLEAR 0x000b ++#define mmDB_DEPTH_CLEAR_BASE_IDX 1 ++#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c ++#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 ++#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d ++#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 ++#define mmDB_Z_INFO 0x000e ++#define mmDB_Z_INFO_BASE_IDX 1 ++#define mmDB_STENCIL_INFO 0x000f ++#define mmDB_STENCIL_INFO_BASE_IDX 1 ++#define mmDB_Z_READ_BASE 0x0010 ++#define mmDB_Z_READ_BASE_BASE_IDX 1 ++#define mmDB_Z_READ_BASE_HI 0x0011 ++#define mmDB_Z_READ_BASE_HI_BASE_IDX 1 ++#define mmDB_STENCIL_READ_BASE 0x0012 ++#define mmDB_STENCIL_READ_BASE_BASE_IDX 1 ++#define mmDB_STENCIL_READ_BASE_HI 0x0013 ++#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1 ++#define mmDB_Z_WRITE_BASE 0x0014 ++#define mmDB_Z_WRITE_BASE_BASE_IDX 1 ++#define mmDB_Z_WRITE_BASE_HI 0x0015 ++#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1 ++#define mmDB_STENCIL_WRITE_BASE 0x0016 ++#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1 ++#define mmDB_STENCIL_WRITE_BASE_HI 0x0017 ++#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 ++#define mmDB_DFSM_CONTROL 0x0018 ++#define mmDB_DFSM_CONTROL_BASE_IDX 1 ++#define mmDB_Z_INFO2 0x001a ++#define mmDB_Z_INFO2_BASE_IDX 1 ++#define mmDB_STENCIL_INFO2 0x001b ++#define mmDB_STENCIL_INFO2_BASE_IDX 1 ++#define mmTA_BC_BASE_ADDR 0x0020 ++#define mmTA_BC_BASE_ADDR_BASE_IDX 1 ++#define mmTA_BC_BASE_ADDR_HI 0x0021 ++#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_HI_0 0x007a ++#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_HI_1 0x007b ++#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_HI_2 0x007c ++#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_HI_3 0x007d ++#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_2 0x007e ++#define mmCOHER_DEST_BASE_2_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_3 0x007f ++#define mmCOHER_DEST_BASE_3_BASE_IDX 1 ++#define mmPA_SC_WINDOW_OFFSET 0x0080 ++#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1 ++#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081 ++#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 ++#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082 ++#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_RULE 0x0083 ++#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_0_TL 0x0084 ++#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_0_BR 0x0085 ++#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_1_TL 0x0086 ++#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_1_BR 0x0087 ++#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_2_TL 0x0088 ++#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_2_BR 0x0089 ++#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_3_TL 0x008a ++#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1 ++#define mmPA_SC_CLIPRECT_3_BR 0x008b ++#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1 ++#define mmPA_SC_EDGERULE 0x008c ++#define mmPA_SC_EDGERULE_BASE_IDX 1 ++#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d ++#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 ++#define mmCB_TARGET_MASK 0x008e ++#define mmCB_TARGET_MASK_BASE_IDX 1 ++#define mmCB_SHADER_MASK 0x008f ++#define mmCB_SHADER_MASK_BASE_IDX 1 ++#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090 ++#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 ++#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091 ++#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_0 0x0092 ++#define mmCOHER_DEST_BASE_0_BASE_IDX 1 ++#define mmCOHER_DEST_BASE_1 0x0093 ++#define mmCOHER_DEST_BASE_1_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094 ++#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095 ++#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096 ++#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097 ++#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098 ++#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099 ++#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a ++#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b ++#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c ++#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d ++#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e ++#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f ++#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0 ++#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1 ++#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2 ++#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3 ++#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4 ++#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5 ++#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6 ++#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7 ++#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8 ++#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9 ++#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa ++#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab ++#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac ++#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad ++#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae ++#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af ++#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0 ++#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1 ++#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2 ++#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 ++#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3 ++#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_0 0x00b4 ++#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_0 0x00b5 ++#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_1 0x00b6 ++#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_1 0x00b7 ++#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_2 0x00b8 ++#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_2 0x00b9 ++#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_3 0x00ba ++#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_3 0x00bb ++#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_4 0x00bc ++#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_4 0x00bd ++#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_5 0x00be ++#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_5 0x00bf ++#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_6 0x00c0 ++#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_6 0x00c1 ++#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_7 0x00c2 ++#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_7 0x00c3 ++#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_8 0x00c4 ++#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_8 0x00c5 ++#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_9 0x00c6 ++#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_9 0x00c7 ++#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_10 0x00c8 ++#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_10 0x00c9 ++#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_11 0x00ca ++#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_11 0x00cb ++#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_12 0x00cc ++#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_12 0x00cd ++#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_13 0x00ce ++#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_13 0x00cf ++#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_14 0x00d0 ++#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_14 0x00d1 ++#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMIN_15 0x00d2 ++#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1 ++#define mmPA_SC_VPORT_ZMAX_15 0x00d3 ++#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1 ++#define mmPA_SC_RASTER_CONFIG 0x00d4 ++#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1 ++#define mmPA_SC_RASTER_CONFIG_1 0x00d5 ++#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1 ++#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 ++#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 ++#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7 ++#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 ++#define mmCP_PERFMON_CNTX_CNTL 0x00d8 ++#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1 ++#define mmCP_PIPEID 0x00d9 ++#define mmCP_PIPEID_BASE_IDX 1 ++#define mmCP_RINGID 0x00d9 ++#define mmCP_RINGID_BASE_IDX 1 ++#define mmCP_VMID 0x00da ++#define mmCP_VMID_BASE_IDX 1 ++#define mmPA_SC_RIGHT_VERT_GRID 0x00e8 ++#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 ++#define mmPA_SC_LEFT_VERT_GRID 0x00e9 ++#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 ++#define mmPA_SC_HORIZ_GRID 0x00ea ++#define mmPA_SC_HORIZ_GRID_BASE_IDX 1 ++#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 ++#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 ++#define mmCB_BLEND_RED 0x0105 ++#define mmCB_BLEND_RED_BASE_IDX 1 ++#define mmCB_BLEND_GREEN 0x0106 ++#define mmCB_BLEND_GREEN_BASE_IDX 1 ++#define mmCB_BLEND_BLUE 0x0107 ++#define mmCB_BLEND_BLUE_BASE_IDX 1 ++#define mmCB_BLEND_ALPHA 0x0108 ++#define mmCB_BLEND_ALPHA_BASE_IDX 1 ++#define mmCB_DCC_CONTROL 0x0109 ++#define mmCB_DCC_CONTROL_BASE_IDX 1 ++#define mmDB_STENCIL_CONTROL 0x010b ++#define mmDB_STENCIL_CONTROL_BASE_IDX 1 ++#define mmDB_STENCILREFMASK 0x010c ++#define mmDB_STENCILREFMASK_BASE_IDX 1 ++#define mmDB_STENCILREFMASK_BF 0x010d ++#define mmDB_STENCILREFMASK_BF_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE 0x010f ++#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET 0x0110 ++#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE 0x0111 ++#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET 0x0112 ++#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE 0x0113 ++#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET 0x0114 ++#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_1 0x0115 ++#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_1 0x0116 ++#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_1 0x0117 ++#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_1 0x0118 ++#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_1 0x0119 ++#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_1 0x011a ++#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_2 0x011b ++#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_2 0x011c ++#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_2 0x011d ++#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_2 0x011e ++#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_2 0x011f ++#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_2 0x0120 ++#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_3 0x0121 ++#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_3 0x0122 ++#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_3 0x0123 ++#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_3 0x0124 ++#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_3 0x0125 ++#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_3 0x0126 ++#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_4 0x0127 ++#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_4 0x0128 ++#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_4 0x0129 ++#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_4 0x012a ++#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_4 0x012b ++#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_4 0x012c ++#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_5 0x012d ++#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_5 0x012e ++#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_5 0x012f ++#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_5 0x0130 ++#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_5 0x0131 ++#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_5 0x0132 ++#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_6 0x0133 ++#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_6 0x0134 ++#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_6 0x0135 ++#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_6 0x0136 ++#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_6 0x0137 ++#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_6 0x0138 ++#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_7 0x0139 ++#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_7 0x013a ++#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_7 0x013b ++#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_7 0x013c ++#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_7 0x013d ++#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_7 0x013e ++#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_8 0x013f ++#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_8 0x0140 ++#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_8 0x0141 ++#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_8 0x0142 ++#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_8 0x0143 ++#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_8 0x0144 ++#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_9 0x0145 ++#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_9 0x0146 ++#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_9 0x0147 ++#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_9 0x0148 ++#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_9 0x0149 ++#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_9 0x014a ++#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_10 0x014b ++#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_10 0x014c ++#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_10 0x014d ++#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_10 0x014e ++#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_10 0x014f ++#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_10 0x0150 ++#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_11 0x0151 ++#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_11 0x0152 ++#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_11 0x0153 ++#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_11 0x0154 ++#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_11 0x0155 ++#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_11 0x0156 ++#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_12 0x0157 ++#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_12 0x0158 ++#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_12 0x0159 ++#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_12 0x015a ++#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_12 0x015b ++#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_12 0x015c ++#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_13 0x015d ++#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_13 0x015e ++#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_13 0x015f ++#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_13 0x0160 ++#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_13 0x0161 ++#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_13 0x0162 ++#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_14 0x0163 ++#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_14 0x0164 ++#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_14 0x0165 ++#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_14 0x0166 ++#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_14 0x0167 ++#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_14 0x0168 ++#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 ++#define mmPA_CL_VPORT_XSCALE_15 0x0169 ++#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1 ++#define mmPA_CL_VPORT_XOFFSET_15 0x016a ++#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 ++#define mmPA_CL_VPORT_YSCALE_15 0x016b ++#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1 ++#define mmPA_CL_VPORT_YOFFSET_15 0x016c ++#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZSCALE_15 0x016d ++#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 ++#define mmPA_CL_VPORT_ZOFFSET_15 0x016e ++#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 ++#define mmPA_CL_UCP_0_X 0x016f ++#define mmPA_CL_UCP_0_X_BASE_IDX 1 ++#define mmPA_CL_UCP_0_Y 0x0170 ++#define mmPA_CL_UCP_0_Y_BASE_IDX 1 ++#define mmPA_CL_UCP_0_Z 0x0171 ++#define mmPA_CL_UCP_0_Z_BASE_IDX 1 ++#define mmPA_CL_UCP_0_W 0x0172 ++#define mmPA_CL_UCP_0_W_BASE_IDX 1 ++#define mmPA_CL_UCP_1_X 0x0173 ++#define mmPA_CL_UCP_1_X_BASE_IDX 1 ++#define mmPA_CL_UCP_1_Y 0x0174 ++#define mmPA_CL_UCP_1_Y_BASE_IDX 1 ++#define mmPA_CL_UCP_1_Z 0x0175 ++#define mmPA_CL_UCP_1_Z_BASE_IDX 1 ++#define mmPA_CL_UCP_1_W 0x0176 ++#define mmPA_CL_UCP_1_W_BASE_IDX 1 ++#define mmPA_CL_UCP_2_X 0x0177 ++#define mmPA_CL_UCP_2_X_BASE_IDX 1 ++#define mmPA_CL_UCP_2_Y 0x0178 ++#define mmPA_CL_UCP_2_Y_BASE_IDX 1 ++#define mmPA_CL_UCP_2_Z 0x0179 ++#define mmPA_CL_UCP_2_Z_BASE_IDX 1 ++#define mmPA_CL_UCP_2_W 0x017a ++#define mmPA_CL_UCP_2_W_BASE_IDX 1 ++#define mmPA_CL_UCP_3_X 0x017b ++#define mmPA_CL_UCP_3_X_BASE_IDX 1 ++#define mmPA_CL_UCP_3_Y 0x017c ++#define mmPA_CL_UCP_3_Y_BASE_IDX 1 ++#define mmPA_CL_UCP_3_Z 0x017d ++#define mmPA_CL_UCP_3_Z_BASE_IDX 1 ++#define mmPA_CL_UCP_3_W 0x017e ++#define mmPA_CL_UCP_3_W_BASE_IDX 1 ++#define mmPA_CL_UCP_4_X 0x017f ++#define mmPA_CL_UCP_4_X_BASE_IDX 1 ++#define mmPA_CL_UCP_4_Y 0x0180 ++#define mmPA_CL_UCP_4_Y_BASE_IDX 1 ++#define mmPA_CL_UCP_4_Z 0x0181 ++#define mmPA_CL_UCP_4_Z_BASE_IDX 1 ++#define mmPA_CL_UCP_4_W 0x0182 ++#define mmPA_CL_UCP_4_W_BASE_IDX 1 ++#define mmPA_CL_UCP_5_X 0x0183 ++#define mmPA_CL_UCP_5_X_BASE_IDX 1 ++#define mmPA_CL_UCP_5_Y 0x0184 ++#define mmPA_CL_UCP_5_Y_BASE_IDX 1 ++#define mmPA_CL_UCP_5_Z 0x0185 ++#define mmPA_CL_UCP_5_Z_BASE_IDX 1 ++#define mmPA_CL_UCP_5_W 0x0186 ++#define mmPA_CL_UCP_5_W_BASE_IDX 1 ++#define mmPA_CL_PROG_NEAR_CLIP_Z 0x0187 ++#define mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_0 0x0191 ++#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_1 0x0192 ++#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_2 0x0193 ++#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_3 0x0194 ++#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_4 0x0195 ++#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_5 0x0196 ++#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_6 0x0197 ++#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_7 0x0198 ++#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_8 0x0199 ++#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_9 0x019a ++#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_10 0x019b ++#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_11 0x019c ++#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_12 0x019d ++#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_13 0x019e ++#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_14 0x019f ++#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_15 0x01a0 ++#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_16 0x01a1 ++#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_17 0x01a2 ++#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_18 0x01a3 ++#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_19 0x01a4 ++#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_20 0x01a5 ++#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_21 0x01a6 ++#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_22 0x01a7 ++#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_23 0x01a8 ++#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_24 0x01a9 ++#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_25 0x01aa ++#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_26 0x01ab ++#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_27 0x01ac ++#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_28 0x01ad ++#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_29 0x01ae ++#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_30 0x01af ++#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1 ++#define mmSPI_PS_INPUT_CNTL_31 0x01b0 ++#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1 ++#define mmSPI_VS_OUT_CONFIG 0x01b1 ++#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1 ++#define mmSPI_PS_INPUT_ENA 0x01b3 ++#define mmSPI_PS_INPUT_ENA_BASE_IDX 1 ++#define mmSPI_PS_INPUT_ADDR 0x01b4 ++#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1 ++#define mmSPI_INTERP_CONTROL_0 0x01b5 ++#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1 ++#define mmSPI_PS_IN_CONTROL 0x01b6 ++#define mmSPI_PS_IN_CONTROL_BASE_IDX 1 ++#define mmSPI_BARYC_CNTL 0x01b8 ++#define mmSPI_BARYC_CNTL_BASE_IDX 1 ++#define mmSPI_TMPRING_SIZE 0x01ba ++#define mmSPI_TMPRING_SIZE_BASE_IDX 1 ++#define mmSPI_SHADER_POS_FORMAT 0x01c3 ++#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1 ++#define mmSPI_SHADER_Z_FORMAT 0x01c4 ++#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1 ++#define mmSPI_SHADER_COL_FORMAT 0x01c5 ++#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1 ++#define mmSX_PS_DOWNCONVERT 0x01d5 ++#define mmSX_PS_DOWNCONVERT_BASE_IDX 1 ++#define mmSX_BLEND_OPT_EPSILON 0x01d6 ++#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1 ++#define mmSX_BLEND_OPT_CONTROL 0x01d7 ++#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1 ++#define mmSX_MRT0_BLEND_OPT 0x01d8 ++#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1 ++#define mmSX_MRT1_BLEND_OPT 0x01d9 ++#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1 ++#define mmSX_MRT2_BLEND_OPT 0x01da ++#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1 ++#define mmSX_MRT3_BLEND_OPT 0x01db ++#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1 ++#define mmSX_MRT4_BLEND_OPT 0x01dc ++#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1 ++#define mmSX_MRT5_BLEND_OPT 0x01dd ++#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1 ++#define mmSX_MRT6_BLEND_OPT 0x01de ++#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1 ++#define mmSX_MRT7_BLEND_OPT 0x01df ++#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1 ++#define mmCB_BLEND0_CONTROL 0x01e0 ++#define mmCB_BLEND0_CONTROL_BASE_IDX 1 ++#define mmCB_BLEND1_CONTROL 0x01e1 ++#define mmCB_BLEND1_CONTROL_BASE_IDX 1 ++#define mmCB_BLEND2_CONTROL 0x01e2 ++#define mmCB_BLEND2_CONTROL_BASE_IDX 1 ++#define mmCB_BLEND3_CONTROL 0x01e3 ++#define mmCB_BLEND3_CONTROL_BASE_IDX 1 ++#define mmCB_BLEND4_CONTROL 0x01e4 ++#define mmCB_BLEND4_CONTROL_BASE_IDX 1 ++#define mmCB_BLEND5_CONTROL 0x01e5 ++#define mmCB_BLEND5_CONTROL_BASE_IDX 1 ++#define mmCB_BLEND6_CONTROL 0x01e6 ++#define mmCB_BLEND6_CONTROL_BASE_IDX 1 ++#define mmCB_BLEND7_CONTROL 0x01e7 ++#define mmCB_BLEND7_CONTROL_BASE_IDX 1 ++#define mmCB_MRT0_EPITCH 0x01e8 ++#define mmCB_MRT0_EPITCH_BASE_IDX 1 ++#define mmCB_MRT1_EPITCH 0x01e9 ++#define mmCB_MRT1_EPITCH_BASE_IDX 1 ++#define mmCB_MRT2_EPITCH 0x01ea ++#define mmCB_MRT2_EPITCH_BASE_IDX 1 ++#define mmCB_MRT3_EPITCH 0x01eb ++#define mmCB_MRT3_EPITCH_BASE_IDX 1 ++#define mmCB_MRT4_EPITCH 0x01ec ++#define mmCB_MRT4_EPITCH_BASE_IDX 1 ++#define mmCB_MRT5_EPITCH 0x01ed ++#define mmCB_MRT5_EPITCH_BASE_IDX 1 ++#define mmCB_MRT6_EPITCH 0x01ee ++#define mmCB_MRT6_EPITCH_BASE_IDX 1 ++#define mmCB_MRT7_EPITCH 0x01ef ++#define mmCB_MRT7_EPITCH_BASE_IDX 1 ++#define mmCS_COPY_STATE 0x01f3 ++#define mmCS_COPY_STATE_BASE_IDX 1 ++#define mmGFX_COPY_STATE 0x01f4 ++#define mmGFX_COPY_STATE_BASE_IDX 1 ++#define mmPA_CL_POINT_X_RAD 0x01f5 ++#define mmPA_CL_POINT_X_RAD_BASE_IDX 1 ++#define mmPA_CL_POINT_Y_RAD 0x01f6 ++#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1 ++#define mmPA_CL_POINT_SIZE 0x01f7 ++#define mmPA_CL_POINT_SIZE_BASE_IDX 1 ++#define mmPA_CL_POINT_CULL_RAD 0x01f8 ++#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1 ++#define mmVGT_DMA_BASE_HI 0x01f9 ++#define mmVGT_DMA_BASE_HI_BASE_IDX 1 ++#define mmVGT_DMA_BASE 0x01fa ++#define mmVGT_DMA_BASE_BASE_IDX 1 ++#define mmVGT_DRAW_INITIATOR 0x01fc ++#define mmVGT_DRAW_INITIATOR_BASE_IDX 1 ++#define mmVGT_IMMED_DATA 0x01fd ++#define mmVGT_IMMED_DATA_BASE_IDX 1 ++#define mmVGT_EVENT_ADDRESS_REG 0x01fe ++#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1 ++#define mmDB_DEPTH_CONTROL 0x0200 ++#define mmDB_DEPTH_CONTROL_BASE_IDX 1 ++#define mmDB_EQAA 0x0201 ++#define mmDB_EQAA_BASE_IDX 1 ++#define mmCB_COLOR_CONTROL 0x0202 ++#define mmCB_COLOR_CONTROL_BASE_IDX 1 ++#define mmDB_SHADER_CONTROL 0x0203 ++#define mmDB_SHADER_CONTROL_BASE_IDX 1 ++#define mmPA_CL_CLIP_CNTL 0x0204 ++#define mmPA_CL_CLIP_CNTL_BASE_IDX 1 ++#define mmPA_SU_SC_MODE_CNTL 0x0205 ++#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1 ++#define mmPA_CL_VTE_CNTL 0x0206 ++#define mmPA_CL_VTE_CNTL_BASE_IDX 1 ++#define mmPA_CL_VS_OUT_CNTL 0x0207 ++#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1 ++#define mmPA_CL_NANINF_CNTL 0x0208 ++#define mmPA_CL_NANINF_CNTL_BASE_IDX 1 ++#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209 ++#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 ++#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a ++#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 ++#define mmPA_SU_PRIM_FILTER_CNTL 0x020b ++#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 ++#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c ++#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 ++#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d ++#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 ++#define mmPA_CL_NGG_CNTL 0x020e ++#define mmPA_CL_NGG_CNTL_BASE_IDX 1 ++#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f ++#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 ++#define mmPA_STEREO_CNTL 0x0210 ++#define mmPA_STEREO_CNTL_BASE_IDX 1 ++#define mmPA_SU_POINT_SIZE 0x0280 ++#define mmPA_SU_POINT_SIZE_BASE_IDX 1 ++#define mmPA_SU_POINT_MINMAX 0x0281 ++#define mmPA_SU_POINT_MINMAX_BASE_IDX 1 ++#define mmPA_SU_LINE_CNTL 0x0282 ++#define mmPA_SU_LINE_CNTL_BASE_IDX 1 ++#define mmPA_SC_LINE_STIPPLE 0x0283 ++#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1 ++#define mmVGT_OUTPUT_PATH_CNTL 0x0284 ++#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 ++#define mmVGT_HOS_CNTL 0x0285 ++#define mmVGT_HOS_CNTL_BASE_IDX 1 ++#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286 ++#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 ++#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287 ++#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 ++#define mmVGT_HOS_REUSE_DEPTH 0x0288 ++#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1 ++#define mmVGT_GROUP_PRIM_TYPE 0x0289 ++#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1 ++#define mmVGT_GROUP_FIRST_DECR 0x028a ++#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1 ++#define mmVGT_GROUP_DECR 0x028b ++#define mmVGT_GROUP_DECR_BASE_IDX 1 ++#define mmVGT_GROUP_VECT_0_CNTL 0x028c ++#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 ++#define mmVGT_GROUP_VECT_1_CNTL 0x028d ++#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 ++#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e ++#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 ++#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f ++#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 ++#define mmVGT_GS_MODE 0x0290 ++#define mmVGT_GS_MODE_BASE_IDX 1 ++#define mmVGT_GS_ONCHIP_CNTL 0x0291 ++#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1 ++#define mmPA_SC_MODE_CNTL_0 0x0292 ++#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1 ++#define mmPA_SC_MODE_CNTL_1 0x0293 ++#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1 ++#define mmVGT_ENHANCE 0x0294 ++#define mmVGT_ENHANCE_BASE_IDX 1 ++#define mmVGT_GS_PER_ES 0x0295 ++#define mmVGT_GS_PER_ES_BASE_IDX 1 ++#define mmVGT_ES_PER_GS 0x0296 ++#define mmVGT_ES_PER_GS_BASE_IDX 1 ++#define mmVGT_GS_PER_VS 0x0297 ++#define mmVGT_GS_PER_VS_BASE_IDX 1 ++#define mmVGT_GSVS_RING_OFFSET_1 0x0298 ++#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 ++#define mmVGT_GSVS_RING_OFFSET_2 0x0299 ++#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 ++#define mmVGT_GSVS_RING_OFFSET_3 0x029a ++#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 ++#define mmVGT_GS_OUT_PRIM_TYPE 0x029b ++#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 ++#define mmIA_ENHANCE 0x029c ++#define mmIA_ENHANCE_BASE_IDX 1 ++#define mmVGT_DMA_SIZE 0x029d ++#define mmVGT_DMA_SIZE_BASE_IDX 1 ++#define mmVGT_DMA_MAX_SIZE 0x029e ++#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1 ++#define mmVGT_DMA_INDEX_TYPE 0x029f ++#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1 ++#define mmWD_ENHANCE 0x02a0 ++#define mmWD_ENHANCE_BASE_IDX 1 ++#define mmVGT_PRIMITIVEID_EN 0x02a1 ++#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1 ++#define mmVGT_DMA_NUM_INSTANCES 0x02a2 ++#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1 ++#define mmVGT_PRIMITIVEID_RESET 0x02a3 ++#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1 ++#define mmVGT_EVENT_INITIATOR 0x02a4 ++#define mmVGT_EVENT_INITIATOR_BASE_IDX 1 ++#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5 ++#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 ++#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 ++#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 ++#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 ++#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 ++#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 ++#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 ++#define mmIA_MULTI_VGT_PARAM_BC 0x02aa ++#define mmIA_MULTI_VGT_PARAM_BC_BASE_IDX 1 ++#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab ++#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 ++#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac ++#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 ++#define mmVGT_REUSE_OFF 0x02ad ++#define mmVGT_REUSE_OFF_BASE_IDX 1 ++#define mmVGT_VTX_CNT_EN 0x02ae ++#define mmVGT_VTX_CNT_EN_BASE_IDX 1 ++#define mmDB_HTILE_SURFACE 0x02af ++#define mmDB_HTILE_SURFACE_BASE_IDX 1 ++#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0 ++#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 ++#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1 ++#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 ++#define mmDB_PRELOAD_CONTROL 0x02b2 ++#define mmDB_PRELOAD_CONTROL_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4 ++#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 ++#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5 ++#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7 ++#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8 ++#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 ++#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9 ++#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb ++#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc ++#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 ++#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd ++#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf ++#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0 ++#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 ++#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1 ++#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3 ++#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 ++#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca ++#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 ++#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb ++#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 ++#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc ++#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 ++#define mmVGT_GS_MAX_VERT_OUT 0x02ce ++#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1 ++#define mmVGT_TESS_DISTRIBUTION 0x02d4 ++#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1 ++#define mmVGT_SHADER_STAGES_EN 0x02d5 ++#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1 ++#define mmVGT_LS_HS_CONFIG 0x02d6 ++#define mmVGT_LS_HS_CONFIG_BASE_IDX 1 ++#define mmVGT_GS_VERT_ITEMSIZE 0x02d7 ++#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 ++#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8 ++#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 ++#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9 ++#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 ++#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da ++#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 ++#define mmVGT_TF_PARAM 0x02db ++#define mmVGT_TF_PARAM_BASE_IDX 1 ++#define mmDB_ALPHA_TO_MASK 0x02dc ++#define mmDB_ALPHA_TO_MASK_BASE_IDX 1 ++#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd ++#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 ++#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de ++#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 ++#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df ++#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 ++#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 ++#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 ++#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 ++#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 ++#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 ++#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 ++#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 ++#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 ++#define mmVGT_GS_INSTANCE_CNT 0x02e4 ++#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1 ++#define mmVGT_STRMOUT_CONFIG 0x02e5 ++#define mmVGT_STRMOUT_CONFIG_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_CONFIG 0x02e6 ++#define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 ++#define mmVGT_DMA_EVENT_INITIATOR 0x02e7 ++#define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 ++#define mmPA_SC_CENTROID_PRIORITY_0 0x02f5 ++#define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 ++#define mmPA_SC_CENTROID_PRIORITY_1 0x02f6 ++#define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 ++#define mmPA_SC_LINE_CNTL 0x02f7 ++#define mmPA_SC_LINE_CNTL_BASE_IDX 1 ++#define mmPA_SC_AA_CONFIG 0x02f8 ++#define mmPA_SC_AA_CONFIG_BASE_IDX 1 ++#define mmPA_SU_VTX_CNTL 0x02f9 ++#define mmPA_SU_VTX_CNTL_BASE_IDX 1 ++#define mmPA_CL_GB_VERT_CLIP_ADJ 0x02fa ++#define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 ++#define mmPA_CL_GB_VERT_DISC_ADJ 0x02fb ++#define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 ++#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x02fc ++#define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 ++#define mmPA_CL_GB_HORZ_DISC_ADJ 0x02fd ++#define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d ++#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 ++#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0x030e ++#define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 ++#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0x030f ++#define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 ++#define mmPA_SC_SHADER_CONTROL 0x0310 ++#define mmPA_SC_SHADER_CONTROL_BASE_IDX 1 ++#define mmPA_SC_BINNER_CNTL_0 0x0311 ++#define mmPA_SC_BINNER_CNTL_0_BASE_IDX 1 ++#define mmPA_SC_BINNER_CNTL_1 0x0312 ++#define mmPA_SC_BINNER_CNTL_1_BASE_IDX 1 ++#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 ++#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 ++#define mmPA_SC_NGG_MODE_CNTL 0x0314 ++#define mmPA_SC_NGG_MODE_CNTL_BASE_IDX 1 ++#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x0316 ++#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 ++#define mmVGT_OUT_DEALLOC_CNTL 0x0317 ++#define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 ++#define mmCB_COLOR0_BASE 0x0318 ++#define mmCB_COLOR0_BASE_BASE_IDX 1 ++#define mmCB_COLOR0_BASE_EXT 0x0319 ++#define mmCB_COLOR0_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR0_ATTRIB2 0x031a ++#define mmCB_COLOR0_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR0_VIEW 0x031b ++#define mmCB_COLOR0_VIEW_BASE_IDX 1 ++#define mmCB_COLOR0_INFO 0x031c ++#define mmCB_COLOR0_INFO_BASE_IDX 1 ++#define mmCB_COLOR0_ATTRIB 0x031d ++#define mmCB_COLOR0_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR0_DCC_CONTROL 0x031e ++#define mmCB_COLOR0_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR0_CMASK 0x031f ++#define mmCB_COLOR0_CMASK_BASE_IDX 1 ++#define mmCB_COLOR0_CMASK_BASE_EXT 0x0320 ++#define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR0_FMASK 0x0321 ++#define mmCB_COLOR0_FMASK_BASE_IDX 1 ++#define mmCB_COLOR0_FMASK_BASE_EXT 0x0322 ++#define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR0_CLEAR_WORD0 0x0323 ++#define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR0_CLEAR_WORD1 0x0324 ++#define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR0_DCC_BASE 0x0325 ++#define mmCB_COLOR0_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR0_DCC_BASE_EXT 0x0326 ++#define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR1_BASE 0x0327 ++#define mmCB_COLOR1_BASE_BASE_IDX 1 ++#define mmCB_COLOR1_BASE_EXT 0x0328 ++#define mmCB_COLOR1_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR1_ATTRIB2 0x0329 ++#define mmCB_COLOR1_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR1_VIEW 0x032a ++#define mmCB_COLOR1_VIEW_BASE_IDX 1 ++#define mmCB_COLOR1_INFO 0x032b ++#define mmCB_COLOR1_INFO_BASE_IDX 1 ++#define mmCB_COLOR1_ATTRIB 0x032c ++#define mmCB_COLOR1_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR1_DCC_CONTROL 0x032d ++#define mmCB_COLOR1_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR1_CMASK 0x032e ++#define mmCB_COLOR1_CMASK_BASE_IDX 1 ++#define mmCB_COLOR1_CMASK_BASE_EXT 0x032f ++#define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR1_FMASK 0x0330 ++#define mmCB_COLOR1_FMASK_BASE_IDX 1 ++#define mmCB_COLOR1_FMASK_BASE_EXT 0x0331 ++#define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR1_CLEAR_WORD0 0x0332 ++#define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR1_CLEAR_WORD1 0x0333 ++#define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR1_DCC_BASE 0x0334 ++#define mmCB_COLOR1_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR1_DCC_BASE_EXT 0x0335 ++#define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR2_BASE 0x0336 ++#define mmCB_COLOR2_BASE_BASE_IDX 1 ++#define mmCB_COLOR2_BASE_EXT 0x0337 ++#define mmCB_COLOR2_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR2_ATTRIB2 0x0338 ++#define mmCB_COLOR2_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR2_VIEW 0x0339 ++#define mmCB_COLOR2_VIEW_BASE_IDX 1 ++#define mmCB_COLOR2_INFO 0x033a ++#define mmCB_COLOR2_INFO_BASE_IDX 1 ++#define mmCB_COLOR2_ATTRIB 0x033b ++#define mmCB_COLOR2_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR2_DCC_CONTROL 0x033c ++#define mmCB_COLOR2_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR2_CMASK 0x033d ++#define mmCB_COLOR2_CMASK_BASE_IDX 1 ++#define mmCB_COLOR2_CMASK_BASE_EXT 0x033e ++#define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR2_FMASK 0x033f ++#define mmCB_COLOR2_FMASK_BASE_IDX 1 ++#define mmCB_COLOR2_FMASK_BASE_EXT 0x0340 ++#define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR2_CLEAR_WORD0 0x0341 ++#define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR2_CLEAR_WORD1 0x0342 ++#define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR2_DCC_BASE 0x0343 ++#define mmCB_COLOR2_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR2_DCC_BASE_EXT 0x0344 ++#define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR3_BASE 0x0345 ++#define mmCB_COLOR3_BASE_BASE_IDX 1 ++#define mmCB_COLOR3_BASE_EXT 0x0346 ++#define mmCB_COLOR3_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR3_ATTRIB2 0x0347 ++#define mmCB_COLOR3_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR3_VIEW 0x0348 ++#define mmCB_COLOR3_VIEW_BASE_IDX 1 ++#define mmCB_COLOR3_INFO 0x0349 ++#define mmCB_COLOR3_INFO_BASE_IDX 1 ++#define mmCB_COLOR3_ATTRIB 0x034a ++#define mmCB_COLOR3_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR3_DCC_CONTROL 0x034b ++#define mmCB_COLOR3_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR3_CMASK 0x034c ++#define mmCB_COLOR3_CMASK_BASE_IDX 1 ++#define mmCB_COLOR3_CMASK_BASE_EXT 0x034d ++#define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR3_FMASK 0x034e ++#define mmCB_COLOR3_FMASK_BASE_IDX 1 ++#define mmCB_COLOR3_FMASK_BASE_EXT 0x034f ++#define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR3_CLEAR_WORD0 0x0350 ++#define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR3_CLEAR_WORD1 0x0351 ++#define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR3_DCC_BASE 0x0352 ++#define mmCB_COLOR3_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR3_DCC_BASE_EXT 0x0353 ++#define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR4_BASE 0x0354 ++#define mmCB_COLOR4_BASE_BASE_IDX 1 ++#define mmCB_COLOR4_BASE_EXT 0x0355 ++#define mmCB_COLOR4_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR4_ATTRIB2 0x0356 ++#define mmCB_COLOR4_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR4_VIEW 0x0357 ++#define mmCB_COLOR4_VIEW_BASE_IDX 1 ++#define mmCB_COLOR4_INFO 0x0358 ++#define mmCB_COLOR4_INFO_BASE_IDX 1 ++#define mmCB_COLOR4_ATTRIB 0x0359 ++#define mmCB_COLOR4_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR4_DCC_CONTROL 0x035a ++#define mmCB_COLOR4_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR4_CMASK 0x035b ++#define mmCB_COLOR4_CMASK_BASE_IDX 1 ++#define mmCB_COLOR4_CMASK_BASE_EXT 0x035c ++#define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR4_FMASK 0x035d ++#define mmCB_COLOR4_FMASK_BASE_IDX 1 ++#define mmCB_COLOR4_FMASK_BASE_EXT 0x035e ++#define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR4_CLEAR_WORD0 0x035f ++#define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR4_CLEAR_WORD1 0x0360 ++#define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR4_DCC_BASE 0x0361 ++#define mmCB_COLOR4_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR4_DCC_BASE_EXT 0x0362 ++#define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR5_BASE 0x0363 ++#define mmCB_COLOR5_BASE_BASE_IDX 1 ++#define mmCB_COLOR5_BASE_EXT 0x0364 ++#define mmCB_COLOR5_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR5_ATTRIB2 0x0365 ++#define mmCB_COLOR5_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR5_VIEW 0x0366 ++#define mmCB_COLOR5_VIEW_BASE_IDX 1 ++#define mmCB_COLOR5_INFO 0x0367 ++#define mmCB_COLOR5_INFO_BASE_IDX 1 ++#define mmCB_COLOR5_ATTRIB 0x0368 ++#define mmCB_COLOR5_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR5_DCC_CONTROL 0x0369 ++#define mmCB_COLOR5_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR5_CMASK 0x036a ++#define mmCB_COLOR5_CMASK_BASE_IDX 1 ++#define mmCB_COLOR5_CMASK_BASE_EXT 0x036b ++#define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR5_FMASK 0x036c ++#define mmCB_COLOR5_FMASK_BASE_IDX 1 ++#define mmCB_COLOR5_FMASK_BASE_EXT 0x036d ++#define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR5_CLEAR_WORD0 0x036e ++#define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR5_CLEAR_WORD1 0x036f ++#define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR5_DCC_BASE 0x0370 ++#define mmCB_COLOR5_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR5_DCC_BASE_EXT 0x0371 ++#define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR6_BASE 0x0372 ++#define mmCB_COLOR6_BASE_BASE_IDX 1 ++#define mmCB_COLOR6_BASE_EXT 0x0373 ++#define mmCB_COLOR6_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR6_ATTRIB2 0x0374 ++#define mmCB_COLOR6_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR6_VIEW 0x0375 ++#define mmCB_COLOR6_VIEW_BASE_IDX 1 ++#define mmCB_COLOR6_INFO 0x0376 ++#define mmCB_COLOR6_INFO_BASE_IDX 1 ++#define mmCB_COLOR6_ATTRIB 0x0377 ++#define mmCB_COLOR6_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR6_DCC_CONTROL 0x0378 ++#define mmCB_COLOR6_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR6_CMASK 0x0379 ++#define mmCB_COLOR6_CMASK_BASE_IDX 1 ++#define mmCB_COLOR6_CMASK_BASE_EXT 0x037a ++#define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR6_FMASK 0x037b ++#define mmCB_COLOR6_FMASK_BASE_IDX 1 ++#define mmCB_COLOR6_FMASK_BASE_EXT 0x037c ++#define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR6_CLEAR_WORD0 0x037d ++#define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR6_CLEAR_WORD1 0x037e ++#define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR6_DCC_BASE 0x037f ++#define mmCB_COLOR6_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR6_DCC_BASE_EXT 0x0380 ++#define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR7_BASE 0x0381 ++#define mmCB_COLOR7_BASE_BASE_IDX 1 ++#define mmCB_COLOR7_BASE_EXT 0x0382 ++#define mmCB_COLOR7_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR7_ATTRIB2 0x0383 ++#define mmCB_COLOR7_ATTRIB2_BASE_IDX 1 ++#define mmCB_COLOR7_VIEW 0x0384 ++#define mmCB_COLOR7_VIEW_BASE_IDX 1 ++#define mmCB_COLOR7_INFO 0x0385 ++#define mmCB_COLOR7_INFO_BASE_IDX 1 ++#define mmCB_COLOR7_ATTRIB 0x0386 ++#define mmCB_COLOR7_ATTRIB_BASE_IDX 1 ++#define mmCB_COLOR7_DCC_CONTROL 0x0387 ++#define mmCB_COLOR7_DCC_CONTROL_BASE_IDX 1 ++#define mmCB_COLOR7_CMASK 0x0388 ++#define mmCB_COLOR7_CMASK_BASE_IDX 1 ++#define mmCB_COLOR7_CMASK_BASE_EXT 0x0389 ++#define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR7_FMASK 0x038a ++#define mmCB_COLOR7_FMASK_BASE_IDX 1 ++#define mmCB_COLOR7_FMASK_BASE_EXT 0x038b ++#define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 ++#define mmCB_COLOR7_CLEAR_WORD0 0x038c ++#define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 ++#define mmCB_COLOR7_CLEAR_WORD1 0x038d ++#define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 ++#define mmCB_COLOR7_DCC_BASE 0x038e ++#define mmCB_COLOR7_DCC_BASE_BASE_IDX 1 ++#define mmCB_COLOR7_DCC_BASE_EXT 0x038f ++#define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 ++ ++ ++// addressBlock: gc_gfxudec ++// base address: 0x30000 ++#define mmCP_EOP_DONE_ADDR_LO 0x2000 ++#define mmCP_EOP_DONE_ADDR_LO_BASE_IDX 1 ++#define mmCP_EOP_DONE_ADDR_HI 0x2001 ++#define mmCP_EOP_DONE_ADDR_HI_BASE_IDX 1 ++#define mmCP_EOP_DONE_DATA_LO 0x2002 ++#define mmCP_EOP_DONE_DATA_LO_BASE_IDX 1 ++#define mmCP_EOP_DONE_DATA_HI 0x2003 ++#define mmCP_EOP_DONE_DATA_HI_BASE_IDX 1 ++#define mmCP_EOP_LAST_FENCE_LO 0x2004 ++#define mmCP_EOP_LAST_FENCE_LO_BASE_IDX 1 ++#define mmCP_EOP_LAST_FENCE_HI 0x2005 ++#define mmCP_EOP_LAST_FENCE_HI_BASE_IDX 1 ++#define mmCP_STREAM_OUT_ADDR_LO 0x2006 ++#define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 ++#define mmCP_STREAM_OUT_ADDR_HI 0x2007 ++#define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2008 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2009 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x200a ++#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x200b ++#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x200c ++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x200d ++#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x200e ++#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x200f ++#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2010 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2011 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2012 ++#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2013 ++#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2014 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2015 ++#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2016 ++#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 ++#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2017 ++#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 ++#define mmCP_PIPE_STATS_ADDR_LO 0x2018 ++#define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 ++#define mmCP_PIPE_STATS_ADDR_HI 0x2019 ++#define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 ++#define mmCP_VGT_IAVERT_COUNT_LO 0x201a ++#define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_IAVERT_COUNT_HI 0x201b ++#define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 ++#define mmCP_VGT_IAPRIM_COUNT_LO 0x201c ++#define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_IAPRIM_COUNT_HI 0x201d ++#define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 ++#define mmCP_VGT_GSPRIM_COUNT_LO 0x201e ++#define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_GSPRIM_COUNT_HI 0x201f ++#define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 ++#define mmCP_VGT_VSINVOC_COUNT_LO 0x2020 ++#define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_VSINVOC_COUNT_HI 0x2021 ++#define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 ++#define mmCP_VGT_GSINVOC_COUNT_LO 0x2022 ++#define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_GSINVOC_COUNT_HI 0x2023 ++#define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 ++#define mmCP_VGT_HSINVOC_COUNT_LO 0x2024 ++#define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_HSINVOC_COUNT_HI 0x2025 ++#define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 ++#define mmCP_VGT_DSINVOC_COUNT_LO 0x2026 ++#define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_DSINVOC_COUNT_HI 0x2027 ++#define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 ++#define mmCP_PA_CINVOC_COUNT_LO 0x2028 ++#define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 ++#define mmCP_PA_CINVOC_COUNT_HI 0x2029 ++#define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 ++#define mmCP_PA_CPRIM_COUNT_LO 0x202a ++#define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 ++#define mmCP_PA_CPRIM_COUNT_HI 0x202b ++#define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 ++#define mmCP_SC_PSINVOC_COUNT0_LO 0x202c ++#define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 ++#define mmCP_SC_PSINVOC_COUNT0_HI 0x202d ++#define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 ++#define mmCP_SC_PSINVOC_COUNT1_LO 0x202e ++#define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 ++#define mmCP_SC_PSINVOC_COUNT1_HI 0x202f ++#define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 ++#define mmCP_VGT_CSINVOC_COUNT_LO 0x2030 ++#define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 ++#define mmCP_VGT_CSINVOC_COUNT_HI 0x2031 ++#define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 ++#define mmCP_PIPE_STATS_CONTROL 0x203d ++#define mmCP_PIPE_STATS_CONTROL_BASE_IDX 1 ++#define mmCP_STREAM_OUT_CONTROL 0x203e ++#define mmCP_STREAM_OUT_CONTROL_BASE_IDX 1 ++#define mmCP_STRMOUT_CNTL 0x203f ++#define mmCP_STRMOUT_CNTL_BASE_IDX 1 ++#define mmSCRATCH_REG0 0x2040 ++#define mmSCRATCH_REG0_BASE_IDX 1 ++#define mmSCRATCH_REG1 0x2041 ++#define mmSCRATCH_REG1_BASE_IDX 1 ++#define mmSCRATCH_REG2 0x2042 ++#define mmSCRATCH_REG2_BASE_IDX 1 ++#define mmSCRATCH_REG3 0x2043 ++#define mmSCRATCH_REG3_BASE_IDX 1 ++#define mmSCRATCH_REG4 0x2044 ++#define mmSCRATCH_REG4_BASE_IDX 1 ++#define mmSCRATCH_REG5 0x2045 ++#define mmSCRATCH_REG5_BASE_IDX 1 ++#define mmSCRATCH_REG6 0x2046 ++#define mmSCRATCH_REG6_BASE_IDX 1 ++#define mmSCRATCH_REG7 0x2047 ++#define mmSCRATCH_REG7_BASE_IDX 1 ++#define mmCP_APPEND_DATA_HI 0x204c ++#define mmCP_APPEND_DATA_HI_BASE_IDX 1 ++#define mmCP_APPEND_LAST_CS_FENCE_HI 0x204d ++#define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 ++#define mmCP_APPEND_LAST_PS_FENCE_HI 0x204e ++#define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 ++#define mmSCRATCH_UMSK 0x2050 ++#define mmSCRATCH_UMSK_BASE_IDX 1 ++#define mmSCRATCH_ADDR 0x2051 ++#define mmSCRATCH_ADDR_BASE_IDX 1 ++#define mmCP_PFP_ATOMIC_PREOP_LO 0x2052 ++#define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 ++#define mmCP_PFP_ATOMIC_PREOP_HI 0x2053 ++#define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 ++#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 ++#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 ++#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 ++#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 ++#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 ++#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 ++#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 ++#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 ++#define mmCP_APPEND_ADDR_LO 0x2058 ++#define mmCP_APPEND_ADDR_LO_BASE_IDX 1 ++#define mmCP_APPEND_ADDR_HI 0x2059 ++#define mmCP_APPEND_ADDR_HI_BASE_IDX 1 ++#define mmCP_APPEND_DATA_LO 0x205a ++#define mmCP_APPEND_DATA_LO_BASE_IDX 1 ++#define mmCP_APPEND_LAST_CS_FENCE_LO 0x205b ++#define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 ++#define mmCP_APPEND_LAST_PS_FENCE_LO 0x205c ++#define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 ++#define mmCP_ATOMIC_PREOP_LO 0x205d ++#define mmCP_ATOMIC_PREOP_LO_BASE_IDX 1 ++#define mmCP_ME_ATOMIC_PREOP_LO 0x205d ++#define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 ++#define mmCP_ATOMIC_PREOP_HI 0x205e ++#define mmCP_ATOMIC_PREOP_HI_BASE_IDX 1 ++#define mmCP_ME_ATOMIC_PREOP_HI 0x205e ++#define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 ++#define mmCP_GDS_ATOMIC0_PREOP_LO 0x205f ++#define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 ++#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f ++#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 ++#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2060 ++#define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 ++#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 ++#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 ++#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2061 ++#define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 ++#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 ++#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 ++#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2062 ++#define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 ++#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 ++#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 ++#define mmCP_ME_MC_WADDR_LO 0x2069 ++#define mmCP_ME_MC_WADDR_LO_BASE_IDX 1 ++#define mmCP_ME_MC_WADDR_HI 0x206a ++#define mmCP_ME_MC_WADDR_HI_BASE_IDX 1 ++#define mmCP_ME_MC_WDATA_LO 0x206b ++#define mmCP_ME_MC_WDATA_LO_BASE_IDX 1 ++#define mmCP_ME_MC_WDATA_HI 0x206c ++#define mmCP_ME_MC_WDATA_HI_BASE_IDX 1 ++#define mmCP_ME_MC_RADDR_LO 0x206d ++#define mmCP_ME_MC_RADDR_LO_BASE_IDX 1 ++#define mmCP_ME_MC_RADDR_HI 0x206e ++#define mmCP_ME_MC_RADDR_HI_BASE_IDX 1 ++#define mmCP_SEM_WAIT_TIMER 0x206f ++#define mmCP_SEM_WAIT_TIMER_BASE_IDX 1 ++#define mmCP_SIG_SEM_ADDR_LO 0x2070 ++#define mmCP_SIG_SEM_ADDR_LO_BASE_IDX 1 ++#define mmCP_SIG_SEM_ADDR_HI 0x2071 ++#define mmCP_SIG_SEM_ADDR_HI_BASE_IDX 1 ++#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2074 ++#define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 ++#define mmCP_WAIT_SEM_ADDR_LO 0x2075 ++#define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 ++#define mmCP_WAIT_SEM_ADDR_HI 0x2076 ++#define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 ++#define mmCP_DMA_PFP_CONTROL 0x2077 ++#define mmCP_DMA_PFP_CONTROL_BASE_IDX 1 ++#define mmCP_DMA_ME_CONTROL 0x2078 ++#define mmCP_DMA_ME_CONTROL_BASE_IDX 1 ++#define mmCP_COHER_BASE_HI 0x2079 ++#define mmCP_COHER_BASE_HI_BASE_IDX 1 ++#define mmCP_COHER_START_DELAY 0x207b ++#define mmCP_COHER_START_DELAY_BASE_IDX 1 ++#define mmCP_COHER_CNTL 0x207c ++#define mmCP_COHER_CNTL_BASE_IDX 1 ++#define mmCP_COHER_SIZE 0x207d ++#define mmCP_COHER_SIZE_BASE_IDX 1 ++#define mmCP_COHER_BASE 0x207e ++#define mmCP_COHER_BASE_BASE_IDX 1 ++#define mmCP_COHER_STATUS 0x207f ++#define mmCP_COHER_STATUS_BASE_IDX 1 ++#define mmCP_DMA_ME_SRC_ADDR 0x2080 ++#define mmCP_DMA_ME_SRC_ADDR_BASE_IDX 1 ++#define mmCP_DMA_ME_SRC_ADDR_HI 0x2081 ++#define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 ++#define mmCP_DMA_ME_DST_ADDR 0x2082 ++#define mmCP_DMA_ME_DST_ADDR_BASE_IDX 1 ++#define mmCP_DMA_ME_DST_ADDR_HI 0x2083 ++#define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 ++#define mmCP_DMA_ME_COMMAND 0x2084 ++#define mmCP_DMA_ME_COMMAND_BASE_IDX 1 ++#define mmCP_DMA_PFP_SRC_ADDR 0x2085 ++#define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 ++#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2086 ++#define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 ++#define mmCP_DMA_PFP_DST_ADDR 0x2087 ++#define mmCP_DMA_PFP_DST_ADDR_BASE_IDX 1 ++#define mmCP_DMA_PFP_DST_ADDR_HI 0x2088 ++#define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 ++#define mmCP_DMA_PFP_COMMAND 0x2089 ++#define mmCP_DMA_PFP_COMMAND_BASE_IDX 1 ++#define mmCP_DMA_CNTL 0x208a ++#define mmCP_DMA_CNTL_BASE_IDX 1 ++#define mmCP_DMA_READ_TAGS 0x208b ++#define mmCP_DMA_READ_TAGS_BASE_IDX 1 ++#define mmCP_COHER_SIZE_HI 0x208c ++#define mmCP_COHER_SIZE_HI_BASE_IDX 1 ++#define mmCP_PFP_IB_CONTROL 0x208d ++#define mmCP_PFP_IB_CONTROL_BASE_IDX 1 ++#define mmCP_PFP_LOAD_CONTROL 0x208e ++#define mmCP_PFP_LOAD_CONTROL_BASE_IDX 1 ++#define mmCP_SCRATCH_INDEX 0x208f ++#define mmCP_SCRATCH_INDEX_BASE_IDX 1 ++#define mmCP_SCRATCH_DATA 0x2090 ++#define mmCP_SCRATCH_DATA_BASE_IDX 1 ++#define mmCP_RB_OFFSET 0x2091 ++#define mmCP_RB_OFFSET_BASE_IDX 1 ++#define mmCP_IB1_OFFSET 0x2092 ++#define mmCP_IB1_OFFSET_BASE_IDX 1 ++#define mmCP_IB2_OFFSET 0x2093 ++#define mmCP_IB2_OFFSET_BASE_IDX 1 ++#define mmCP_IB1_PREAMBLE_BEGIN 0x2094 ++#define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 ++#define mmCP_IB1_PREAMBLE_END 0x2095 ++#define mmCP_IB1_PREAMBLE_END_BASE_IDX 1 ++#define mmCP_IB2_PREAMBLE_BEGIN 0x2096 ++#define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 ++#define mmCP_IB2_PREAMBLE_END 0x2097 ++#define mmCP_IB2_PREAMBLE_END_BASE_IDX 1 ++#define mmCP_CE_IB1_OFFSET 0x2098 ++#define mmCP_CE_IB1_OFFSET_BASE_IDX 1 ++#define mmCP_CE_IB2_OFFSET 0x2099 ++#define mmCP_CE_IB2_OFFSET_BASE_IDX 1 ++#define mmCP_CE_COUNTER 0x209a ++#define mmCP_CE_COUNTER_BASE_IDX 1 ++#define mmCP_CE_RB_OFFSET 0x209b ++#define mmCP_CE_RB_OFFSET_BASE_IDX 1 ++#define mmCP_CE_INIT_CMD_BUFSZ 0x20bd ++#define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 ++#define mmCP_CE_IB1_CMD_BUFSZ 0x20be ++#define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 ++#define mmCP_CE_IB2_CMD_BUFSZ 0x20bf ++#define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 ++#define mmCP_IB1_CMD_BUFSZ 0x20c0 ++#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1 ++#define mmCP_IB2_CMD_BUFSZ 0x20c1 ++#define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 ++#define mmCP_ST_CMD_BUFSZ 0x20c2 ++#define mmCP_ST_CMD_BUFSZ_BASE_IDX 1 ++#define mmCP_CE_INIT_BASE_LO 0x20c3 ++#define mmCP_CE_INIT_BASE_LO_BASE_IDX 1 ++#define mmCP_CE_INIT_BASE_HI 0x20c4 ++#define mmCP_CE_INIT_BASE_HI_BASE_IDX 1 ++#define mmCP_CE_INIT_BUFSZ 0x20c5 ++#define mmCP_CE_INIT_BUFSZ_BASE_IDX 1 ++#define mmCP_CE_IB1_BASE_LO 0x20c6 ++#define mmCP_CE_IB1_BASE_LO_BASE_IDX 1 ++#define mmCP_CE_IB1_BASE_HI 0x20c7 ++#define mmCP_CE_IB1_BASE_HI_BASE_IDX 1 ++#define mmCP_CE_IB1_BUFSZ 0x20c8 ++#define mmCP_CE_IB1_BUFSZ_BASE_IDX 1 ++#define mmCP_CE_IB2_BASE_LO 0x20c9 ++#define mmCP_CE_IB2_BASE_LO_BASE_IDX 1 ++#define mmCP_CE_IB2_BASE_HI 0x20ca ++#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1 ++#define mmCP_CE_IB2_BUFSZ 0x20cb ++#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1 ++#define mmCP_IB1_BASE_LO 0x20cc ++#define mmCP_IB1_BASE_LO_BASE_IDX 1 ++#define mmCP_IB1_BASE_HI 0x20cd ++#define mmCP_IB1_BASE_HI_BASE_IDX 1 ++#define mmCP_IB1_BUFSZ 0x20ce ++#define mmCP_IB1_BUFSZ_BASE_IDX 1 ++#define mmCP_IB2_BASE_LO 0x20cf ++#define mmCP_IB2_BASE_LO_BASE_IDX 1 ++#define mmCP_IB2_BASE_HI 0x20d0 ++#define mmCP_IB2_BASE_HI_BASE_IDX 1 ++#define mmCP_IB2_BUFSZ 0x20d1 ++#define mmCP_IB2_BUFSZ_BASE_IDX 1 ++#define mmCP_ST_BASE_LO 0x20d2 ++#define mmCP_ST_BASE_LO_BASE_IDX 1 ++#define mmCP_ST_BASE_HI 0x20d3 ++#define mmCP_ST_BASE_HI_BASE_IDX 1 ++#define mmCP_ST_BUFSZ 0x20d4 ++#define mmCP_ST_BUFSZ_BASE_IDX 1 ++#define mmCP_EOP_DONE_EVENT_CNTL 0x20d5 ++#define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 ++#define mmCP_EOP_DONE_DATA_CNTL 0x20d6 ++#define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 ++#define mmCP_EOP_DONE_CNTX_ID 0x20d7 ++#define mmCP_EOP_DONE_CNTX_ID_BASE_IDX 1 ++#define mmCP_PFP_COMPLETION_STATUS 0x20ec ++#define mmCP_PFP_COMPLETION_STATUS_BASE_IDX 1 ++#define mmCP_CE_COMPLETION_STATUS 0x20ed ++#define mmCP_CE_COMPLETION_STATUS_BASE_IDX 1 ++#define mmCP_PRED_NOT_VISIBLE 0x20ee ++#define mmCP_PRED_NOT_VISIBLE_BASE_IDX 1 ++#define mmCP_PFP_METADATA_BASE_ADDR 0x20f0 ++#define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 ++#define mmCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 ++#define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 ++#define mmCP_CE_METADATA_BASE_ADDR 0x20f2 ++#define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 ++#define mmCP_CE_METADATA_BASE_ADDR_HI 0x20f3 ++#define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 ++#define mmCP_DRAW_INDX_INDR_ADDR 0x20f4 ++#define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 ++#define mmCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 ++#define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 ++#define mmCP_DISPATCH_INDR_ADDR 0x20f6 ++#define mmCP_DISPATCH_INDR_ADDR_BASE_IDX 1 ++#define mmCP_DISPATCH_INDR_ADDR_HI 0x20f7 ++#define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 ++#define mmCP_INDEX_BASE_ADDR 0x20f8 ++#define mmCP_INDEX_BASE_ADDR_BASE_IDX 1 ++#define mmCP_INDEX_BASE_ADDR_HI 0x20f9 ++#define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 ++#define mmCP_INDEX_TYPE 0x20fa ++#define mmCP_INDEX_TYPE_BASE_IDX 1 ++#define mmCP_GDS_BKUP_ADDR 0x20fb ++#define mmCP_GDS_BKUP_ADDR_BASE_IDX 1 ++#define mmCP_GDS_BKUP_ADDR_HI 0x20fc ++#define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 ++#define mmCP_SAMPLE_STATUS 0x20fd ++#define mmCP_SAMPLE_STATUS_BASE_IDX 1 ++#define mmCP_ME_COHER_CNTL 0x20fe ++#define mmCP_ME_COHER_CNTL_BASE_IDX 1 ++#define mmCP_ME_COHER_SIZE 0x20ff ++#define mmCP_ME_COHER_SIZE_BASE_IDX 1 ++#define mmCP_ME_COHER_SIZE_HI 0x2100 ++#define mmCP_ME_COHER_SIZE_HI_BASE_IDX 1 ++#define mmCP_ME_COHER_BASE 0x2101 ++#define mmCP_ME_COHER_BASE_BASE_IDX 1 ++#define mmCP_ME_COHER_BASE_HI 0x2102 ++#define mmCP_ME_COHER_BASE_HI_BASE_IDX 1 ++#define mmCP_ME_COHER_STATUS 0x2103 ++#define mmCP_ME_COHER_STATUS_BASE_IDX 1 ++#define mmRLC_GPM_PERF_COUNT_0 0x2140 ++#define mmRLC_GPM_PERF_COUNT_0_BASE_IDX 1 ++#define mmRLC_GPM_PERF_COUNT_1 0x2141 ++#define mmRLC_GPM_PERF_COUNT_1_BASE_IDX 1 ++#define mmGRBM_GFX_INDEX 0x2200 ++#define mmGRBM_GFX_INDEX_BASE_IDX 1 ++#define mmVGT_GSVS_RING_SIZE 0x2241 ++#define mmVGT_GSVS_RING_SIZE_BASE_IDX 1 ++#define mmVGT_PRIMITIVE_TYPE 0x2242 ++#define mmVGT_PRIMITIVE_TYPE_BASE_IDX 1 ++#define mmVGT_INDEX_TYPE 0x2243 ++#define mmVGT_INDEX_TYPE_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2244 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2245 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x2246 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x2247 ++#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 ++#define mmVGT_MAX_VTX_INDX 0x2248 ++#define mmVGT_MAX_VTX_INDX_BASE_IDX 1 ++#define mmVGT_MIN_VTX_INDX 0x2249 ++#define mmVGT_MIN_VTX_INDX_BASE_IDX 1 ++#define mmVGT_INDX_OFFSET 0x224a ++#define mmVGT_INDX_OFFSET_BASE_IDX 1 ++#define mmVGT_MULTI_PRIM_IB_RESET_EN 0x224b ++#define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 ++#define mmVGT_NUM_INDICES 0x224c ++#define mmVGT_NUM_INDICES_BASE_IDX 1 ++#define mmVGT_NUM_INSTANCES 0x224d ++#define mmVGT_NUM_INSTANCES_BASE_IDX 1 ++#define mmVGT_TF_RING_SIZE 0x224e ++#define mmVGT_TF_RING_SIZE_BASE_IDX 1 ++#define mmVGT_HS_OFFCHIP_PARAM 0x224f ++#define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 ++#define mmVGT_TF_MEMORY_BASE 0x2250 ++#define mmVGT_TF_MEMORY_BASE_BASE_IDX 1 ++#define mmVGT_TF_MEMORY_BASE_HI 0x2251 ++#define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 ++#define mmWD_POS_BUF_BASE 0x2252 ++#define mmWD_POS_BUF_BASE_BASE_IDX 1 ++#define mmWD_POS_BUF_BASE_HI 0x2253 ++#define mmWD_POS_BUF_BASE_HI_BASE_IDX 1 ++#define mmWD_CNTL_SB_BUF_BASE 0x2254 ++#define mmWD_CNTL_SB_BUF_BASE_BASE_IDX 1 ++#define mmWD_CNTL_SB_BUF_BASE_HI 0x2255 ++#define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 ++#define mmWD_INDEX_BUF_BASE 0x2256 ++#define mmWD_INDEX_BUF_BASE_BASE_IDX 1 ++#define mmWD_INDEX_BUF_BASE_HI 0x2257 ++#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 ++#define mmIA_MULTI_VGT_PARAM 0x2258 ++#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 ++#define mmVGT_INSTANCE_BASE_ID 0x225a ++#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 ++#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 ++#define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 ++#define mmPA_SC_LINE_STIPPLE_STATE 0x2281 ++#define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 ++#define mmPA_SC_SCREEN_EXTENT_MIN_0 0x2284 ++#define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 ++#define mmPA_SC_SCREEN_EXTENT_MAX_0 0x2285 ++#define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 ++#define mmPA_SC_SCREEN_EXTENT_MIN_1 0x2286 ++#define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 ++#define mmPA_SC_SCREEN_EXTENT_MAX_1 0x228b ++#define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 ++#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 ++#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 ++#define mmPA_SC_P3D_TRAP_SCREEN_H 0x22a1 ++#define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 ++#define mmPA_SC_P3D_TRAP_SCREEN_V 0x22a2 ++#define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 ++#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 ++#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 ++#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 ++#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 ++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 ++#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 ++#define mmPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 ++#define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 ++#define mmPA_SC_HP3D_TRAP_SCREEN_V 0x22aa ++#define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 ++#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab ++#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 ++#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac ++#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 ++#define mmPA_SC_TRAP_SCREEN_HV_EN 0x22b0 ++#define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 ++#define mmPA_SC_TRAP_SCREEN_H 0x22b1 ++#define mmPA_SC_TRAP_SCREEN_H_BASE_IDX 1 ++#define mmPA_SC_TRAP_SCREEN_V 0x22b2 ++#define mmPA_SC_TRAP_SCREEN_V_BASE_IDX 1 ++#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 ++#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 ++#define mmPA_SC_TRAP_SCREEN_COUNT 0x22b4 ++#define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 ++#define mmPA_STATE_STEREO_X 0x22b5 ++#define mmPA_STATE_STEREO_X_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_BASE 0x2330 ++#define mmSQ_THREAD_TRACE_BASE_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_SIZE 0x2331 ++#define mmSQ_THREAD_TRACE_SIZE_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_MASK 0x2332 ++#define mmSQ_THREAD_TRACE_MASK_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2333 ++#define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_PERF_MASK 0x2334 ++#define mmSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_CTRL 0x2335 ++#define mmSQ_THREAD_TRACE_CTRL_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_MODE 0x2336 ++#define mmSQ_THREAD_TRACE_MODE_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_BASE2 0x2337 ++#define mmSQ_THREAD_TRACE_BASE2_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2338 ++#define mmSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_WPTR 0x2339 ++#define mmSQ_THREAD_TRACE_WPTR_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_STATUS 0x233a ++#define mmSQ_THREAD_TRACE_STATUS_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_HIWATER 0x233b ++#define mmSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_CNTR 0x233c ++#define mmSQ_THREAD_TRACE_CNTR_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_USERDATA_0 0x2340 ++#define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_USERDATA_1 0x2341 ++#define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_USERDATA_2 0x2342 ++#define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 ++#define mmSQ_THREAD_TRACE_USERDATA_3 0x2343 ++#define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 ++#define mmSQC_CACHES 0x2348 ++#define mmSQC_CACHES_BASE_IDX 1 ++#define mmSQC_WRITEBACK 0x2349 ++#define mmSQC_WRITEBACK_BASE_IDX 1 ++#define mmTA_CS_BC_BASE_ADDR 0x2380 ++#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 ++#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 ++#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 ++#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 ++#define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT1_LOW 0x23c2 ++#define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT1_HI 0x23c3 ++#define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT2_LOW 0x23c4 ++#define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT2_HI 0x23c5 ++#define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT3_LOW 0x23c6 ++#define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 ++#define mmDB_OCCLUSION_COUNT3_HI 0x23c7 ++#define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 ++#define mmDB_ZPASS_COUNT_LOW 0x23fe ++#define mmDB_ZPASS_COUNT_LOW_BASE_IDX 1 ++#define mmDB_ZPASS_COUNT_HI 0x23ff ++#define mmDB_ZPASS_COUNT_HI_BASE_IDX 1 ++#define mmGDS_RD_ADDR 0x2400 ++#define mmGDS_RD_ADDR_BASE_IDX 1 ++#define mmGDS_RD_DATA 0x2401 ++#define mmGDS_RD_DATA_BASE_IDX 1 ++#define mmGDS_RD_BURST_ADDR 0x2402 ++#define mmGDS_RD_BURST_ADDR_BASE_IDX 1 ++#define mmGDS_RD_BURST_COUNT 0x2403 ++#define mmGDS_RD_BURST_COUNT_BASE_IDX 1 ++#define mmGDS_RD_BURST_DATA 0x2404 ++#define mmGDS_RD_BURST_DATA_BASE_IDX 1 ++#define mmGDS_WR_ADDR 0x2405 ++#define mmGDS_WR_ADDR_BASE_IDX 1 ++#define mmGDS_WR_DATA 0x2406 ++#define mmGDS_WR_DATA_BASE_IDX 1 ++#define mmGDS_WR_BURST_ADDR 0x2407 ++#define mmGDS_WR_BURST_ADDR_BASE_IDX 1 ++#define mmGDS_WR_BURST_DATA 0x2408 ++#define mmGDS_WR_BURST_DATA_BASE_IDX 1 ++#define mmGDS_WRITE_COMPLETE 0x2409 ++#define mmGDS_WRITE_COMPLETE_BASE_IDX 1 ++#define mmGDS_ATOM_CNTL 0x240a ++#define mmGDS_ATOM_CNTL_BASE_IDX 1 ++#define mmGDS_ATOM_COMPLETE 0x240b ++#define mmGDS_ATOM_COMPLETE_BASE_IDX 1 ++#define mmGDS_ATOM_BASE 0x240c ++#define mmGDS_ATOM_BASE_BASE_IDX 1 ++#define mmGDS_ATOM_SIZE 0x240d ++#define mmGDS_ATOM_SIZE_BASE_IDX 1 ++#define mmGDS_ATOM_OFFSET0 0x240e ++#define mmGDS_ATOM_OFFSET0_BASE_IDX 1 ++#define mmGDS_ATOM_OFFSET1 0x240f ++#define mmGDS_ATOM_OFFSET1_BASE_IDX 1 ++#define mmGDS_ATOM_DST 0x2410 ++#define mmGDS_ATOM_DST_BASE_IDX 1 ++#define mmGDS_ATOM_OP 0x2411 ++#define mmGDS_ATOM_OP_BASE_IDX 1 ++#define mmGDS_ATOM_SRC0 0x2412 ++#define mmGDS_ATOM_SRC0_BASE_IDX 1 ++#define mmGDS_ATOM_SRC0_U 0x2413 ++#define mmGDS_ATOM_SRC0_U_BASE_IDX 1 ++#define mmGDS_ATOM_SRC1 0x2414 ++#define mmGDS_ATOM_SRC1_BASE_IDX 1 ++#define mmGDS_ATOM_SRC1_U 0x2415 ++#define mmGDS_ATOM_SRC1_U_BASE_IDX 1 ++#define mmGDS_ATOM_READ0 0x2416 ++#define mmGDS_ATOM_READ0_BASE_IDX 1 ++#define mmGDS_ATOM_READ0_U 0x2417 ++#define mmGDS_ATOM_READ0_U_BASE_IDX 1 ++#define mmGDS_ATOM_READ1 0x2418 ++#define mmGDS_ATOM_READ1_BASE_IDX 1 ++#define mmGDS_ATOM_READ1_U 0x2419 ++#define mmGDS_ATOM_READ1_U_BASE_IDX 1 ++#define mmGDS_GWS_RESOURCE_CNTL 0x241a ++#define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 ++#define mmGDS_GWS_RESOURCE 0x241b ++#define mmGDS_GWS_RESOURCE_BASE_IDX 1 ++#define mmGDS_GWS_RESOURCE_CNT 0x241c ++#define mmGDS_GWS_RESOURCE_CNT_BASE_IDX 1 ++#define mmGDS_OA_CNTL 0x241d ++#define mmGDS_OA_CNTL_BASE_IDX 1 ++#define mmGDS_OA_COUNTER 0x241e ++#define mmGDS_OA_COUNTER_BASE_IDX 1 ++#define mmGDS_OA_ADDRESS 0x241f ++#define mmGDS_OA_ADDRESS_BASE_IDX 1 ++#define mmGDS_OA_INCDEC 0x2420 ++#define mmGDS_OA_INCDEC_BASE_IDX 1 ++#define mmGDS_OA_RING_SIZE 0x2421 ++#define mmGDS_OA_RING_SIZE_BASE_IDX 1 ++#define mmSPI_CONFIG_CNTL 0x2440 ++#define mmSPI_CONFIG_CNTL_BASE_IDX 1 ++#define mmSPI_CONFIG_CNTL_1 0x2441 ++#define mmSPI_CONFIG_CNTL_1_BASE_IDX 1 ++#define mmSPI_CONFIG_CNTL_2 0x2442 ++#define mmSPI_CONFIG_CNTL_2_BASE_IDX 1 ++#define mmSPI_WAVE_LIMIT_CNTL 0x2443 ++#define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 ++ ++ ++// addressBlock: gc_perfddec ++// base address: 0x34000 ++#define mmCPG_PERFCOUNTER1_LO 0x3000 ++#define mmCPG_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmCPG_PERFCOUNTER1_HI 0x3001 ++#define mmCPG_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmCPG_PERFCOUNTER0_LO 0x3002 ++#define mmCPG_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmCPG_PERFCOUNTER0_HI 0x3003 ++#define mmCPG_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmCPC_PERFCOUNTER1_LO 0x3004 ++#define mmCPC_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmCPC_PERFCOUNTER1_HI 0x3005 ++#define mmCPC_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmCPC_PERFCOUNTER0_LO 0x3006 ++#define mmCPC_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmCPC_PERFCOUNTER0_HI 0x3007 ++#define mmCPC_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmCPF_PERFCOUNTER1_LO 0x3008 ++#define mmCPF_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmCPF_PERFCOUNTER1_HI 0x3009 ++#define mmCPF_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmCPF_PERFCOUNTER0_LO 0x300a ++#define mmCPF_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmCPF_PERFCOUNTER0_HI 0x300b ++#define mmCPF_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmCPF_LATENCY_STATS_DATA 0x300c ++#define mmCPF_LATENCY_STATS_DATA_BASE_IDX 1 ++#define mmCPG_LATENCY_STATS_DATA 0x300d ++#define mmCPG_LATENCY_STATS_DATA_BASE_IDX 1 ++#define mmCPC_LATENCY_STATS_DATA 0x300e ++#define mmCPC_LATENCY_STATS_DATA_BASE_IDX 1 ++#define mmGRBM_PERFCOUNTER0_LO 0x3040 ++#define mmGRBM_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmGRBM_PERFCOUNTER0_HI 0x3041 ++#define mmGRBM_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmGRBM_PERFCOUNTER1_LO 0x3043 ++#define mmGRBM_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmGRBM_PERFCOUNTER1_HI 0x3044 ++#define mmGRBM_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmGRBM_SE0_PERFCOUNTER_LO 0x3045 ++#define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 ++#define mmGRBM_SE0_PERFCOUNTER_HI 0x3046 ++#define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 ++#define mmGRBM_SE1_PERFCOUNTER_LO 0x3047 ++#define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 ++#define mmGRBM_SE1_PERFCOUNTER_HI 0x3048 ++#define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 ++#define mmGRBM_SE2_PERFCOUNTER_LO 0x3049 ++#define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 ++#define mmGRBM_SE2_PERFCOUNTER_HI 0x304a ++#define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 ++#define mmGRBM_SE3_PERFCOUNTER_LO 0x304b ++#define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 ++#define mmGRBM_SE3_PERFCOUNTER_HI 0x304c ++#define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 ++#define mmWD_PERFCOUNTER0_LO 0x3080 ++#define mmWD_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmWD_PERFCOUNTER0_HI 0x3081 ++#define mmWD_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmWD_PERFCOUNTER1_LO 0x3082 ++#define mmWD_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmWD_PERFCOUNTER1_HI 0x3083 ++#define mmWD_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmWD_PERFCOUNTER2_LO 0x3084 ++#define mmWD_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmWD_PERFCOUNTER2_HI 0x3085 ++#define mmWD_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmWD_PERFCOUNTER3_LO 0x3086 ++#define mmWD_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmWD_PERFCOUNTER3_HI 0x3087 ++#define mmWD_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmIA_PERFCOUNTER0_LO 0x3088 ++#define mmIA_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmIA_PERFCOUNTER0_HI 0x3089 ++#define mmIA_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmIA_PERFCOUNTER1_LO 0x308a ++#define mmIA_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmIA_PERFCOUNTER1_HI 0x308b ++#define mmIA_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmIA_PERFCOUNTER2_LO 0x308c ++#define mmIA_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmIA_PERFCOUNTER2_HI 0x308d ++#define mmIA_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmIA_PERFCOUNTER3_LO 0x308e ++#define mmIA_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmIA_PERFCOUNTER3_HI 0x308f ++#define mmIA_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER0_LO 0x3090 ++#define mmVGT_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER0_HI 0x3091 ++#define mmVGT_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER1_LO 0x3092 ++#define mmVGT_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER1_HI 0x3093 ++#define mmVGT_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER2_LO 0x3094 ++#define mmVGT_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER2_HI 0x3095 ++#define mmVGT_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER3_LO 0x3096 ++#define mmVGT_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER3_HI 0x3097 ++#define mmVGT_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER0_LO 0x3100 ++#define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER0_HI 0x3101 ++#define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER1_LO 0x3102 ++#define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER1_HI 0x3103 ++#define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER2_LO 0x3104 ++#define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER2_HI 0x3105 ++#define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER3_LO 0x3106 ++#define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER3_HI 0x3107 ++#define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER0_LO 0x3140 ++#define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER0_HI 0x3141 ++#define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER1_LO 0x3142 ++#define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER1_HI 0x3143 ++#define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER2_LO 0x3144 ++#define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER2_HI 0x3145 ++#define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER3_LO 0x3146 ++#define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER3_HI 0x3147 ++#define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER4_LO 0x3148 ++#define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER4_HI 0x3149 ++#define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER5_LO 0x314a ++#define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER5_HI 0x314b ++#define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER6_LO 0x314c ++#define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER6_HI 0x314d ++#define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER7_LO 0x314e ++#define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER7_HI 0x314f ++#define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER0_HI 0x3180 ++#define mmSPI_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER0_LO 0x3181 ++#define mmSPI_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER1_HI 0x3182 ++#define mmSPI_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER1_LO 0x3183 ++#define mmSPI_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER2_HI 0x3184 ++#define mmSPI_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER2_LO 0x3185 ++#define mmSPI_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER3_HI 0x3186 ++#define mmSPI_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER3_LO 0x3187 ++#define mmSPI_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER4_HI 0x3188 ++#define mmSPI_PERFCOUNTER4_HI_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER4_LO 0x3189 ++#define mmSPI_PERFCOUNTER4_LO_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER5_HI 0x318a ++#define mmSPI_PERFCOUNTER5_HI_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER5_LO 0x318b ++#define mmSPI_PERFCOUNTER5_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER0_LO 0x31c0 ++#define mmSQ_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER0_HI 0x31c1 ++#define mmSQ_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER1_LO 0x31c2 ++#define mmSQ_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER1_HI 0x31c3 ++#define mmSQ_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER2_LO 0x31c4 ++#define mmSQ_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER2_HI 0x31c5 ++#define mmSQ_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER3_LO 0x31c6 ++#define mmSQ_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER3_HI 0x31c7 ++#define mmSQ_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER4_LO 0x31c8 ++#define mmSQ_PERFCOUNTER4_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER4_HI 0x31c9 ++#define mmSQ_PERFCOUNTER4_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER5_LO 0x31ca ++#define mmSQ_PERFCOUNTER5_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER5_HI 0x31cb ++#define mmSQ_PERFCOUNTER5_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER6_LO 0x31cc ++#define mmSQ_PERFCOUNTER6_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER6_HI 0x31cd ++#define mmSQ_PERFCOUNTER6_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER7_LO 0x31ce ++#define mmSQ_PERFCOUNTER7_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER7_HI 0x31cf ++#define mmSQ_PERFCOUNTER7_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER8_LO 0x31d0 ++#define mmSQ_PERFCOUNTER8_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER8_HI 0x31d1 ++#define mmSQ_PERFCOUNTER8_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER9_LO 0x31d2 ++#define mmSQ_PERFCOUNTER9_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER9_HI 0x31d3 ++#define mmSQ_PERFCOUNTER9_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER10_LO 0x31d4 ++#define mmSQ_PERFCOUNTER10_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER10_HI 0x31d5 ++#define mmSQ_PERFCOUNTER10_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER11_LO 0x31d6 ++#define mmSQ_PERFCOUNTER11_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER11_HI 0x31d7 ++#define mmSQ_PERFCOUNTER11_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER12_LO 0x31d8 ++#define mmSQ_PERFCOUNTER12_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER12_HI 0x31d9 ++#define mmSQ_PERFCOUNTER12_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER13_LO 0x31da ++#define mmSQ_PERFCOUNTER13_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER13_HI 0x31db ++#define mmSQ_PERFCOUNTER13_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER14_LO 0x31dc ++#define mmSQ_PERFCOUNTER14_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER14_HI 0x31dd ++#define mmSQ_PERFCOUNTER14_HI_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER15_LO 0x31de ++#define mmSQ_PERFCOUNTER15_LO_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER15_HI 0x31df ++#define mmSQ_PERFCOUNTER15_HI_BASE_IDX 1 ++#define mmSX_PERFCOUNTER0_LO 0x3240 ++#define mmSX_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmSX_PERFCOUNTER0_HI 0x3241 ++#define mmSX_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmSX_PERFCOUNTER1_LO 0x3242 ++#define mmSX_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmSX_PERFCOUNTER1_HI 0x3243 ++#define mmSX_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmSX_PERFCOUNTER2_LO 0x3244 ++#define mmSX_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmSX_PERFCOUNTER2_HI 0x3245 ++#define mmSX_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmSX_PERFCOUNTER3_LO 0x3246 ++#define mmSX_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmSX_PERFCOUNTER3_HI 0x3247 ++#define mmSX_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER0_LO 0x3280 ++#define mmGDS_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER0_HI 0x3281 ++#define mmGDS_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER1_LO 0x3282 ++#define mmGDS_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER1_HI 0x3283 ++#define mmGDS_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER2_LO 0x3284 ++#define mmGDS_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER2_HI 0x3285 ++#define mmGDS_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER3_LO 0x3286 ++#define mmGDS_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER3_HI 0x3287 ++#define mmGDS_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmTA_PERFCOUNTER0_LO 0x32c0 ++#define mmTA_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmTA_PERFCOUNTER0_HI 0x32c1 ++#define mmTA_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmTA_PERFCOUNTER1_LO 0x32c2 ++#define mmTA_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmTA_PERFCOUNTER1_HI 0x32c3 ++#define mmTA_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmTD_PERFCOUNTER0_LO 0x3300 ++#define mmTD_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmTD_PERFCOUNTER0_HI 0x3301 ++#define mmTD_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmTD_PERFCOUNTER1_LO 0x3302 ++#define mmTD_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmTD_PERFCOUNTER1_HI 0x3303 ++#define mmTD_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER0_LO 0x3340 ++#define mmTCP_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER0_HI 0x3341 ++#define mmTCP_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER1_LO 0x3342 ++#define mmTCP_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER1_HI 0x3343 ++#define mmTCP_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER2_LO 0x3344 ++#define mmTCP_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER2_HI 0x3345 ++#define mmTCP_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER3_LO 0x3346 ++#define mmTCP_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER3_HI 0x3347 ++#define mmTCP_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER0_LO 0x3380 ++#define mmTCC_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER0_HI 0x3381 ++#define mmTCC_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER1_LO 0x3382 ++#define mmTCC_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER1_HI 0x3383 ++#define mmTCC_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER2_LO 0x3384 ++#define mmTCC_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER2_HI 0x3385 ++#define mmTCC_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER3_LO 0x3386 ++#define mmTCC_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER3_HI 0x3387 ++#define mmTCC_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER0_LO 0x3390 ++#define mmTCA_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER0_HI 0x3391 ++#define mmTCA_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER1_LO 0x3392 ++#define mmTCA_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER1_HI 0x3393 ++#define mmTCA_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER2_LO 0x3394 ++#define mmTCA_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER2_HI 0x3395 ++#define mmTCA_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER3_LO 0x3396 ++#define mmTCA_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER3_HI 0x3397 ++#define mmTCA_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmCB_PERFCOUNTER0_LO 0x3406 ++#define mmCB_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmCB_PERFCOUNTER0_HI 0x3407 ++#define mmCB_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmCB_PERFCOUNTER1_LO 0x3408 ++#define mmCB_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmCB_PERFCOUNTER1_HI 0x3409 ++#define mmCB_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmCB_PERFCOUNTER2_LO 0x340a ++#define mmCB_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmCB_PERFCOUNTER2_HI 0x340b ++#define mmCB_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmCB_PERFCOUNTER3_LO 0x340c ++#define mmCB_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmCB_PERFCOUNTER3_HI 0x340d ++#define mmCB_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmDB_PERFCOUNTER0_LO 0x3440 ++#define mmDB_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmDB_PERFCOUNTER0_HI 0x3441 ++#define mmDB_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmDB_PERFCOUNTER1_LO 0x3442 ++#define mmDB_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmDB_PERFCOUNTER1_HI 0x3443 ++#define mmDB_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmDB_PERFCOUNTER2_LO 0x3444 ++#define mmDB_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmDB_PERFCOUNTER2_HI 0x3445 ++#define mmDB_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmDB_PERFCOUNTER3_LO 0x3446 ++#define mmDB_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmDB_PERFCOUNTER3_HI 0x3447 ++#define mmDB_PERFCOUNTER3_HI_BASE_IDX 1 ++#define mmRLC_PERFCOUNTER0_LO 0x3480 ++#define mmRLC_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmRLC_PERFCOUNTER0_HI 0x3481 ++#define mmRLC_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmRLC_PERFCOUNTER1_LO 0x3482 ++#define mmRLC_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmRLC_PERFCOUNTER1_HI 0x3483 ++#define mmRLC_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER0_LO 0x34c0 ++#define mmRMI_PERFCOUNTER0_LO_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER0_HI 0x34c1 ++#define mmRMI_PERFCOUNTER0_HI_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER1_LO 0x34c2 ++#define mmRMI_PERFCOUNTER1_LO_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER1_HI 0x34c3 ++#define mmRMI_PERFCOUNTER1_HI_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER2_LO 0x34c4 ++#define mmRMI_PERFCOUNTER2_LO_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER2_HI 0x34c5 ++#define mmRMI_PERFCOUNTER2_HI_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER3_LO 0x34c6 ++#define mmRMI_PERFCOUNTER3_LO_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER3_HI 0x34c7 ++#define mmRMI_PERFCOUNTER3_HI_BASE_IDX 1 ++ ++ ++// addressBlock: gc_utcl2_atcl2pfcntrdec ++// base address: 0x35400 ++#define mmATC_L2_PERFCOUNTER_LO 0x3500 ++#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 1 ++#define mmATC_L2_PERFCOUNTER_HI 0x3501 ++#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 1 ++ ++ ++// addressBlock: gc_utcl2_vml2prdec ++// base address: 0x35420 ++#define mmMC_VM_L2_PERFCOUNTER_LO 0x3508 ++#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER_HI 0x3509 ++#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 ++ ++ ++// addressBlock: gc_perfsdec ++// base address: 0x36000 ++#define mmCPG_PERFCOUNTER1_SELECT 0x3800 ++#define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmCPG_PERFCOUNTER0_SELECT1 0x3801 ++#define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmCPG_PERFCOUNTER0_SELECT 0x3802 ++#define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmCPC_PERFCOUNTER1_SELECT 0x3803 ++#define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmCPC_PERFCOUNTER0_SELECT1 0x3804 ++#define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmCPF_PERFCOUNTER1_SELECT 0x3805 ++#define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmCPF_PERFCOUNTER0_SELECT1 0x3806 ++#define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmCPF_PERFCOUNTER0_SELECT 0x3807 ++#define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmCP_PERFMON_CNTL 0x3808 ++#define mmCP_PERFMON_CNTL_BASE_IDX 1 ++#define mmCPC_PERFCOUNTER0_SELECT 0x3809 ++#define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a ++#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 ++#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b ++#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 ++#define mmCPF_LATENCY_STATS_SELECT 0x380c ++#define mmCPF_LATENCY_STATS_SELECT_BASE_IDX 1 ++#define mmCPG_LATENCY_STATS_SELECT 0x380d ++#define mmCPG_LATENCY_STATS_SELECT_BASE_IDX 1 ++#define mmCPC_LATENCY_STATS_SELECT 0x380e ++#define mmCPC_LATENCY_STATS_SELECT_BASE_IDX 1 ++#define mmCP_DRAW_OBJECT 0x3810 ++#define mmCP_DRAW_OBJECT_BASE_IDX 1 ++#define mmCP_DRAW_OBJECT_COUNTER 0x3811 ++#define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 ++#define mmCP_DRAW_WINDOW_MASK_HI 0x3812 ++#define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 ++#define mmCP_DRAW_WINDOW_HI 0x3813 ++#define mmCP_DRAW_WINDOW_HI_BASE_IDX 1 ++#define mmCP_DRAW_WINDOW_LO 0x3814 ++#define mmCP_DRAW_WINDOW_LO_BASE_IDX 1 ++#define mmCP_DRAW_WINDOW_CNTL 0x3815 ++#define mmCP_DRAW_WINDOW_CNTL_BASE_IDX 1 ++#define mmGRBM_PERFCOUNTER0_SELECT 0x3840 ++#define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmGRBM_PERFCOUNTER1_SELECT 0x3841 ++#define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x3842 ++#define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 ++#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x3843 ++#define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 ++#define mmGRBM_SE2_PERFCOUNTER_SELECT 0x3844 ++#define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 ++#define mmGRBM_SE3_PERFCOUNTER_SELECT 0x3845 ++#define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 ++#define mmWD_PERFCOUNTER0_SELECT 0x3880 ++#define mmWD_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmWD_PERFCOUNTER1_SELECT 0x3881 ++#define mmWD_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmWD_PERFCOUNTER2_SELECT 0x3882 ++#define mmWD_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmWD_PERFCOUNTER3_SELECT 0x3883 ++#define mmWD_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmIA_PERFCOUNTER0_SELECT 0x3884 ++#define mmIA_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmIA_PERFCOUNTER1_SELECT 0x3885 ++#define mmIA_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmIA_PERFCOUNTER2_SELECT 0x3886 ++#define mmIA_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmIA_PERFCOUNTER3_SELECT 0x3887 ++#define mmIA_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmIA_PERFCOUNTER0_SELECT1 0x3888 ++#define mmIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER0_SELECT 0x388c ++#define mmVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER1_SELECT 0x388d ++#define mmVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER2_SELECT 0x388e ++#define mmVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER3_SELECT 0x388f ++#define mmVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER0_SELECT1 0x3890 ++#define mmVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER1_SELECT1 0x3891 ++#define mmVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmVGT_PERFCOUNTER_SEID_MASK 0x3894 ++#define mmVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER0_SELECT 0x3900 ++#define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER0_SELECT1 0x3901 ++#define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER1_SELECT 0x3902 ++#define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER1_SELECT1 0x3903 ++#define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER2_SELECT 0x3904 ++#define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmPA_SU_PERFCOUNTER3_SELECT 0x3905 ++#define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER0_SELECT 0x3940 ++#define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER0_SELECT1 0x3941 ++#define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER1_SELECT 0x3942 ++#define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER2_SELECT 0x3943 ++#define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER3_SELECT 0x3944 ++#define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER4_SELECT 0x3945 ++#define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER5_SELECT 0x3946 ++#define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER6_SELECT 0x3947 ++#define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 ++#define mmPA_SC_PERFCOUNTER7_SELECT 0x3948 ++#define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER0_SELECT 0x3980 ++#define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER1_SELECT 0x3981 ++#define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER2_SELECT 0x3982 ++#define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER3_SELECT 0x3983 ++#define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER0_SELECT1 0x3984 ++#define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER1_SELECT1 0x3985 ++#define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER2_SELECT1 0x3986 ++#define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER3_SELECT1 0x3987 ++#define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER4_SELECT 0x3988 ++#define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER5_SELECT 0x3989 ++#define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 ++#define mmSPI_PERFCOUNTER_BINS 0x398a ++#define mmSPI_PERFCOUNTER_BINS_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER0_SELECT 0x39c0 ++#define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER1_SELECT 0x39c1 ++#define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER2_SELECT 0x39c2 ++#define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER3_SELECT 0x39c3 ++#define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER4_SELECT 0x39c4 ++#define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER5_SELECT 0x39c5 ++#define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER6_SELECT 0x39c6 ++#define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER7_SELECT 0x39c7 ++#define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER8_SELECT 0x39c8 ++#define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER9_SELECT 0x39c9 ++#define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER10_SELECT 0x39ca ++#define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER11_SELECT 0x39cb ++#define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER12_SELECT 0x39cc ++#define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER13_SELECT 0x39cd ++#define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER14_SELECT 0x39ce ++#define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER15_SELECT 0x39cf ++#define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER_CTRL 0x39e0 ++#define mmSQ_PERFCOUNTER_CTRL_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER_MASK 0x39e1 ++#define mmSQ_PERFCOUNTER_MASK_BASE_IDX 1 ++#define mmSQ_PERFCOUNTER_CTRL2 0x39e2 ++#define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 ++#define mmSX_PERFCOUNTER0_SELECT 0x3a40 ++#define mmSX_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmSX_PERFCOUNTER1_SELECT 0x3a41 ++#define mmSX_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmSX_PERFCOUNTER2_SELECT 0x3a42 ++#define mmSX_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmSX_PERFCOUNTER3_SELECT 0x3a43 ++#define mmSX_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmSX_PERFCOUNTER0_SELECT1 0x3a44 ++#define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmSX_PERFCOUNTER1_SELECT1 0x3a45 ++#define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER0_SELECT 0x3a80 ++#define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER1_SELECT 0x3a81 ++#define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER2_SELECT 0x3a82 ++#define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER3_SELECT 0x3a83 ++#define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmGDS_PERFCOUNTER0_SELECT1 0x3a84 ++#define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmTA_PERFCOUNTER0_SELECT 0x3ac0 ++#define mmTA_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmTA_PERFCOUNTER0_SELECT1 0x3ac1 ++#define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmTA_PERFCOUNTER1_SELECT 0x3ac2 ++#define mmTA_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmTD_PERFCOUNTER0_SELECT 0x3b00 ++#define mmTD_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmTD_PERFCOUNTER0_SELECT1 0x3b01 ++#define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmTD_PERFCOUNTER1_SELECT 0x3b02 ++#define mmTD_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER0_SELECT 0x3b40 ++#define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER0_SELECT1 0x3b41 ++#define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER1_SELECT 0x3b42 ++#define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER1_SELECT1 0x3b43 ++#define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER2_SELECT 0x3b44 ++#define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmTCP_PERFCOUNTER3_SELECT 0x3b45 ++#define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER0_SELECT 0x3b80 ++#define mmTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER0_SELECT1 0x3b81 ++#define mmTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER1_SELECT 0x3b82 ++#define mmTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER1_SELECT1 0x3b83 ++#define mmTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER2_SELECT 0x3b84 ++#define mmTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmTCC_PERFCOUNTER3_SELECT 0x3b85 ++#define mmTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER0_SELECT 0x3b90 ++#define mmTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER0_SELECT1 0x3b91 ++#define mmTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER1_SELECT 0x3b92 ++#define mmTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER1_SELECT1 0x3b93 ++#define mmTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER2_SELECT 0x3b94 ++#define mmTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmTCA_PERFCOUNTER3_SELECT 0x3b95 ++#define mmTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmCB_PERFCOUNTER_FILTER 0x3c00 ++#define mmCB_PERFCOUNTER_FILTER_BASE_IDX 1 ++#define mmCB_PERFCOUNTER0_SELECT 0x3c01 ++#define mmCB_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmCB_PERFCOUNTER0_SELECT1 0x3c02 ++#define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmCB_PERFCOUNTER1_SELECT 0x3c03 ++#define mmCB_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmCB_PERFCOUNTER2_SELECT 0x3c04 ++#define mmCB_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmCB_PERFCOUNTER3_SELECT 0x3c05 ++#define mmCB_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmDB_PERFCOUNTER0_SELECT 0x3c40 ++#define mmDB_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmDB_PERFCOUNTER0_SELECT1 0x3c41 ++#define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmDB_PERFCOUNTER1_SELECT 0x3c42 ++#define mmDB_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmDB_PERFCOUNTER1_SELECT1 0x3c43 ++#define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 ++#define mmDB_PERFCOUNTER2_SELECT 0x3c44 ++#define mmDB_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmDB_PERFCOUNTER3_SELECT 0x3c46 ++#define mmDB_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmRLC_SPM_PERFMON_CNTL 0x3c80 ++#define mmRLC_SPM_PERFMON_CNTL_BASE_IDX 1 ++#define mmRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 ++#define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 ++#define mmRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 ++#define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 ++#define mmRLC_SPM_PERFMON_RING_SIZE 0x3c83 ++#define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 ++#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c84 ++#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 ++#define mmRLC_SPM_SE_MUXSEL_ADDR 0x3c85 ++#define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 ++#define mmRLC_SPM_SE_MUXSEL_DATA 0x3c86 ++#define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 ++#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0x3c87 ++#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0x3c88 ++#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0x3c89 ++#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0x3c8a ++#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0x3c8b ++#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0x3c8c ++#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0x3c8d ++#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0x3c8e ++#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0x3c90 ++#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0x3c91 ++#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0x3c92 ++#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0x3c93 ++#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0x3c94 ++#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0x3c95 ++#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0x3c96 ++#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0x3c97 ++#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0x3c98 ++#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0x3c9a ++#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c9b ++#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 ++#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c9c ++#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 ++#define mmRLC_SPM_RING_RDPTR 0x3c9d ++#define mmRLC_SPM_RING_RDPTR_BASE_IDX 1 ++#define mmRLC_SPM_SEGMENT_THRESHOLD 0x3c9e ++#define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 ++#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0x3ca3 ++#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 ++#define mmRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0x3ca4 ++#define mmRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1 ++#define mmRLC_PERFMON_CLK_CNTL_UCODE 0x3cbe ++#define mmRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 ++#define mmRLC_PERFMON_CLK_CNTL 0x3cbf ++#define mmRLC_PERFMON_CLK_CNTL_BASE_IDX 1 ++#define mmRLC_PERFMON_CNTL 0x3cc0 ++#define mmRLC_PERFMON_CNTL_BASE_IDX 1 ++#define mmRLC_PERFCOUNTER0_SELECT 0x3cc1 ++#define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmRLC_PERFCOUNTER1_SELECT 0x3cc2 ++#define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 ++#define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 ++#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 ++#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 ++#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 ++#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 ++#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 ++#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 ++#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 ++#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER0_SELECT 0x3d00 ++#define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER0_SELECT1 0x3d01 ++#define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER1_SELECT 0x3d02 ++#define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER2_SELECT 0x3d03 ++#define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER2_SELECT1 0x3d04 ++#define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 ++#define mmRMI_PERFCOUNTER3_SELECT 0x3d05 ++#define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 ++#define mmRMI_PERF_COUNTER_CNTL 0x3d06 ++#define mmRMI_PERF_COUNTER_CNTL_BASE_IDX 1 ++ ++ ++// addressBlock: gc_utcl2_atcl2pfcntldec ++// base address: 0x37500 ++#define mmATC_L2_PERFCOUNTER0_CFG 0x3d40 ++#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 ++#define mmATC_L2_PERFCOUNTER1_CFG 0x3d41 ++#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 ++#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x3d42 ++#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 ++ ++ ++// addressBlock: gc_utcl2_vml2pldec ++// base address: 0x37530 ++#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x3d4c ++#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x3d4d ++#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x3d4e ++#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x3d4f ++#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x3d50 ++#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x3d51 ++#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x3d52 ++#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x3d53 ++#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 ++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d54 ++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 ++ ++ ++// addressBlock: gc_rlcpdec ++// base address: 0x3b000 ++#define mmRLC_CNTL 0x4c00 ++#define mmRLC_CNTL_BASE_IDX 1 ++#define mmRLC_STAT 0x4c04 ++#define mmRLC_STAT_BASE_IDX 1 ++#define mmRLC_SAFE_MODE 0x4c05 ++#define mmRLC_SAFE_MODE_BASE_IDX 1 ++#define mmRLC_MEM_SLP_CNTL 0x4c06 ++#define mmRLC_MEM_SLP_CNTL_BASE_IDX 1 ++#define mmSMU_RLC_RESPONSE 0x4c07 ++#define mmSMU_RLC_RESPONSE_BASE_IDX 1 ++#define mmRLC_RLCV_SAFE_MODE 0x4c08 ++#define mmRLC_RLCV_SAFE_MODE_BASE_IDX 1 ++#define mmRLC_SMU_SAFE_MODE 0x4c09 ++#define mmRLC_SMU_SAFE_MODE_BASE_IDX 1 ++#define mmRLC_RLCV_COMMAND 0x4c0a ++#define mmRLC_RLCV_COMMAND_BASE_IDX 1 ++#define mmRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c ++#define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 ++#define mmRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d ++#define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 ++#define mmRLC_GPM_TIMER_INT_0 0x4c0e ++#define mmRLC_GPM_TIMER_INT_0_BASE_IDX 1 ++#define mmRLC_GPM_TIMER_INT_1 0x4c0f ++#define mmRLC_GPM_TIMER_INT_1_BASE_IDX 1 ++#define mmRLC_GPM_TIMER_INT_2 0x4c10 ++#define mmRLC_GPM_TIMER_INT_2_BASE_IDX 1 ++#define mmRLC_GPM_TIMER_CTRL 0x4c11 ++#define mmRLC_GPM_TIMER_CTRL_BASE_IDX 1 ++#define mmRLC_LB_CNTR_MAX 0x4c12 ++#define mmRLC_LB_CNTR_MAX_BASE_IDX 1 ++#define mmRLC_GPM_TIMER_STAT 0x4c13 ++#define mmRLC_GPM_TIMER_STAT_BASE_IDX 1 ++#define mmRLC_GPM_TIMER_INT_3 0x4c15 ++#define mmRLC_GPM_TIMER_INT_3_BASE_IDX 1 ++#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1 0x4c16 ++#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 ++#define mmRLC_SERDES_NONCU_MASTER_BUSY_1 0x4c17 ++#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX 1 ++#define mmRLC_INT_STAT 0x4c18 ++#define mmRLC_INT_STAT_BASE_IDX 1 ++#define mmRLC_LB_CNTL 0x4c19 ++#define mmRLC_LB_CNTL_BASE_IDX 1 ++#define mmRLC_MGCG_CTRL 0x4c1a ++#define mmRLC_MGCG_CTRL_BASE_IDX 1 ++#define mmRLC_LB_CNTR_INIT 0x4c1b ++#define mmRLC_LB_CNTR_INIT_BASE_IDX 1 ++#define mmRLC_LOAD_BALANCE_CNTR 0x4c1c ++#define mmRLC_LOAD_BALANCE_CNTR_BASE_IDX 1 ++#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e ++#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 ++#define mmRLC_PG_DELAY_2 0x4c1f ++#define mmRLC_PG_DELAY_2_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 ++#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 ++#define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 ++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 ++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 ++#define mmRLC_UCODE_CNTL 0x4c27 ++#define mmRLC_UCODE_CNTL_BASE_IDX 1 ++#define mmRLC_GPM_THREAD_RESET 0x4c28 ++#define mmRLC_GPM_THREAD_RESET_BASE_IDX 1 ++#define mmRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 ++#define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 ++#define mmRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a ++#define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 ++#define mmRLC_FIREWALL_VIOLATION 0x4c2b ++#define mmRLC_FIREWALL_VIOLATION_BASE_IDX 1 ++#define mmRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 ++#define mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 ++#define mmRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 ++#define mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 ++#define mmRLC_CLK_COUNT_REFCLK_LSB 0x4c32 ++#define mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 ++#define mmRLC_CLK_COUNT_REFCLK_MSB 0x4c33 ++#define mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 ++#define mmRLC_CLK_COUNT_CTRL 0x4c34 ++#define mmRLC_CLK_COUNT_CTRL_BASE_IDX 1 ++#define mmRLC_CLK_COUNT_STAT 0x4c35 ++#define mmRLC_CLK_COUNT_STAT_BASE_IDX 1 ++#define mmRLC_GPM_STAT 0x4c40 ++#define mmRLC_GPM_STAT_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_32_RES_SEL 0x4c41 ++#define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_32 0x4c42 ++#define mmRLC_GPU_CLOCK_32_BASE_IDX 1 ++#define mmRLC_PG_CNTL 0x4c43 ++#define mmRLC_PG_CNTL_BASE_IDX 1 ++#define mmRLC_GPM_THREAD_PRIORITY 0x4c44 ++#define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 ++#define mmRLC_GPM_THREAD_ENABLE 0x4c45 ++#define mmRLC_GPM_THREAD_ENABLE_BASE_IDX 1 ++#define mmRLC_CGTT_MGCG_OVERRIDE 0x4c48 ++#define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 ++#define mmRLC_CGCG_CGLS_CTRL 0x4c49 ++#define mmRLC_CGCG_CGLS_CTRL_BASE_IDX 1 ++#define mmRLC_CGCG_RAMP_CTRL 0x4c4a ++#define mmRLC_CGCG_RAMP_CTRL_BASE_IDX 1 ++#define mmRLC_DYN_PG_STATUS 0x4c4b ++#define mmRLC_DYN_PG_STATUS_BASE_IDX 1 ++#define mmRLC_DYN_PG_REQUEST 0x4c4c ++#define mmRLC_DYN_PG_REQUEST_BASE_IDX 1 ++#define mmRLC_PG_DELAY 0x4c4d ++#define mmRLC_PG_DELAY_BASE_IDX 1 ++#define mmRLC_CU_STATUS 0x4c4e ++#define mmRLC_CU_STATUS_BASE_IDX 1 ++#define mmRLC_LB_INIT_CU_MASK 0x4c4f ++#define mmRLC_LB_INIT_CU_MASK_BASE_IDX 1 ++#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x4c50 ++#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX 1 ++#define mmRLC_LB_PARAMS 0x4c51 ++#define mmRLC_LB_PARAMS_BASE_IDX 1 ++#define mmRLC_THREAD1_DELAY 0x4c52 ++#define mmRLC_THREAD1_DELAY_BASE_IDX 1 ++#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x4c53 ++#define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 1 ++#define mmRLC_MAX_PG_CU 0x4c54 ++#define mmRLC_MAX_PG_CU_BASE_IDX 1 ++#define mmRLC_AUTO_PG_CTRL 0x4c55 ++#define mmRLC_AUTO_PG_CTRL_BASE_IDX 1 ++#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x4c56 ++#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 1 ++#define mmRLC_SERDES_RD_PENDING 0x4c58 ++#define mmRLC_SERDES_RD_PENDING_BASE_IDX 1 ++#define mmRLC_SERDES_RD_MASTER_INDEX 0x4c59 ++#define mmRLC_SERDES_RD_MASTER_INDEX_BASE_IDX 1 ++#define mmRLC_SERDES_RD_DATA_0 0x4c5a ++#define mmRLC_SERDES_RD_DATA_0_BASE_IDX 1 ++#define mmRLC_SERDES_RD_DATA_1 0x4c5b ++#define mmRLC_SERDES_RD_DATA_1_BASE_IDX 1 ++#define mmRLC_SERDES_RD_DATA_2 0x4c5c ++#define mmRLC_SERDES_RD_DATA_2_BASE_IDX 1 ++#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x4c5d ++#define mmRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX 1 ++#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x4c5e ++#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX 1 ++#define mmRLC_SERDES_WR_CTRL 0x4c5f ++#define mmRLC_SERDES_WR_CTRL_BASE_IDX 1 ++#define mmRLC_SERDES_WR_DATA 0x4c60 ++#define mmRLC_SERDES_WR_DATA_BASE_IDX 1 ++#define mmRLC_SERDES_CU_MASTER_BUSY 0x4c61 ++#define mmRLC_SERDES_CU_MASTER_BUSY_BASE_IDX 1 ++#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x4c62 ++#define mmRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_0 0x4c63 ++#define mmRLC_GPM_GENERAL_0_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_1 0x4c64 ++#define mmRLC_GPM_GENERAL_1_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_2 0x4c65 ++#define mmRLC_GPM_GENERAL_2_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_3 0x4c66 ++#define mmRLC_GPM_GENERAL_3_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_4 0x4c67 ++#define mmRLC_GPM_GENERAL_4_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_5 0x4c68 ++#define mmRLC_GPM_GENERAL_5_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_6 0x4c69 ++#define mmRLC_GPM_GENERAL_6_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_7 0x4c6a ++#define mmRLC_GPM_GENERAL_7_BASE_IDX 1 ++#define mmRLC_GPM_SCRATCH_ADDR 0x4c6c ++#define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 ++#define mmRLC_GPM_SCRATCH_DATA 0x4c6d ++#define mmRLC_GPM_SCRATCH_DATA_BASE_IDX 1 ++#define mmRLC_STATIC_PG_STATUS 0x4c6e ++#define mmRLC_STATIC_PG_STATUS_BASE_IDX 1 ++#define mmRLC_SPM_MC_CNTL 0x4c71 ++#define mmRLC_SPM_MC_CNTL_BASE_IDX 1 ++#define mmRLC_SPM_INT_CNTL 0x4c72 ++#define mmRLC_SPM_INT_CNTL_BASE_IDX 1 ++#define mmRLC_SPM_INT_STATUS 0x4c73 ++#define mmRLC_SPM_INT_STATUS_BASE_IDX 1 ++#define mmRLC_SMU_MESSAGE 0x4c76 ++#define mmRLC_SMU_MESSAGE_BASE_IDX 1 ++#define mmRLC_GPM_LOG_SIZE 0x4c77 ++#define mmRLC_GPM_LOG_SIZE_BASE_IDX 1 ++#define mmRLC_PG_DELAY_3 0x4c78 ++#define mmRLC_PG_DELAY_3_BASE_IDX 1 ++#define mmRLC_GPR_REG1 0x4c79 ++#define mmRLC_GPR_REG1_BASE_IDX 1 ++#define mmRLC_GPR_REG2 0x4c7a ++#define mmRLC_GPR_REG2_BASE_IDX 1 ++#define mmRLC_GPM_LOG_CONT 0x4c7b ++#define mmRLC_GPM_LOG_CONT_BASE_IDX 1 ++#define mmRLC_GPM_INT_DISABLE_TH0 0x4c7c ++#define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 ++#define mmRLC_GPM_INT_FORCE_TH0 0x4c7e ++#define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 ++#define mmRLC_GPM_INT_FORCE_TH1 0x4c7f ++#define mmRLC_GPM_INT_FORCE_TH1_BASE_IDX 1 ++#define mmRLC_SRM_CNTL 0x4c80 ++#define mmRLC_SRM_CNTL_BASE_IDX 1 ++#define mmRLC_SRM_ARAM_ADDR 0x4c83 ++#define mmRLC_SRM_ARAM_ADDR_BASE_IDX 1 ++#define mmRLC_SRM_ARAM_DATA 0x4c84 ++#define mmRLC_SRM_ARAM_DATA_BASE_IDX 1 ++#define mmRLC_SRM_DRAM_ADDR 0x4c85 ++#define mmRLC_SRM_DRAM_ADDR_BASE_IDX 1 ++#define mmRLC_SRM_DRAM_DATA 0x4c86 ++#define mmRLC_SRM_DRAM_DATA_BASE_IDX 1 ++#define mmRLC_SRM_GPM_COMMAND 0x4c87 ++#define mmRLC_SRM_GPM_COMMAND_BASE_IDX 1 ++#define mmRLC_SRM_GPM_COMMAND_STATUS 0x4c88 ++#define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 ++#define mmRLC_SRM_RLCV_COMMAND 0x4c89 ++#define mmRLC_SRM_RLCV_COMMAND_BASE_IDX 1 ++#define mmRLC_SRM_RLCV_COMMAND_STATUS 0x4c8a ++#define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b ++#define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c ++#define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d ++#define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e ++#define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f ++#define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 ++#define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 ++#define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 ++#define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 ++#define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 ++#define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 ++#define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 ++#define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 ++#define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 ++#define mmRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a ++#define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 ++#define mmRLC_SRM_STAT 0x4c9b ++#define mmRLC_SRM_STAT_BASE_IDX 1 ++#define mmRLC_SRM_GPM_ABORT 0x4c9c ++#define mmRLC_SRM_GPM_ABORT_BASE_IDX 1 ++#define mmRLC_CSIB_ADDR_LO 0x4ca2 ++#define mmRLC_CSIB_ADDR_LO_BASE_IDX 1 ++#define mmRLC_CSIB_ADDR_HI 0x4ca3 ++#define mmRLC_CSIB_ADDR_HI_BASE_IDX 1 ++#define mmRLC_CSIB_LENGTH 0x4ca4 ++#define mmRLC_CSIB_LENGTH_BASE_IDX 1 ++#define mmRLC_SMU_COMMAND 0x4ca9 ++#define mmRLC_SMU_COMMAND_BASE_IDX 1 ++#define mmRLC_CP_SCHEDULERS 0x4caa ++#define mmRLC_CP_SCHEDULERS_BASE_IDX 1 ++#define mmRLC_SMU_ARGUMENT_1 0x4cab ++#define mmRLC_SMU_ARGUMENT_1_BASE_IDX 1 ++#define mmRLC_SMU_ARGUMENT_2 0x4cac ++#define mmRLC_SMU_ARGUMENT_2_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_8 0x4cad ++#define mmRLC_GPM_GENERAL_8_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_9 0x4cae ++#define mmRLC_GPM_GENERAL_9_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_10 0x4caf ++#define mmRLC_GPM_GENERAL_10_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_11 0x4cb0 ++#define mmRLC_GPM_GENERAL_11_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_12 0x4cb1 ++#define mmRLC_GPM_GENERAL_12_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_CNTL_0 0x4cb2 ++#define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_CNTL_1 0x4cb3 ++#define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_CNTL_2 0x4cb4 ++#define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 ++#define mmRLC_SPM_UTCL1_CNTL 0x4cb5 ++#define mmRLC_SPM_UTCL1_CNTL_BASE_IDX 1 ++#define mmRLC_UTCL1_STATUS_2 0x4cb6 ++#define mmRLC_UTCL1_STATUS_2_BASE_IDX 1 ++#define mmRLC_LB_THR_CONFIG_2 0x4cb8 ++#define mmRLC_LB_THR_CONFIG_2_BASE_IDX 1 ++#define mmRLC_LB_THR_CONFIG_3 0x4cb9 ++#define mmRLC_LB_THR_CONFIG_3_BASE_IDX 1 ++#define mmRLC_LB_THR_CONFIG_4 0x4cba ++#define mmRLC_LB_THR_CONFIG_4_BASE_IDX 1 ++#define mmRLC_SPM_UTCL1_ERROR_1 0x4cbc ++#define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 ++#define mmRLC_SPM_UTCL1_ERROR_2 0x4cbd ++#define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe ++#define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 ++#define mmRLC_LB_THR_CONFIG_1 0x4cbf ++#define mmRLC_LB_THR_CONFIG_1_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 ++#define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 ++#define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 ++#define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 ++#define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 ++#define mmRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 ++#define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 ++#define mmRLC_CGCG_CGLS_CTRL_3D 0x4cc5 ++#define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 ++#define mmRLC_CGCG_RAMP_CTRL_3D 0x4cc6 ++#define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 ++#define mmRLC_SEMAPHORE_0 0x4cc7 ++#define mmRLC_SEMAPHORE_0_BASE_IDX 1 ++#define mmRLC_SEMAPHORE_1 0x4cc8 ++#define mmRLC_SEMAPHORE_1_BASE_IDX 1 ++#define mmRLC_CP_EOF_INT 0x4cca ++#define mmRLC_CP_EOF_INT_BASE_IDX 1 ++#define mmRLC_CP_EOF_INT_CNT 0x4ccb ++#define mmRLC_CP_EOF_INT_CNT_BASE_IDX 1 ++#define mmRLC_SPARE_INT 0x4ccc ++#define mmRLC_SPARE_INT_BASE_IDX 1 ++#define mmRLC_PREWALKER_UTCL1_CNTL 0x4ccd ++#define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX 1 ++#define mmRLC_PREWALKER_UTCL1_TRIG 0x4cce ++#define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX 1 ++#define mmRLC_PREWALKER_UTCL1_ADDR_LSB 0x4ccf ++#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX 1 ++#define mmRLC_PREWALKER_UTCL1_ADDR_MSB 0x4cd0 ++#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX 1 ++#define mmRLC_PREWALKER_UTCL1_SIZE_LSB 0x4cd1 ++#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX 1 ++#define mmRLC_PREWALKER_UTCL1_SIZE_MSB 0x4cd2 ++#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX 1 ++#define mmRLC_DSM_TRIG 0x4cd3 ++#define mmRLC_DSM_TRIG_BASE_IDX 1 ++#define mmRLC_UTCL1_STATUS 0x4cd4 ++#define mmRLC_UTCL1_STATUS_BASE_IDX 1 ++#define mmRLC_R2I_CNTL_0 0x4cd5 ++#define mmRLC_R2I_CNTL_0_BASE_IDX 1 ++#define mmRLC_R2I_CNTL_1 0x4cd6 ++#define mmRLC_R2I_CNTL_1_BASE_IDX 1 ++#define mmRLC_R2I_CNTL_2 0x4cd7 ++#define mmRLC_R2I_CNTL_2_BASE_IDX 1 ++#define mmRLC_R2I_CNTL_3 0x4cd8 ++#define mmRLC_R2I_CNTL_3_BASE_IDX 1 ++#define mmRLC_UTCL2_CNTL 0x4cd9 ++#define mmRLC_UTCL2_CNTL_BASE_IDX 1 ++#define mmRLC_LBPW_CU_STAT 0x4cda ++#define mmRLC_LBPW_CU_STAT_BASE_IDX 1 ++#define mmRLC_DS_CNTL 0x4cdb ++#define mmRLC_DS_CNTL_BASE_IDX 1 ++#define mmRLC_GPM_INT_STAT_TH0 0x4cdc ++#define mmRLC_GPM_INT_STAT_TH0_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_13 0x4cdd ++#define mmRLC_GPM_GENERAL_13_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_14 0x4cde ++#define mmRLC_GPM_GENERAL_14_BASE_IDX 1 ++#define mmRLC_GPM_GENERAL_15 0x4cdf ++#define mmRLC_GPM_GENERAL_15_BASE_IDX 1 ++#define mmRLC_SPARE_INT_1 0x4ce0 ++#define mmRLC_SPARE_INT_1_BASE_IDX 1 ++#define mmRLC_RLCV_SPARE_INT_1 0x4ce1 ++#define mmRLC_RLCV_SPARE_INT_1_BASE_IDX 1 ++#define mmRLC_SEMAPHORE_2 0x4ce3 ++#define mmRLC_SEMAPHORE_2_BASE_IDX 1 ++#define mmRLC_SEMAPHORE_3 0x4ce4 ++#define mmRLC_SEMAPHORE_3_BASE_IDX 1 ++#define mmRLC_SMU_ARGUMENT_3 0x4ce5 ++#define mmRLC_SMU_ARGUMENT_3_BASE_IDX 1 ++#define mmRLC_SMU_ARGUMENT_4 0x4ce6 ++#define mmRLC_SMU_ARGUMENT_4_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_COUNT_LSB_1 0x4ce8 ++#define mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_COUNT_MSB_1 0x4ce9 ++#define mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 ++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea ++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb ++#define mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 ++#define mmRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec ++#define mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 ++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef ++#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 ++#define mmRLC_CPG_STAT_INVAL 0x4d09 ++#define mmRLC_CPG_STAT_INVAL_BASE_IDX 1 ++#define mmRLC_RLCV_SPARE_INT 0x4f30 ++#define mmRLC_RLCV_SPARE_INT_BASE_IDX 1 ++#define mmRLC_SMU_CLK_REQ 0x4f97 ++#define mmRLC_SMU_CLK_REQ_BASE_IDX 1 ++ ++ ++// addressBlock: gc_pwrdec ++// base address: 0x3c000 ++#define mmCGTS_SM_CTRL_REG 0x5000 ++#define mmCGTS_SM_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_RD_CTRL_REG 0x5001 ++#define mmCGTS_RD_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_RD_REG 0x5002 ++#define mmCGTS_RD_REG_BASE_IDX 1 ++#define mmCGTS_TCC_DISABLE 0x5003 ++#define mmCGTS_TCC_DISABLE_BASE_IDX 1 ++#define mmCGTS_USER_TCC_DISABLE 0x5004 ++#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1 ++#define mmCGTS_CU0_SP0_CTRL_REG 0x5008 ++#define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0x5009 ++#define mmCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU0_TA_SQC_CTRL_REG 0x500a ++#define mmCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU0_SP1_CTRL_REG 0x500b ++#define mmCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU0_TD_TCP_CTRL_REG 0x500c ++#define mmCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU1_SP0_CTRL_REG 0x500d ++#define mmCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0x500e ++#define mmCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU1_TA_SQC_CTRL_REG 0x500f ++#define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU1_SP1_CTRL_REG 0x5010 ++#define mmCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU1_TD_TCP_CTRL_REG 0x5011 ++#define mmCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU2_SP0_CTRL_REG 0x5012 ++#define mmCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0x5013 ++#define mmCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU2_TA_SQC_CTRL_REG 0x5014 ++#define mmCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU2_SP1_CTRL_REG 0x5015 ++#define mmCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU2_TD_TCP_CTRL_REG 0x5016 ++#define mmCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU3_SP0_CTRL_REG 0x5017 ++#define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0x5018 ++#define mmCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU3_TA_SQC_CTRL_REG 0x5019 ++#define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU3_SP1_CTRL_REG 0x501a ++#define mmCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU3_TD_TCP_CTRL_REG 0x501b ++#define mmCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU4_SP0_CTRL_REG 0x501c ++#define mmCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0x501d ++#define mmCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU4_TA_SQC_CTRL_REG 0x501e ++#define mmCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU4_SP1_CTRL_REG 0x501f ++#define mmCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU4_TD_TCP_CTRL_REG 0x5020 ++#define mmCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU5_SP0_CTRL_REG 0x5021 ++#define mmCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0x5022 ++#define mmCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU5_TA_SQC_CTRL_REG 0x5023 ++#define mmCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU5_SP1_CTRL_REG 0x5024 ++#define mmCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU5_TD_TCP_CTRL_REG 0x5025 ++#define mmCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU6_SP0_CTRL_REG 0x5026 ++#define mmCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0x5027 ++#define mmCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU6_TA_SQC_CTRL_REG 0x5028 ++#define mmCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU6_SP1_CTRL_REG 0x5029 ++#define mmCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU6_TD_TCP_CTRL_REG 0x502a ++#define mmCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU7_SP0_CTRL_REG 0x502b ++#define mmCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0x502c ++#define mmCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU7_TA_SQC_CTRL_REG 0x502d ++#define mmCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU7_SP1_CTRL_REG 0x502e ++#define mmCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU7_TD_TCP_CTRL_REG 0x502f ++#define mmCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU8_SP0_CTRL_REG 0x5030 ++#define mmCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0x5031 ++#define mmCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU8_TA_SQC_CTRL_REG 0x5032 ++#define mmCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU8_SP1_CTRL_REG 0x5033 ++#define mmCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU8_TD_TCP_CTRL_REG 0x5034 ++#define mmCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU9_SP0_CTRL_REG 0x5035 ++#define mmCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0x5036 ++#define mmCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU9_TA_SQC_CTRL_REG 0x5037 ++#define mmCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU9_SP1_CTRL_REG 0x5038 ++#define mmCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU9_TD_TCP_CTRL_REG 0x5039 ++#define mmCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU10_SP0_CTRL_REG 0x503a ++#define mmCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0x503b ++#define mmCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU10_TA_SQC_CTRL_REG 0x503c ++#define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU10_SP1_CTRL_REG 0x503d ++#define mmCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU10_TD_TCP_CTRL_REG 0x503e ++#define mmCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU11_SP0_CTRL_REG 0x503f ++#define mmCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0x5040 ++#define mmCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU11_TA_SQC_CTRL_REG 0x5041 ++#define mmCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU11_SP1_CTRL_REG 0x5042 ++#define mmCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU11_TD_TCP_CTRL_REG 0x5043 ++#define mmCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU12_SP0_CTRL_REG 0x5044 ++#define mmCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0x5045 ++#define mmCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU12_TA_SQC_CTRL_REG 0x5046 ++#define mmCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU12_SP1_CTRL_REG 0x5047 ++#define mmCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU12_TD_TCP_CTRL_REG 0x5048 ++#define mmCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU13_SP0_CTRL_REG 0x5049 ++#define mmCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0x504a ++#define mmCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU13_TA_SQC_CTRL_REG 0x504b ++#define mmCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU13_SP1_CTRL_REG 0x504c ++#define mmCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU13_TD_TCP_CTRL_REG 0x504d ++#define mmCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU14_SP0_CTRL_REG 0x504e ++#define mmCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0x504f ++#define mmCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU14_TA_SQC_CTRL_REG 0x5050 ++#define mmCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU14_SP1_CTRL_REG 0x5051 ++#define mmCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU14_TD_TCP_CTRL_REG 0x5052 ++#define mmCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU15_SP0_CTRL_REG 0x5053 ++#define mmCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0x5054 ++#define mmCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU15_TA_SQC_CTRL_REG 0x5055 ++#define mmCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU15_SP1_CTRL_REG 0x5056 ++#define mmCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU15_TD_TCP_CTRL_REG 0x5057 ++#define mmCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU0_TCPI_CTRL_REG 0x5058 ++#define mmCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU1_TCPI_CTRL_REG 0x5059 ++#define mmCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU2_TCPI_CTRL_REG 0x505a ++#define mmCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU3_TCPI_CTRL_REG 0x505b ++#define mmCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU4_TCPI_CTRL_REG 0x505c ++#define mmCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU5_TCPI_CTRL_REG 0x505d ++#define mmCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU6_TCPI_CTRL_REG 0x505e ++#define mmCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU7_TCPI_CTRL_REG 0x505f ++#define mmCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU8_TCPI_CTRL_REG 0x5060 ++#define mmCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU9_TCPI_CTRL_REG 0x5061 ++#define mmCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU10_TCPI_CTRL_REG 0x5062 ++#define mmCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU11_TCPI_CTRL_REG 0x5063 ++#define mmCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU12_TCPI_CTRL_REG 0x5064 ++#define mmCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU13_TCPI_CTRL_REG 0x5065 ++#define mmCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU14_TCPI_CTRL_REG 0x5066 ++#define mmCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTS_CU15_TCPI_CTRL_REG 0x5067 ++#define mmCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 ++#define mmCGTT_SPI_PS_CLK_CTRL 0x507d ++#define mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_SPIS_CLK_CTRL 0x507e ++#define mmCGTT_SPIS_CLK_CTRL_BASE_IDX 1 ++#define mmCGTX_SPI_DEBUG_CLK_CTRL 0x507f ++#define mmCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_SPI_CLK_CTRL 0x5080 ++#define mmCGTT_SPI_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_PC_CLK_CTRL 0x5081 ++#define mmCGTT_PC_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_BCI_CLK_CTRL 0x5082 ++#define mmCGTT_BCI_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_VGT_CLK_CTRL 0x5084 ++#define mmCGTT_VGT_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_IA_CLK_CTRL 0x5085 ++#define mmCGTT_IA_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_WD_CLK_CTRL 0x5086 ++#define mmCGTT_WD_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_PA_CLK_CTRL 0x5088 ++#define mmCGTT_PA_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_SC_CLK_CTRL0 0x5089 ++#define mmCGTT_SC_CLK_CTRL0_BASE_IDX 1 ++#define mmCGTT_SC_CLK_CTRL1 0x508a ++#define mmCGTT_SC_CLK_CTRL1_BASE_IDX 1 ++#define mmCGTT_SC_CLK_CTRL2 0x508b ++#define mmCGTT_SC_CLK_CTRL2_BASE_IDX 1 ++#define mmCGTT_SQ_CLK_CTRL 0x508c ++#define mmCGTT_SQ_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_SQG_CLK_CTRL 0x508d ++#define mmCGTT_SQG_CLK_CTRL_BASE_IDX 1 ++#define mmSQ_ALU_CLK_CTRL 0x508e ++#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1 ++#define mmSQ_TEX_CLK_CTRL 0x508f ++#define mmSQ_TEX_CLK_CTRL_BASE_IDX 1 ++#define mmSQ_LDS_CLK_CTRL 0x5090 ++#define mmSQ_LDS_CLK_CTRL_BASE_IDX 1 ++#define mmSQ_POWER_THROTTLE 0x5091 ++#define mmSQ_POWER_THROTTLE_BASE_IDX 1 ++#define mmSQ_POWER_THROTTLE2 0x5092 ++#define mmSQ_POWER_THROTTLE2_BASE_IDX 1 ++#define mmCGTT_SX_CLK_CTRL0 0x5094 ++#define mmCGTT_SX_CLK_CTRL0_BASE_IDX 1 ++#define mmCGTT_SX_CLK_CTRL1 0x5095 ++#define mmCGTT_SX_CLK_CTRL1_BASE_IDX 1 ++#define mmCGTT_SX_CLK_CTRL2 0x5096 ++#define mmCGTT_SX_CLK_CTRL2_BASE_IDX 1 ++#define mmCGTT_SX_CLK_CTRL3 0x5097 ++#define mmCGTT_SX_CLK_CTRL3_BASE_IDX 1 ++#define mmCGTT_SX_CLK_CTRL4 0x5098 ++#define mmCGTT_SX_CLK_CTRL4_BASE_IDX 1 ++#define mmTD_CGTT_CTRL 0x509c ++#define mmTD_CGTT_CTRL_BASE_IDX 1 ++#define mmTA_CGTT_CTRL 0x509d ++#define mmTA_CGTT_CTRL_BASE_IDX 1 ++#define mmCGTT_TCPI_CLK_CTRL 0x509e ++#define mmCGTT_TCPI_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_TCI_CLK_CTRL 0x509f ++#define mmCGTT_TCI_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_GDS_CLK_CTRL 0x50a0 ++#define mmCGTT_GDS_CLK_CTRL_BASE_IDX 1 ++#define mmDB_CGTT_CLK_CTRL_0 0x50a4 ++#define mmDB_CGTT_CLK_CTRL_0_BASE_IDX 1 ++#define mmCB_CGTT_SCLK_CTRL 0x50a8 ++#define mmCB_CGTT_SCLK_CTRL_BASE_IDX 1 ++#define mmTCC_CGTT_SCLK_CTRL 0x50ac ++#define mmTCC_CGTT_SCLK_CTRL_BASE_IDX 1 ++#define mmTCA_CGTT_SCLK_CTRL 0x50ad ++#define mmTCA_CGTT_SCLK_CTRL_BASE_IDX 1 ++#define mmCGTT_CP_CLK_CTRL 0x50b0 ++#define mmCGTT_CP_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_CPF_CLK_CTRL 0x50b1 ++#define mmCGTT_CPF_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_CPC_CLK_CTRL 0x50b2 ++#define mmCGTT_CPC_CLK_CTRL_BASE_IDX 1 ++#define mmCGTT_RLC_CLK_CTRL 0x50b5 ++#define mmCGTT_RLC_CLK_CTRL_BASE_IDX 1 ++#define mmRLC_GFX_RM_CNTL 0x50b6 ++#define mmRLC_GFX_RM_CNTL_BASE_IDX 1 ++#define mmRMI_CGTT_SCLK_CTRL 0x50c0 ++#define mmRMI_CGTT_SCLK_CTRL_BASE_IDX 1 ++#define mmCGTT_TCPF_CLK_CTRL 0x50c1 ++#define mmCGTT_TCPF_CLK_CTRL_BASE_IDX 1 ++#define mmSE_CAC_CGTT_CLK_CTRL 0x50d0 ++#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1 ++#define mmGC_CAC_CGTT_CLK_CTRL 0x50d8 ++#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1 ++#define mmGRBM_CGTT_CLK_CNTL 0x50e0 ++#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 1 ++ ++ ++// addressBlock: gc_ea_pwrdec ++// base address: 0x3c000 ++#define mmGCEA_CGTT_CLK_CTRL 0x50c4 ++#define mmGCEA_CGTT_CLK_CTRL_BASE_IDX 1 ++ ++ ++// addressBlock: gc_utcl2_vmsharedhvdec ++// base address: 0x3ea00 ++#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 ++#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 ++#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 ++#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 ++#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 ++#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 ++#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 ++#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 ++#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 ++#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 ++#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a ++#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b ++#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c ++#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d ++#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e ++#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f ++#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 ++#define mmVM_IOMMU_MMIO_CNTRL_1 0x5a90 ++#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_LO_0 0x5a91 ++#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_LO_1 0x5a92 ++#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_LO_2 0x5a93 ++#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_LO_3 0x5a94 ++#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_HI_0 0x5a95 ++#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_HI_1 0x5a96 ++#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_HI_2 0x5a97 ++#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 1 ++#define mmMC_VM_MARC_BASE_HI_3 0x5a98 ++#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_LO_0 0x5a99 ++#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_LO_1 0x5a9a ++#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_LO_2 0x5a9b ++#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_LO_3 0x5a9c ++#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_HI_0 0x5a9d ++#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_HI_1 0x5a9e ++#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_HI_2 0x5a9f ++#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 ++#define mmMC_VM_MARC_RELOC_HI_3 0x5aa0 ++#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_LO_0 0x5aa1 ++#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_LO_1 0x5aa2 ++#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_LO_2 0x5aa3 ++#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_LO_3 0x5aa4 ++#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_HI_0 0x5aa5 ++#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_HI_1 0x5aa6 ++#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_HI_2 0x5aa7 ++#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 1 ++#define mmMC_VM_MARC_LEN_HI_3 0x5aa8 ++#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 1 ++#define mmVM_IOMMU_CONTROL_REGISTER 0x5aa9 ++#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 ++#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5aaa ++#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL 0x5aab ++#define mmVM_PCIE_ATS_CNTL_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_0 0x5aac ++#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_1 0x5aad ++#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_2 0x5aae ++#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_3 0x5aaf ++#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_4 0x5ab0 ++#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_5 0x5ab1 ++#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_6 0x5ab2 ++#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_7 0x5ab3 ++#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_8 0x5ab4 ++#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_9 0x5ab5 ++#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_10 0x5ab6 ++#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_11 0x5ab7 ++#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_12 0x5ab8 ++#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_13 0x5ab9 ++#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_14 0x5aba ++#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 ++#define mmVM_PCIE_ATS_CNTL_VF_15 0x5abb ++#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 ++#define mmUTCL2_CGTT_CLK_CTRL 0x5abc ++#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 ++#define mmMC_SHARED_ACTIVE_FCN_ID 0x5abd ++#define mmMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 ++#define mmMC_VM_XGMI_GPUIOV_ENABLE 0x5abe ++#define mmMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 ++ ++ ++// addressBlock: gc_hypdec ++// base address: 0x3e000 ++#define mmCP_HYP_PFP_UCODE_ADDR 0x5814 ++#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_PFP_UCODE_ADDR 0x5814 ++#define mmCP_PFP_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_HYP_PFP_UCODE_DATA 0x5815 ++#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 ++#define mmCP_PFP_UCODE_DATA 0x5815 ++#define mmCP_PFP_UCODE_DATA_BASE_IDX 1 ++#define mmCP_HYP_ME_UCODE_ADDR 0x5816 ++#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_ME_RAM_RADDR 0x5816 ++#define mmCP_ME_RAM_RADDR_BASE_IDX 1 ++#define mmCP_ME_RAM_WADDR 0x5816 ++#define mmCP_ME_RAM_WADDR_BASE_IDX 1 ++#define mmCP_HYP_ME_UCODE_DATA 0x5817 ++#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 ++#define mmCP_ME_RAM_DATA 0x5817 ++#define mmCP_ME_RAM_DATA_BASE_IDX 1 ++#define mmCP_CE_UCODE_ADDR 0x5818 ++#define mmCP_CE_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_HYP_CE_UCODE_ADDR 0x5818 ++#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_CE_UCODE_DATA 0x5819 ++#define mmCP_CE_UCODE_DATA_BASE_IDX 1 ++#define mmCP_HYP_CE_UCODE_DATA 0x5819 ++#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 ++#define mmCP_HYP_MEC1_UCODE_ADDR 0x581a ++#define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_MEC_ME1_UCODE_ADDR 0x581a ++#define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_HYP_MEC1_UCODE_DATA 0x581b ++#define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 ++#define mmCP_MEC_ME1_UCODE_DATA 0x581b ++#define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 ++#define mmCP_HYP_MEC2_UCODE_ADDR 0x581c ++#define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_MEC_ME2_UCODE_ADDR 0x581c ++#define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 ++#define mmCP_HYP_MEC2_UCODE_DATA 0x581d ++#define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 ++#define mmCP_MEC_ME2_UCODE_DATA 0x581d ++#define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 ++#define mmCP_HYP_PFP_UCODE_CHKSUM 0x581e ++#define mmCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX 1 ++#define mmCP_HYP_CE_UCODE_CHKSUM 0x581f ++#define mmCP_HYP_CE_UCODE_CHKSUM_BASE_IDX 1 ++#define mmCP_HYP_ME_UCODE_CHKSUM 0x5820 ++#define mmCP_HYP_ME_UCODE_CHKSUM_BASE_IDX 1 ++#define mmCP_HYP_MEC_ME1_UCODE_CHKSUM 0x5821 ++#define mmCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX 1 ++#define mmCP_HYP_MEC_ME2_UCODE_CHKSUM 0x5822 ++#define mmCP_HYP_MEC_ME2_UCODE_CHKSUM_BASE_IDX 1 ++#define mmRLC_GPM_UCODE_ADDR 0x583c ++#define mmRLC_GPM_UCODE_ADDR_BASE_IDX 1 ++#define mmRLC_GPM_UCODE_DATA 0x583d ++#define mmRLC_GPM_UCODE_DATA_BASE_IDX 1 ++#define mmGRBM_GFX_INDEX_SR_SELECT 0x5a00 ++#define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 ++#define mmGRBM_GFX_INDEX_SR_DATA 0x5a01 ++#define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 ++#define mmGRBM_GFX_CNTL_SR_SELECT 0x5a02 ++#define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 ++#define mmGRBM_GFX_CNTL_SR_DATA 0x5a03 ++#define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 ++#define mmGRBM_CAM_INDEX 0x5a04 ++#define mmGRBM_CAM_INDEX_BASE_IDX 1 ++#define mmGRBM_HYP_CAM_INDEX 0x5a04 ++#define mmGRBM_HYP_CAM_INDEX_BASE_IDX 1 ++#define mmGRBM_CAM_DATA 0x5a05 ++#define mmGRBM_CAM_DATA_BASE_IDX 1 ++#define mmGRBM_HYP_CAM_DATA 0x5a05 ++#define mmGRBM_HYP_CAM_DATA_BASE_IDX 1 ++#define mmRLC_GPU_IOV_VF_ENABLE 0x5b00 ++#define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 ++#define mmRLC_GPU_IOV_CFG_REG6 0x5b06 ++#define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 ++#define mmRLC_GPU_IOV_CFG_REG8 0x5b20 ++#define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 ++#define mmRLC_RLCV_TIMER_INT_0 0x5b25 ++#define mmRLC_RLCV_TIMER_INT_0_BASE_IDX 1 ++#define mmRLC_RLCV_TIMER_CTRL 0x5b26 ++#define mmRLC_RLCV_TIMER_CTRL_BASE_IDX 1 ++#define mmRLC_RLCV_TIMER_STAT 0x5b27 ++#define mmRLC_RLCV_TIMER_STAT_BASE_IDX 1 ++#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a ++#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 ++#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b ++#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 ++#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c ++#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 ++#define mmRLC_GPU_IOV_VF_MASK 0x5b2d ++#define mmRLC_GPU_IOV_VF_MASK_BASE_IDX 1 ++#define mmRLC_HYP_SEMAPHORE_0 0x5b2e ++#define mmRLC_HYP_SEMAPHORE_0_BASE_IDX 1 ++#define mmRLC_HYP_SEMAPHORE_1 0x5b2f ++#define mmRLC_HYP_SEMAPHORE_1_BASE_IDX 1 ++#define mmRLC_CLK_CNTL 0x5b31 ++#define mmRLC_CLK_CNTL_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SCH_BLOCK 0x5b34 ++#define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 ++#define mmRLC_GPU_IOV_CFG_REG1 0x5b35 ++#define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 ++#define mmRLC_GPU_IOV_CFG_REG2 0x5b36 ++#define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 ++#define mmRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 ++#define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SCH_0 0x5b38 ++#define mmRLC_GPU_IOV_SCH_0_BASE_IDX 1 ++#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 ++#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SCH_3 0x5b3a ++#define mmRLC_GPU_IOV_SCH_3_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SCH_1 0x5b3b ++#define mmRLC_GPU_IOV_SCH_1_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SCH_2 0x5b3c ++#define mmRLC_GPU_IOV_SCH_2_BASE_IDX 1 ++#define mmRLC_GPU_IOV_INT_STAT 0x5b3f ++#define mmRLC_GPU_IOV_INT_STAT_BASE_IDX 1 ++#define mmRLC_RLCV_TIMER_INT_1 0x5b40 ++#define mmRLC_RLCV_TIMER_INT_1_BASE_IDX 1 ++#define mmRLC_GPU_IOV_UCODE_ADDR 0x5b42 ++#define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 ++#define mmRLC_GPU_IOV_UCODE_DATA 0x5b43 ++#define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SCRATCH_ADDR 0x5b44 ++#define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SCRATCH_DATA 0x5b45 ++#define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 ++#define mmRLC_GPU_IOV_F32_CNTL 0x5b46 ++#define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 ++#define mmRLC_GPU_IOV_F32_RESET 0x5b47 ++#define mmRLC_GPU_IOV_F32_RESET_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SDMA0_STATUS 0x5b48 ++#define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SDMA1_STATUS 0x5b49 ++#define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SMU_RESPONSE 0x5b4a ++#define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 ++#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c ++#define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 ++#define mmRLC_GPU_IOV_RLC_RESPONSE 0x5b4d ++#define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 ++#define mmRLC_GPU_IOV_INT_DISABLE 0x5b4e ++#define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 ++#define mmRLC_GPU_IOV_INT_FORCE 0x5b4f ++#define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5b50 ++#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 ++#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5b51 ++#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 ++#define mmRLC_HYP_SEMAPHORE_2 0x5b52 ++#define mmRLC_HYP_SEMAPHORE_2_BASE_IDX 1 ++#define mmRLC_HYP_SEMAPHORE_3 0x5b53 ++#define mmRLC_HYP_SEMAPHORE_3_BASE_IDX 1 ++ ++ ++// addressBlock: gccacind ++// base address: 0x0 ++#define ixGC_CAC_CNTL 0x0000 ++#define ixGC_CAC_OVR_SEL 0x0001 ++#define ixGC_CAC_OVR_VAL 0x0002 ++#define ixGC_CAC_WEIGHT_BCI_0 0x0003 ++#define ixGC_CAC_WEIGHT_CB_0 0x0004 ++#define ixGC_CAC_WEIGHT_CB_1 0x0005 ++#define ixGC_CAC_WEIGHT_CP_0 0x0008 ++#define ixGC_CAC_WEIGHT_CP_1 0x0009 ++#define ixGC_CAC_WEIGHT_DB_0 0x000a ++#define ixGC_CAC_WEIGHT_DB_1 0x000b ++#define ixGC_CAC_WEIGHT_GDS_0 0x000e ++#define ixGC_CAC_WEIGHT_GDS_1 0x000f ++#define ixGC_CAC_WEIGHT_IA_0 0x0010 ++#define ixGC_CAC_WEIGHT_LDS_0 0x0011 ++#define ixGC_CAC_WEIGHT_LDS_1 0x0012 ++#define ixGC_CAC_WEIGHT_PA_0 0x0013 ++#define ixGC_CAC_WEIGHT_PC_0 0x0014 ++#define ixGC_CAC_WEIGHT_SC_0 0x0015 ++#define ixGC_CAC_WEIGHT_SPI_0 0x0016 ++#define ixGC_CAC_WEIGHT_SPI_1 0x0017 ++#define ixGC_CAC_WEIGHT_SPI_2 0x0018 ++#define ixGC_CAC_WEIGHT_SQ_0 0x001a ++#define ixGC_CAC_WEIGHT_SQ_1 0x001b ++#define ixGC_CAC_WEIGHT_SQ_2 0x001c ++#define ixGC_CAC_WEIGHT_SQ_3 0x001d ++#define ixGC_CAC_WEIGHT_SQ_4 0x001e ++#define ixGC_CAC_WEIGHT_SX_0 0x001f ++#define ixGC_CAC_WEIGHT_SXRB_0 0x0020 ++#define ixGC_CAC_WEIGHT_TA_0 0x0021 ++#define ixGC_CAC_WEIGHT_TCC_0 0x0022 ++#define ixGC_CAC_WEIGHT_TCC_1 0x0023 ++#define ixGC_CAC_WEIGHT_TCC_2 0x0024 ++#define ixGC_CAC_WEIGHT_TCP_0 0x0025 ++#define ixGC_CAC_WEIGHT_TCP_1 0x0026 ++#define ixGC_CAC_WEIGHT_TCP_2 0x0027 ++#define ixGC_CAC_WEIGHT_TD_0 0x0028 ++#define ixGC_CAC_WEIGHT_TD_1 0x0029 ++#define ixGC_CAC_WEIGHT_TD_2 0x002a ++#define ixGC_CAC_WEIGHT_VGT_0 0x002b ++#define ixGC_CAC_WEIGHT_VGT_1 0x002c ++#define ixGC_CAC_WEIGHT_WD_0 0x002d ++#define ixGC_CAC_WEIGHT_CU_0 0x0032 ++#define ixGC_CAC_ACC_BCI0 0x0042 ++#define ixGC_CAC_ACC_CB0 0x0043 ++#define ixGC_CAC_ACC_CB1 0x0044 ++#define ixGC_CAC_ACC_CB2 0x0045 ++#define ixGC_CAC_ACC_CB3 0x0046 ++#define ixGC_CAC_ACC_CP0 0x004b ++#define ixGC_CAC_ACC_CP1 0x004c ++#define ixGC_CAC_ACC_CP2 0x004d ++#define ixGC_CAC_ACC_DB0 0x004e ++#define ixGC_CAC_ACC_DB1 0x004f ++#define ixGC_CAC_ACC_DB2 0x0050 ++#define ixGC_CAC_ACC_DB3 0x0051 ++#define ixGC_CAC_ACC_GDS0 0x0056 ++#define ixGC_CAC_ACC_GDS1 0x0057 ++#define ixGC_CAC_ACC_GDS2 0x0058 ++#define ixGC_CAC_ACC_GDS3 0x0059 ++#define ixGC_CAC_ACC_IA0 0x005a ++#define ixGC_CAC_ACC_LDS0 0x005b ++#define ixGC_CAC_ACC_LDS1 0x005c ++#define ixGC_CAC_ACC_LDS2 0x005d ++#define ixGC_CAC_ACC_LDS3 0x005e ++#define ixGC_CAC_ACC_PA0 0x005f ++#define ixGC_CAC_ACC_PA1 0x0060 ++#define ixGC_CAC_ACC_PC0 0x0061 ++#define ixGC_CAC_ACC_SC0 0x0062 ++#define ixGC_CAC_ACC_SPI0 0x0063 ++#define ixGC_CAC_ACC_SPI1 0x0064 ++#define ixGC_CAC_ACC_SPI2 0x0065 ++#define ixGC_CAC_ACC_SPI3 0x0066 ++#define ixGC_CAC_ACC_SPI4 0x0067 ++#define ixGC_CAC_ACC_SPI5 0x0068 ++#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 0x006f ++#define ixGC_CAC_ACC_EA0 0x0070 ++#define ixGC_CAC_ACC_EA1 0x0071 ++#define ixGC_CAC_ACC_EA2 0x0072 ++#define ixGC_CAC_ACC_EA3 0x0073 ++#define ixGC_CAC_ACC_UTCL2_ATCL20 0x0074 ++#define ixGC_CAC_OVRD_EA 0x0075 ++#define ixGC_CAC_OVRD_UTCL2_ATCL2 0x0076 ++#define ixGC_CAC_WEIGHT_EA_0 0x0077 ++#define ixGC_CAC_WEIGHT_EA_1 0x0078 ++#define ixGC_CAC_WEIGHT_RMI_0 0x0079 ++#define ixGC_CAC_ACC_RMI0 0x007a ++#define ixGC_CAC_OVRD_RMI 0x007b ++#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 0x007c ++#define ixGC_CAC_ACC_UTCL2_ATCL21 0x007d ++#define ixGC_CAC_ACC_UTCL2_ATCL22 0x007e ++#define ixGC_CAC_ACC_UTCL2_ATCL23 0x007f ++#define ixGC_CAC_ACC_EA4 0x0080 ++#define ixGC_CAC_ACC_EA5 0x0081 ++#define ixGC_CAC_WEIGHT_EA_2 0x0082 ++#define ixGC_CAC_ACC_SQ0_LOWER 0x0089 ++#define ixGC_CAC_ACC_SQ0_UPPER 0x008a ++#define ixGC_CAC_ACC_SQ1_LOWER 0x008b ++#define ixGC_CAC_ACC_SQ1_UPPER 0x008c ++#define ixGC_CAC_ACC_SQ2_LOWER 0x008d ++#define ixGC_CAC_ACC_SQ2_UPPER 0x008e ++#define ixGC_CAC_ACC_SQ3_LOWER 0x008f ++#define ixGC_CAC_ACC_SQ3_UPPER 0x0090 ++#define ixGC_CAC_ACC_SQ4_LOWER 0x0091 ++#define ixGC_CAC_ACC_SQ4_UPPER 0x0092 ++#define ixGC_CAC_ACC_SQ5_LOWER 0x0093 ++#define ixGC_CAC_ACC_SQ5_UPPER 0x0094 ++#define ixGC_CAC_ACC_SQ6_LOWER 0x0095 ++#define ixGC_CAC_ACC_SQ6_UPPER 0x0096 ++#define ixGC_CAC_ACC_SQ7_LOWER 0x0097 ++#define ixGC_CAC_ACC_SQ7_UPPER 0x0098 ++#define ixGC_CAC_ACC_SQ8_LOWER 0x0099 ++#define ixGC_CAC_ACC_SQ8_UPPER 0x009a ++#define ixGC_CAC_ACC_SX0 0x009b ++#define ixGC_CAC_ACC_SXRB0 0x009c ++#define ixGC_CAC_ACC_SXRB1 0x009d ++#define ixGC_CAC_ACC_TA0 0x009e ++#define ixGC_CAC_ACC_TCC0 0x009f ++#define ixGC_CAC_ACC_TCC1 0x00a0 ++#define ixGC_CAC_ACC_TCC2 0x00a1 ++#define ixGC_CAC_ACC_TCC3 0x00a2 ++#define ixGC_CAC_ACC_TCC4 0x00a3 ++#define ixGC_CAC_ACC_TCP0 0x00a4 ++#define ixGC_CAC_ACC_TCP1 0x00a5 ++#define ixGC_CAC_ACC_TCP2 0x00a6 ++#define ixGC_CAC_ACC_TCP3 0x00a7 ++#define ixGC_CAC_ACC_TCP4 0x00a8 ++#define ixGC_CAC_ACC_TD0 0x00a9 ++#define ixGC_CAC_ACC_TD1 0x00aa ++#define ixGC_CAC_ACC_TD2 0x00ab ++#define ixGC_CAC_ACC_TD3 0x00ac ++#define ixGC_CAC_ACC_TD4 0x00ad ++#define ixGC_CAC_ACC_TD5 0x00ae ++#define ixGC_CAC_ACC_VGT0 0x00af ++#define ixGC_CAC_ACC_VGT1 0x00b0 ++#define ixGC_CAC_ACC_VGT2 0x00b1 ++#define ixGC_CAC_ACC_WD0 0x00b2 ++#define ixGC_CAC_ACC_CU0 0x00ba ++#define ixGC_CAC_ACC_CU1 0x00bb ++#define ixGC_CAC_ACC_CU2 0x00bc ++#define ixGC_CAC_ACC_CU3 0x00bd ++#define ixGC_CAC_ACC_CU4 0x00be ++#define ixGC_CAC_OVRD_BCI 0x00da ++#define ixGC_CAC_OVRD_CB 0x00db ++#define ixGC_CAC_OVRD_CP 0x00dd ++#define ixGC_CAC_OVRD_DB 0x00de ++#define ixGC_CAC_OVRD_GDS 0x00e0 ++#define ixGC_CAC_OVRD_IA 0x00e1 ++#define ixGC_CAC_OVRD_LDS 0x00e2 ++#define ixGC_CAC_OVRD_PA 0x00e3 ++#define ixGC_CAC_OVRD_PC 0x00e4 ++#define ixGC_CAC_OVRD_SC 0x00e5 ++#define ixGC_CAC_OVRD_SPI 0x00e6 ++#define ixGC_CAC_OVRD_CU 0x00e7 ++#define ixGC_CAC_OVRD_SQ 0x00e8 ++#define ixGC_CAC_OVRD_SX 0x00e9 ++#define ixGC_CAC_OVRD_SXRB 0x00ea ++#define ixGC_CAC_OVRD_TA 0x00eb ++#define ixGC_CAC_OVRD_TCC 0x00ec ++#define ixGC_CAC_OVRD_TCP 0x00ed ++#define ixGC_CAC_OVRD_TD 0x00ee ++#define ixGC_CAC_OVRD_VGT 0x00ef ++#define ixGC_CAC_OVRD_WD 0x00f0 ++#define ixGC_CAC_ACC_BCI1 0x00ff ++#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 0x0100 ++#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x0101 ++#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x0102 ++#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x0103 ++#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x0104 ++#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x0105 ++#define ixGC_CAC_WEIGHT_UTCL2_VML2_0 0x0106 ++#define ixGC_CAC_WEIGHT_UTCL2_VML2_1 0x0107 ++#define ixGC_CAC_WEIGHT_UTCL2_VML2_2 0x0108 ++#define ixGC_CAC_ACC_UTCL2_ATCL24 0x0109 ++#define ixGC_CAC_ACC_UTCL2_ROUTER0 0x010a ++#define ixGC_CAC_ACC_UTCL2_ROUTER1 0x010b ++#define ixGC_CAC_ACC_UTCL2_ROUTER2 0x010c ++#define ixGC_CAC_ACC_UTCL2_ROUTER3 0x010d ++#define ixGC_CAC_ACC_UTCL2_ROUTER4 0x010e ++#define ixGC_CAC_ACC_UTCL2_ROUTER5 0x010f ++#define ixGC_CAC_ACC_UTCL2_ROUTER6 0x0110 ++#define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0111 ++#define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0112 ++#define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0113 ++#define ixGC_CAC_ACC_UTCL2_VML20 0x0114 ++#define ixGC_CAC_ACC_UTCL2_VML21 0x0115 ++#define ixGC_CAC_ACC_UTCL2_VML22 0x0116 ++#define ixGC_CAC_ACC_UTCL2_VML23 0x0117 ++#define ixGC_CAC_ACC_UTCL2_VML24 0x0118 ++#define ixGC_CAC_OVRD_UTCL2_ROUTER 0x0119 ++#define ixGC_CAC_OVRD_UTCL2_VML2 0x011a ++#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0 0x011b ++#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1 0x011c ++#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2 0x011d ++#define ixGC_CAC_ACC_UTCL2_WALKER0 0x011e ++#define ixGC_CAC_ACC_UTCL2_WALKER1 0x011f ++#define ixGC_CAC_ACC_UTCL2_WALKER2 0x0120 ++#define ixGC_CAC_ACC_UTCL2_WALKER3 0x0121 ++#define ixGC_CAC_ACC_UTCL2_WALKER4 0x0122 ++#define ixGC_CAC_OVRD_UTCL2_WALKER 0x0123 ++#define ixPCC_STALL_PATTERN_1_2 0x0134 ++#define ixPCC_STALL_PATTERN_3_4 0x0135 ++#define ixPCC_STALL_PATTERN_5_6 0x0136 ++#define ixPCC_STALL_PATTERN_7 0x0137 ++#define ixPCC_THROT_REINCR_FIRST_PATN_1_8 0x0138 ++#define ixPCC_THROT_REINCR_FIRST_PATN_9_16 0x0139 ++#define ixPCC_THROT_REINCR_FIRST_PATN_17_20 0x0140 ++#define ixPCC_THROT_DECR_FIRST_PATN_1_4 0x0141 ++#define ixPCC_THROT_DECR_FIRST_PATN_5_7 0x0142 ++ ++ ++// addressBlock: secacind ++// base address: 0x0 ++#define ixSE_CAC_CNTL 0x0000 ++#define ixSE_CAC_OVR_SEL 0x0001 ++#define ixSE_CAC_OVR_VAL 0x0002 ++ ++ ++// addressBlock: sqind ++// base address: 0x0 ++#define ixSQ_WAVE_MODE 0x0011 ++#define ixSQ_WAVE_STATUS 0x0012 ++#define ixSQ_WAVE_TRAPSTS 0x0013 ++#define ixSQ_WAVE_HW_ID 0x0014 ++#define ixSQ_WAVE_GPR_ALLOC 0x0015 ++#define ixSQ_WAVE_LDS_ALLOC 0x0016 ++#define ixSQ_WAVE_IB_STS 0x0017 ++#define ixSQ_WAVE_PC_LO 0x0018 ++#define ixSQ_WAVE_PC_HI 0x0019 ++#define ixSQ_WAVE_INST_DW0 0x001a ++#define ixSQ_WAVE_INST_DW1 0x001b ++#define ixSQ_WAVE_IB_DBG0 0x001c ++#define ixSQ_WAVE_IB_DBG1 0x001d ++#define ixSQ_WAVE_FLUSH_IB 0x001e ++#define ixSQ_WAVE_TTMP0 0x026c ++#define ixSQ_WAVE_TTMP1 0x026d ++#define ixSQ_WAVE_TTMP2 0x026e ++#define ixSQ_WAVE_TTMP3 0x026f ++#define ixSQ_WAVE_TTMP4 0x0270 ++#define ixSQ_WAVE_TTMP5 0x0271 ++#define ixSQ_WAVE_TTMP6 0x0272 ++#define ixSQ_WAVE_TTMP7 0x0273 ++#define ixSQ_WAVE_TTMP8 0x0274 ++#define ixSQ_WAVE_TTMP9 0x0275 ++#define ixSQ_WAVE_TTMP10 0x0276 ++#define ixSQ_WAVE_TTMP11 0x0277 ++#define ixSQ_WAVE_TTMP12 0x0278 ++#define ixSQ_WAVE_TTMP13 0x0279 ++#define ixSQ_WAVE_TTMP14 0x027a ++#define ixSQ_WAVE_TTMP15 0x027b ++#define ixSQ_WAVE_M0 0x027c ++#define ixSQ_WAVE_EXEC_LO 0x027e ++#define ixSQ_WAVE_EXEC_HI 0x027f ++#define ixSQ_INTERRUPT_WORD_AUTO_CTXID 0x20c0 ++#define ixSQ_INTERRUPT_WORD_AUTO_HI 0x20c0 ++#define ixSQ_INTERRUPT_WORD_AUTO_LO 0x20c0 ++#define ixSQ_INTERRUPT_WORD_CMN_CTXID 0x20c0 ++#define ixSQ_INTERRUPT_WORD_CMN_HI 0x20c0 ++#define ixSQ_INTERRUPT_WORD_WAVE_CTXID 0x20c0 ++#define ixSQ_INTERRUPT_WORD_WAVE_HI 0x20c0 ++#define ixSQ_INTERRUPT_WORD_WAVE_LO 0x20c0 ++ ++ ++// addressBlock: didtind ++// base address: 0x0 ++#define ixDIDT_SQ_CTRL0 0x0000 ++#define ixDIDT_SQ_CTRL2 0x0002 ++#define ixDIDT_SQ_STALL_CTRL 0x0004 ++#define ixDIDT_SQ_TUNING_CTRL 0x0005 ++#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 ++#define ixDIDT_SQ_CTRL3 0x0007 ++#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008 ++#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009 ++#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a ++#define ixDIDT_SQ_STALL_PATTERN_7 0x000b ++#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c ++#define ixDIDT_SQ_THROTTLE_CNTL0 0x000d ++#define ixDIDT_SQ_THROTTLE_CNTL1 0x000e ++#define ixDIDT_SQ_THROTTLE_CNTL_STATUS 0x000f ++#define ixDIDT_SQ_WEIGHT0_3 0x0010 ++#define ixDIDT_SQ_WEIGHT4_7 0x0011 ++#define ixDIDT_SQ_WEIGHT8_11 0x0012 ++#define ixDIDT_SQ_EDC_CTRL 0x0013 ++#define ixDIDT_SQ_THROTTLE_CTRL 0x0014 ++#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 ++#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 ++#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 ++#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 ++#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a ++#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b ++#define ixDIDT_DB_CTRL0 0x0020 ++#define ixDIDT_DB_CTRL2 0x0022 ++#define ixDIDT_DB_STALL_CTRL 0x0024 ++#define ixDIDT_DB_TUNING_CTRL 0x0025 ++#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026 ++#define ixDIDT_DB_CTRL3 0x0027 ++#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028 ++#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029 ++#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a ++#define ixDIDT_DB_STALL_PATTERN_7 0x002b ++#define ixDIDT_DB_MPD_SCALE_FACTOR 0x002c ++#define ixDIDT_DB_THROTTLE_CNTL0 0x002d ++#define ixDIDT_DB_THROTTLE_CNTL1 0x002e ++#define ixDIDT_DB_THROTTLE_CNTL_STATUS 0x002f ++#define ixDIDT_DB_WEIGHT0_3 0x0030 ++#define ixDIDT_DB_WEIGHT4_7 0x0031 ++#define ixDIDT_DB_WEIGHT8_11 0x0032 ++#define ixDIDT_DB_EDC_CTRL 0x0033 ++#define ixDIDT_DB_THROTTLE_CTRL 0x0034 ++#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 ++#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 ++#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 ++#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 ++#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a ++#define ixDIDT_TD_CTRL0 0x0040 ++#define ixDIDT_TD_CTRL2 0x0042 ++#define ixDIDT_TD_STALL_CTRL 0x0044 ++#define ixDIDT_TD_TUNING_CTRL 0x0045 ++#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046 ++#define ixDIDT_TD_CTRL3 0x0047 ++#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048 ++#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049 ++#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a ++#define ixDIDT_TD_STALL_PATTERN_7 0x004b ++#define ixDIDT_TD_MPD_SCALE_FACTOR 0x004c ++#define ixDIDT_TD_THROTTLE_CNTL0 0x004d ++#define ixDIDT_TD_THROTTLE_CNTL1 0x004e ++#define ixDIDT_TD_THROTTLE_CNTL_STATUS 0x004f ++#define ixDIDT_TD_WEIGHT0_3 0x0050 ++#define ixDIDT_TD_WEIGHT4_7 0x0051 ++#define ixDIDT_TD_WEIGHT8_11 0x0052 ++#define ixDIDT_TD_EDC_CTRL 0x0053 ++#define ixDIDT_TD_THROTTLE_CTRL 0x0054 ++#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 ++#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 ++#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 ++#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 ++#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a ++#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005b ++#define ixDIDT_TCP_CTRL0 0x0060 ++#define ixDIDT_TCP_CTRL2 0x0062 ++#define ixDIDT_TCP_STALL_CTRL 0x0064 ++#define ixDIDT_TCP_TUNING_CTRL 0x0065 ++#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0x0066 ++#define ixDIDT_TCP_CTRL3 0x0067 ++#define ixDIDT_TCP_STALL_PATTERN_1_2 0x0068 ++#define ixDIDT_TCP_STALL_PATTERN_3_4 0x0069 ++#define ixDIDT_TCP_STALL_PATTERN_5_6 0x006a ++#define ixDIDT_TCP_STALL_PATTERN_7 0x006b ++#define ixDIDT_TCP_MPD_SCALE_FACTOR 0x006c ++#define ixDIDT_TCP_THROTTLE_CNTL0 0x006d ++#define ixDIDT_TCP_THROTTLE_CNTL1 0x006e ++#define ixDIDT_TCP_THROTTLE_CNTL_STATUS 0x006f ++#define ixDIDT_TCP_WEIGHT0_3 0x0070 ++#define ixDIDT_TCP_WEIGHT4_7 0x0071 ++#define ixDIDT_TCP_WEIGHT8_11 0x0072 ++#define ixDIDT_TCP_EDC_CTRL 0x0073 ++#define ixDIDT_TCP_THROTTLE_CTRL 0x0074 ++#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 ++#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 ++#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 ++#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 ++#define ixDIDT_TCP_EDC_STALL_DELAY_1 0x007a ++#define ixDIDT_TCP_EDC_STALL_DELAY_2 0x007b ++#define ixDIDT_SQ_STALL_EVENT_COUNTER 0x00a0 ++#define ixDIDT_DB_STALL_EVENT_COUNTER 0x00a1 ++#define ixDIDT_TD_STALL_EVENT_COUNTER 0x00a2 ++#define ixDIDT_TCP_STALL_EVENT_COUNTER 0x00a3 ++#define ixDIDT_DBR_STALL_EVENT_COUNTER 0x00a4 ++#define ixDIDT_SQ_CTRL1 0x00b0 ++#define ixDIDT_SQ_EDC_THRESHOLD 0x00b1 ++#define ixDIDT_DB_CTRL1 0x00b2 ++#define ixDIDT_DB_EDC_THRESHOLD 0x00b3 ++#define ixDIDT_TD_CTRL1 0x00b4 ++#define ixDIDT_TD_EDC_THRESHOLD 0x00b5 ++#define ixDIDT_TCP_CTRL1 0x00b6 ++#define ixDIDT_TCP_EDC_THRESHOLD 0x00b7 ++ ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h +new file mode 100644 +index 0000000..6626fc2 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h +@@ -0,0 +1,31160 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _gc_9_2_1_SH_MASK_HEADER ++#define _gc_9_2_1_SH_MASK_HEADER ++ ++ ++// addressBlock: gc_grbmdec ++//GRBM_CNTL ++#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 ++#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f ++#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL ++#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L ++//GRBM_SKEW_CNTL ++#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 ++#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 ++#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL ++#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L ++//GRBM_STATUS2 ++#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 ++#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 ++#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 ++#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 ++#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 ++#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 ++#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 ++#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa ++#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb ++#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc ++#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd ++#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe ++#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf ++#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 ++#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 ++#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 ++#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 ++#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 ++#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 ++#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 ++#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a ++#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c ++#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d ++#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e ++#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f ++#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL ++#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L ++#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L ++#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L ++#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L ++#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L ++#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L ++#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L ++#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L ++#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L ++#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L ++#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L ++#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L ++#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L ++#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L ++#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L ++#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L ++#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L ++#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L ++#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L ++#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L ++#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L ++#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L ++#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L ++#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L ++//GRBM_PWR_CNTL ++#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 ++#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 ++#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 ++#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 ++#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe ++#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf ++#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L ++#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL ++#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L ++#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L ++#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L ++#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L ++//GRBM_STATUS ++#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 ++#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 ++#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 ++#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 ++#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 ++#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc ++#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd ++#define GRBM_STATUS__TA_BUSY__SHIFT 0xe ++#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf ++#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 ++#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 ++#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 ++#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 ++#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 ++#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 ++#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 ++#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 ++#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 ++#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 ++#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a ++#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c ++#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d ++#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e ++#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f ++#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL ++#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L ++#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L ++#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L ++#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L ++#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L ++#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L ++#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L ++#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L ++#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L ++#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L ++#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L ++#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L ++#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L ++#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L ++#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L ++#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L ++#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L ++#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L ++#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L ++#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L ++#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L ++#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L ++#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L ++//GRBM_STATUS_SE0 ++#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 ++#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 ++#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 ++#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 ++#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 ++#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 ++#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 ++#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a ++#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b ++#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d ++#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e ++#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f ++#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L ++#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L ++#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L ++#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L ++#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L ++#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L ++#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L ++#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L ++#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L ++#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L ++#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L ++#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L ++//GRBM_STATUS_SE1 ++#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 ++#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 ++#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 ++#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 ++#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 ++#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 ++#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 ++#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a ++#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b ++#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d ++#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e ++#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f ++#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L ++#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L ++#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L ++#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L ++#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L ++#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L ++#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L ++#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L ++#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L ++#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L ++#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L ++#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L ++//GRBM_SOFT_RESET ++#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 ++#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 ++#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 ++#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 ++#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 ++#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 ++#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 ++#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 ++#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 ++#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L ++#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L ++#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L ++#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L ++#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L ++#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L ++#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L ++#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L ++#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L ++//GRBM_GFX_CLKEN_CNTL ++#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL ++#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L ++//GRBM_WAIT_IDLE_CLOCKS ++#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 ++#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL ++//GRBM_STATUS_SE2 ++#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 ++#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 ++#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 ++#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 ++#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 ++#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 ++#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 ++#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a ++#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b ++#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d ++#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e ++#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f ++#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L ++#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L ++#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L ++#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L ++#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L ++#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L ++#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L ++#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L ++#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L ++#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L ++#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L ++#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L ++//GRBM_STATUS_SE3 ++#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 ++#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 ++#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 ++#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 ++#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 ++#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 ++#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 ++#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a ++#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b ++#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d ++#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e ++#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f ++#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L ++#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L ++#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L ++#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L ++#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L ++#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L ++#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L ++#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L ++#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L ++#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L ++#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L ++#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L ++//GRBM_READ_ERROR ++#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 ++#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 ++#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 ++#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f ++#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL ++#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L ++#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L ++#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L ++//GRBM_READ_ERROR2 ++#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 ++#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 ++#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 ++#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f ++#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L ++#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L ++//GRBM_INT_CNTL ++#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 ++#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 ++#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L ++#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L ++//GRBM_TRAP_OP ++#define GRBM_TRAP_OP__RW__SHIFT 0x0 ++#define GRBM_TRAP_OP__RW_MASK 0x00000001L ++//GRBM_TRAP_ADDR ++#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 ++#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL ++//GRBM_TRAP_ADDR_MSK ++#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 ++#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL ++//GRBM_TRAP_WD ++#define GRBM_TRAP_WD__DATA__SHIFT 0x0 ++#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL ++//GRBM_TRAP_WD_MSK ++#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 ++#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL ++//GRBM_DSM_BYPASS ++#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 ++#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 ++#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L ++#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L ++//GRBM_WRITE_ERROR ++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 ++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 ++#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 ++#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 ++#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc ++#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd ++#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 ++#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 ++#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f ++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L ++#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L ++#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL ++#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L ++#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L ++#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L ++#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L ++#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L ++#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L ++//GRBM_IOV_ERROR ++#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 ++#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 ++#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a ++#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b ++#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f ++#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL ++#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L ++#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L ++#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L ++#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L ++//GRBM_CHIP_REVISION ++#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 ++#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL ++//GRBM_GFX_CNTL ++#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 ++#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 ++#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 ++#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 ++#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L ++#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL ++#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L ++#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L ++//GRBM_RSMU_CFG ++#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 ++#define GRBM_RSMU_CFG__QOS__SHIFT 0xc ++#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 ++#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11 ++#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL ++#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L ++#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L ++#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L ++//GRBM_IH_CREDIT ++#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 ++#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 ++#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L ++#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L ++//GRBM_PWR_CNTL2 ++#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 ++#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 ++#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L ++#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L ++//GRBM_UTCL2_INVAL_RANGE_START ++#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 ++#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL ++//GRBM_UTCL2_INVAL_RANGE_END ++#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 ++#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL ++//GRBM_RSMU_READ_ERROR ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L ++#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L ++//GRBM_CHICKEN_BITS ++#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 ++#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L ++//GRBM_FENCE_RANGE0 ++#define GRBM_FENCE_RANGE0__START__SHIFT 0x0 ++#define GRBM_FENCE_RANGE0__END__SHIFT 0x10 ++#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL ++#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L ++//GRBM_FENCE_RANGE1 ++#define GRBM_FENCE_RANGE1__START__SHIFT 0x0 ++#define GRBM_FENCE_RANGE1__END__SHIFT 0x10 ++#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL ++#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L ++//GRBM_NOWHERE ++#define GRBM_NOWHERE__DATA__SHIFT 0x0 ++#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG0 ++#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 ++#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG1 ++#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 ++#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG2 ++#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 ++#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG3 ++#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 ++#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG4 ++#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 ++#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG5 ++#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 ++#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG6 ++#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 ++#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL ++//GRBM_SCRATCH_REG7 ++#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 ++#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gc_cpdec ++//CP_CPC_STATUS ++#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 ++#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 ++#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 ++#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 ++#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 ++#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 ++#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 ++#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 ++#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa ++#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb ++#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc ++#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd ++#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe ++#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d ++#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e ++#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f ++#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L ++#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L ++#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L ++#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L ++#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L ++#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L ++#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L ++#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L ++#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L ++#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L ++#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L ++#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L ++#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L ++#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L ++#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L ++#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L ++//CP_CPC_BUSY_STAT ++#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 ++#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 ++#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 ++#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 ++#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 ++#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 ++#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 ++#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 ++#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 ++#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 ++#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa ++#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb ++#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc ++#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd ++#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 ++#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 ++#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 ++#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 ++#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 ++#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 ++#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 ++#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 ++#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 ++#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 ++#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a ++#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b ++#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c ++#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d ++#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L ++#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L ++#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L ++#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L ++#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L ++#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L ++#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L ++#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L ++#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L ++#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L ++#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L ++#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L ++#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L ++#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L ++#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L ++#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L ++#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L ++#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L ++#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L ++#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L ++#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L ++#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L ++#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L ++#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L ++#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L ++#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L ++#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L ++#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L ++//CP_CPC_STALLED_STAT1 ++#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 ++#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 ++#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 ++#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 ++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 ++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa ++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd ++#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 ++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 ++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 ++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 ++#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 ++#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 ++#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 ++#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L ++#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L ++#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L ++#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L ++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L ++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L ++#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L ++#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L ++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L ++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L ++#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L ++#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L ++#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L ++#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L ++//CP_CPF_STATUS ++#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 ++#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 ++#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 ++#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 ++#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 ++#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 ++#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 ++#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 ++#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa ++#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb ++#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc ++#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd ++#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe ++#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf ++#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 ++#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 ++#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a ++#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b ++#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c ++#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e ++#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f ++#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L ++#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L ++#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L ++#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L ++#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L ++#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L ++#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L ++#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L ++#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L ++#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L ++#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L ++#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L ++#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L ++#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L ++#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L ++#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L ++#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L ++#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L ++#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L ++#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L ++#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L ++//CP_CPF_BUSY_STAT ++#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 ++#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 ++#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 ++#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 ++#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 ++#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 ++#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 ++#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 ++#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 ++#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 ++#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb ++#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc ++#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd ++#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe ++#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf ++#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 ++#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 ++#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 ++#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 ++#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 ++#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 ++#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 ++#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 ++#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 ++#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 ++#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a ++#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b ++#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c ++#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d ++#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e ++#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f ++#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L ++#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L ++#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L ++#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L ++#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L ++#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L ++#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L ++#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L ++#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L ++#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L ++#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L ++#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L ++#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L ++#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L ++#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L ++#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L ++#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L ++#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L ++#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L ++#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L ++#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L ++#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L ++#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L ++#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L ++#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L ++#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L ++#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L ++#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L ++#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L ++#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L ++#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L ++//CP_CPF_STALLED_STAT1 ++#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 ++#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 ++#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 ++#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 ++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 ++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 ++#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 ++#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 ++#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 ++#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa ++#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb ++#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L ++#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L ++#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L ++#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L ++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L ++#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L ++#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L ++#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L ++#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L ++#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L ++#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L ++//CP_CPC_GRBM_FREE_COUNT ++#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 ++#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL ++//CP_MEC_CNTL ++#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 ++#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 ++#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 ++#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 ++#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 ++#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 ++#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 ++#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c ++#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d ++#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e ++#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f ++#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L ++#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L ++#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L ++#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L ++#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L ++#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L ++#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L ++#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L ++#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L ++#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L ++#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L ++//CP_MEC_ME1_HEADER_DUMP ++#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 ++#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL ++//CP_MEC_ME2_HEADER_DUMP ++#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 ++#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL ++//CP_CPC_SCRATCH_INDEX ++#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 ++#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL ++//CP_CPC_SCRATCH_DATA ++#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 ++#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL ++//CP_CPF_GRBM_FREE_COUNT ++#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 ++#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L ++//CP_CPC_HALT_HYST_COUNT ++#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 ++#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL ++//CP_CE_COMPARE_COUNT ++#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 ++#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL ++//CP_CE_DE_COUNT ++#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 ++#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL ++//CP_DE_CE_COUNT ++#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 ++#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL ++//CP_DE_LAST_INVAL_COUNT ++#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 ++#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL ++//CP_DE_DE_COUNT ++#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 ++#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL ++//CP_STALLED_STAT3 ++#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 ++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 ++#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 ++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 ++#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 ++#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 ++#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 ++#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 ++#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa ++#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb ++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc ++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd ++#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe ++#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf ++#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 ++#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 ++#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 ++#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 ++#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 ++#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L ++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L ++#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L ++#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L ++#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L ++#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L ++#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L ++#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L ++#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L ++#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L ++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L ++#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L ++#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L ++#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L ++#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L ++#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L ++#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L ++#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L ++#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L ++//CP_STALLED_STAT1 ++#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 ++#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 ++#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 ++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa ++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb ++#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc ++#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd ++#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe ++#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf ++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 ++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 ++#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 ++#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a ++#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b ++#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c ++#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d ++#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L ++#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L ++#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L ++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L ++#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L ++#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L ++#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L ++#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L ++#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L ++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L ++#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L ++#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L ++#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L ++#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L ++#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L ++#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L ++//CP_STALLED_STAT2 ++#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 ++#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 ++#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 ++#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 ++#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 ++#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 ++#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 ++#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa ++#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb ++#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc ++#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd ++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe ++#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf ++#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 ++#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 ++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 ++#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 ++#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 ++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 ++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 ++#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 ++#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 ++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 ++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a ++#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b ++#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c ++#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d ++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e ++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f ++#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L ++#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L ++#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L ++#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L ++#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L ++#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L ++#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L ++#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L ++#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L ++#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L ++#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L ++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L ++#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L ++#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L ++#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L ++#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L ++#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L ++#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L ++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L ++#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L ++#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L ++#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L ++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L ++#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L ++#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L ++#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L ++#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L ++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L ++#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L ++//CP_BUSY_STAT ++#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 ++#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 ++#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 ++#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 ++#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 ++#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa ++#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc ++#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd ++#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe ++#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf ++#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 ++#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 ++#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 ++#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 ++#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 ++#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 ++#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L ++#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L ++#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L ++#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L ++#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L ++#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L ++#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L ++#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L ++#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L ++#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L ++#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L ++#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L ++#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L ++#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L ++#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L ++#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L ++//CP_STAT ++#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 ++#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa ++#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb ++#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc ++#define CP_STAT__DC_BUSY__SHIFT 0xd ++#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe ++#define CP_STAT__PFP_BUSY__SHIFT 0xf ++#define CP_STAT__MEQ_BUSY__SHIFT 0x10 ++#define CP_STAT__ME_BUSY__SHIFT 0x11 ++#define CP_STAT__QUERY_BUSY__SHIFT 0x12 ++#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 ++#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 ++#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 ++#define CP_STAT__DMA_BUSY__SHIFT 0x16 ++#define CP_STAT__RCIU_BUSY__SHIFT 0x17 ++#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 ++#define CP_STAT__CE_BUSY__SHIFT 0x1a ++#define CP_STAT__TCIU_BUSY__SHIFT 0x1b ++#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c ++#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d ++#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e ++#define CP_STAT__CP_BUSY__SHIFT 0x1f ++#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L ++#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L ++#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L ++#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L ++#define CP_STAT__DC_BUSY_MASK 0x00002000L ++#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L ++#define CP_STAT__PFP_BUSY_MASK 0x00008000L ++#define CP_STAT__MEQ_BUSY_MASK 0x00010000L ++#define CP_STAT__ME_BUSY_MASK 0x00020000L ++#define CP_STAT__QUERY_BUSY_MASK 0x00040000L ++#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L ++#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L ++#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L ++#define CP_STAT__DMA_BUSY_MASK 0x00400000L ++#define CP_STAT__RCIU_BUSY_MASK 0x00800000L ++#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L ++#define CP_STAT__CE_BUSY_MASK 0x04000000L ++#define CP_STAT__TCIU_BUSY_MASK 0x08000000L ++#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L ++#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L ++#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L ++#define CP_STAT__CP_BUSY_MASK 0x80000000L ++//CP_ME_HEADER_DUMP ++#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 ++#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL ++//CP_PFP_HEADER_DUMP ++#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 ++#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL ++//CP_GRBM_FREE_COUNT ++#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 ++#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 ++#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 ++#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL ++#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L ++#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L ++//CP_CE_HEADER_DUMP ++#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 ++#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL ++//CP_PFP_INSTR_PNTR ++#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 ++#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL ++//CP_ME_INSTR_PNTR ++#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 ++#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL ++//CP_CE_INSTR_PNTR ++#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 ++#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL ++//CP_MEC1_INSTR_PNTR ++#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 ++#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL ++//CP_MEC2_INSTR_PNTR ++#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 ++#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL ++//CP_CSF_STAT ++#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 ++#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L ++//CP_ME_CNTL ++#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 ++#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 ++#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 ++#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 ++#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 ++#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 ++#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 ++#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 ++#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 ++#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 ++#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 ++#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a ++#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b ++#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c ++#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d ++#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L ++#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L ++#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L ++#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L ++#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L ++#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L ++#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L ++#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L ++#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L ++#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L ++#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L ++#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L ++#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L ++#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L ++#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L ++//CP_CNTX_STAT ++#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 ++#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 ++#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 ++#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c ++#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL ++#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L ++#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L ++#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L ++//CP_ME_PREEMPTION ++#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 ++#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L ++//CP_ROQ_THRESHOLDS ++#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 ++#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 ++#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL ++#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L ++//CP_MEQ_STQ_THRESHOLD ++#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 ++#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL ++//CP_RB2_RPTR ++#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 ++#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL ++//CP_RB1_RPTR ++#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 ++#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL ++//CP_RB0_RPTR ++#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 ++#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL ++//CP_RB_RPTR ++#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 ++#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL ++//CP_RB_WPTR_DELAY ++#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 ++#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c ++#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL ++#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L ++//CP_RB_WPTR_POLL_CNTL ++#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 ++#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL ++#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//CP_ROQ1_THRESHOLDS ++#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 ++#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 ++#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 ++#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 ++#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL ++#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L ++#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L ++#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L ++//CP_ROQ2_THRESHOLDS ++#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 ++#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 ++#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 ++#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 ++#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL ++#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L ++#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L ++#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L ++//CP_STQ_THRESHOLDS ++#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 ++#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 ++#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 ++#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL ++#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L ++#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L ++//CP_QUEUE_THRESHOLDS ++#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 ++#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 ++#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL ++#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L ++//CP_MEQ_THRESHOLDS ++#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 ++#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 ++#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL ++#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L ++//CP_ROQ_AVAIL ++#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 ++#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 ++#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL ++#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L ++//CP_STQ_AVAIL ++#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 ++#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL ++//CP_ROQ2_AVAIL ++#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 ++#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL ++//CP_MEQ_AVAIL ++#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 ++#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL ++//CP_CMD_INDEX ++#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 ++#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc ++#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 ++#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL ++#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L ++#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L ++//CP_CMD_DATA ++#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 ++#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL ++//CP_ROQ_RB_STAT ++#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 ++#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 ++#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL ++#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L ++//CP_ROQ_IB1_STAT ++#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 ++#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 ++#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL ++#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L ++//CP_ROQ_IB2_STAT ++#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 ++#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 ++#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL ++#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L ++//CP_STQ_STAT ++#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 ++#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL ++//CP_STQ_WR_STAT ++#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 ++#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL ++//CP_MEQ_STAT ++#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 ++#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 ++#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL ++#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L ++//CP_CEQ1_AVAIL ++#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 ++#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 ++#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL ++#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L ++//CP_CEQ2_AVAIL ++#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 ++#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL ++//CP_CE_ROQ_RB_STAT ++#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 ++#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 ++#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL ++#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L ++//CP_CE_ROQ_IB1_STAT ++#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 ++#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 ++#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL ++#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L ++//CP_CE_ROQ_IB2_STAT ++#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 ++#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 ++#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL ++#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L ++ ++ ++// addressBlock: gc_padec ++//VGT_VTX_VECT_EJECT_REG ++#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 ++#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL ++//VGT_DMA_DATA_FIFO_DEPTH ++#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 ++#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 ++#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL ++#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L ++//VGT_DMA_REQ_FIFO_DEPTH ++#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 ++#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL ++//VGT_DRAW_INIT_FIFO_DEPTH ++#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 ++#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL ++//VGT_LAST_COPY_STATE ++#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 ++#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 ++#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L ++#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L ++//VGT_CACHE_INVALIDATION ++#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 ++#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 ++#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 ++#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 ++#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 ++#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb ++#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc ++#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd ++#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 ++#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 ++#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 ++#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 ++#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c ++#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d ++#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L ++#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L ++#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L ++#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L ++#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L ++#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L ++#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L ++#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L ++#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L ++#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L ++#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L ++#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L ++#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L ++#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L ++//VGT_STRMOUT_DELAY ++#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 ++#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 ++#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb ++#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe ++#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 ++#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL ++#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L ++#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L ++#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L ++#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L ++//VGT_FIFO_DEPTHS ++#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 ++#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 ++#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 ++#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 ++#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL ++#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L ++#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L ++#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L ++//VGT_GS_VERTEX_REUSE ++#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 ++#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL ++//VGT_MC_LAT_CNTL ++#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 ++#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL ++//IA_CNTL_STATUS ++#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 ++#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 ++#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 ++#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 ++#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 ++#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L ++#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L ++#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L ++#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L ++#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L ++//VGT_CNTL_STATUS ++#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 ++#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 ++#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 ++#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 ++#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 ++#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 ++#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 ++#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 ++#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 ++#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 ++#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa ++#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L ++#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L ++#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L ++#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L ++#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L ++#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L ++#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L ++#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L ++#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L ++#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L ++#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L ++//WD_CNTL_STATUS ++#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 ++#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 ++#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 ++#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 ++#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L ++#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L ++#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L ++#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L ++//CC_GC_PRIM_CONFIG ++#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 ++#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 ++#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L ++#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L ++//GC_USER_PRIM_CONFIG ++#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 ++#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 ++#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L ++#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L ++//WD_QOS ++#define WD_QOS__DRAW_STALL__SHIFT 0x0 ++#define WD_QOS__DRAW_STALL_MASK 0x00000001L ++//WD_UTCL1_CNTL ++#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 ++#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 ++#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 ++#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a ++#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c ++#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L ++#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L ++#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L ++#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L ++#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L ++#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++//WD_UTCL1_STATUS ++#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 ++#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 ++#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 ++#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L ++#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L ++#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L ++//IA_UTCL1_CNTL ++#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 ++#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 ++#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 ++#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a ++#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c ++#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L ++#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L ++#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L ++#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L ++#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L ++#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++//IA_UTCL1_STATUS ++#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 ++#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 ++#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 ++#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L ++#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L ++#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L ++//VGT_SYS_CONFIG ++#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 ++#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 ++#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 ++#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L ++#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL ++#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L ++//VGT_VS_MAX_WAVE_ID ++#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 ++#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL ++//VGT_GS_MAX_WAVE_ID ++#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 ++#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL ++//GFX_PIPE_CONTROL ++#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 ++#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd ++#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 ++#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL ++#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L ++#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L ++//CC_GC_SHADER_ARRAY_CONFIG ++#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 ++#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L ++//GC_USER_SHADER_ARRAY_CONFIG ++#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 ++#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L ++//VGT_DMA_PRIMITIVE_TYPE ++#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 ++#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL ++//VGT_DMA_CONTROL ++#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 ++#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 ++#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 ++#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 ++#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 ++#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 ++#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 ++#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL ++#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L ++#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L ++#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L ++#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L ++#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L ++#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L ++//VGT_DMA_LS_HS_CONFIG ++#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 ++#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L ++//WD_BUF_RESOURCE_1 ++#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 ++#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 ++#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL ++#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L ++//WD_BUF_RESOURCE_2 ++#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 ++#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf ++#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 ++#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL ++#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L ++#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L ++//PA_CL_CNTL_STATUS ++#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 ++#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 ++#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 ++#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L ++#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L ++#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L ++//PA_CL_ENHANCE ++#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 ++#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 ++#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 ++#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 ++#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 ++#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 ++#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 ++#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 ++#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 ++#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb ++#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc ++#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe ++#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 ++#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12 ++#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13 ++#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14 ++#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15 ++#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c ++#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d ++#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e ++#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f ++#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L ++#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L ++#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L ++#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L ++#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L ++#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L ++#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L ++#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L ++#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L ++#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L ++#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L ++#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L ++#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L ++#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L ++#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L ++#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L ++#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L ++#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L ++#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L ++#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L ++#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L ++//PA_CL_RESET_DEBUG ++#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 ++#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L ++//PA_SU_CNTL_STATUS ++#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f ++#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L ++//PA_SC_FIFO_DEPTH_CNTL ++#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 ++#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL ++//PA_SC_P3D_TRAP_SCREEN_HV_LOCK ++#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 ++#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L ++//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK ++#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 ++#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L ++//PA_SC_TRAP_SCREEN_HV_LOCK ++#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 ++#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L ++//PA_SC_FORCE_EOV_MAX_CNTS ++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 ++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 ++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL ++#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L ++//PA_SC_BINNER_EVENT_CNTL_0 ++#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 ++#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 ++#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 ++#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 ++#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 ++#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa ++#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc ++#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe ++#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 ++#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 ++#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 ++#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 ++#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 ++#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a ++#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c ++#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e ++#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L ++#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL ++#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L ++#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L ++#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L ++#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L ++#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L ++#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L ++#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L ++#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L ++#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L ++#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L ++#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L ++#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L ++#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L ++#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L ++//PA_SC_BINNER_EVENT_CNTL_1 ++#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 ++#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 ++#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 ++#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa ++#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc ++#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe ++#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 ++#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 ++#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 ++#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a ++#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c ++#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e ++#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L ++#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L ++#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L ++#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L ++#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L ++#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L ++#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L ++#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L ++#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L ++#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L ++#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L ++#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L ++#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L ++//PA_SC_BINNER_EVENT_CNTL_2 ++#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 ++#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 ++#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 ++#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 ++#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 ++#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa ++#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc ++#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe ++#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 ++#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c ++#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e ++#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L ++#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL ++#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L ++#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L ++#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L ++#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L ++#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L ++#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L ++#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L ++#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L ++#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L ++#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L ++//PA_SC_BINNER_EVENT_CNTL_3 ++#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 ++#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 ++#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe ++#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 ++#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 ++#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 ++#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 ++#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 ++#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a ++#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c ++#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e ++#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L ++#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL ++#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L ++#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L ++#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L ++#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L ++#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L ++#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L ++#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L ++#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L ++#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L ++#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L ++//PA_SC_BINNER_TIMEOUT_COUNTER ++#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 ++#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL ++//PA_SC_BINNER_PERF_CNTL_0 ++#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 ++#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa ++#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 ++#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 ++#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL ++#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L ++#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L ++#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L ++//PA_SC_BINNER_PERF_CNTL_1 ++#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 ++#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 ++#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa ++#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL ++#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L ++#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L ++//PA_SC_BINNER_PERF_CNTL_2 ++#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 ++#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb ++#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL ++#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L ++//PA_SC_BINNER_PERF_CNTL_3 ++#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 ++#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL ++//PA_SC_ENHANCE_2 ++#define PA_SC_ENHANCE_2__RESERVED_0__SHIFT 0x0 ++#define PA_SC_ENHANCE_2__RESERVED_1__SHIFT 0x1 ++#define PA_SC_ENHANCE_2__RESERVED_2__SHIFT 0x2 ++#define PA_SC_ENHANCE_2__RESERVED_3__SHIFT 0x3 ++#define PA_SC_ENHANCE_2__RESERVED_4__SHIFT 0x4 ++#define PA_SC_ENHANCE_2__RESERVED_5__SHIFT 0x5 ++#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6 ++#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT 0x7 ++#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x8 ++#define PA_SC_ENHANCE_2__RESERVED_0_MASK 0x00000001L ++#define PA_SC_ENHANCE_2__RESERVED_1_MASK 0x00000002L ++#define PA_SC_ENHANCE_2__RESERVED_2_MASK 0x00000004L ++#define PA_SC_ENHANCE_2__RESERVED_3_MASK 0x00000008L ++#define PA_SC_ENHANCE_2__RESERVED_4_MASK 0x00000010L ++#define PA_SC_ENHANCE_2__RESERVED_5_MASK 0x00000020L ++#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L ++#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK 0x00000080L ++#define PA_SC_ENHANCE_2__RSVD_MASK 0xFFFFFF00L ++//PA_SC_FIFO_SIZE ++#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 ++#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 ++#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf ++#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 ++#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL ++#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L ++#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L ++#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L ++//PA_SC_IF_FIFO_SIZE ++#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 ++#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 ++#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc ++#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 ++#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL ++#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L ++#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L ++#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L ++//PA_SC_PKR_WAVE_TABLE_CNTL ++#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 ++#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL ++//PA_UTCL1_CNTL1 ++#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 ++#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 ++#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 ++#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 ++#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 ++#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 ++#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 ++#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 ++#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 ++#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 ++#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 ++#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 ++#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 ++#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a ++#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b ++#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c ++#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e ++#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L ++#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L ++#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L ++#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L ++#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L ++#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L ++#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L ++#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L ++#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L ++#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L ++#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L ++#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L ++#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L ++#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L ++#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L ++#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L ++#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L ++//PA_UTCL1_CNTL2 ++#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 ++#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 ++#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 ++#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa ++#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb ++#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc ++#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd ++#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe ++#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf ++#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 ++#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 ++#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 ++#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 ++#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 ++#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 ++#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a ++#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b ++#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL ++#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L ++#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L ++#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L ++#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L ++#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L ++#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L ++#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L ++#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L ++#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L ++#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L ++#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L ++#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L ++#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L ++#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L ++#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L ++#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L ++//PA_SIDEBAND_REQUEST_DELAYS ++#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 ++#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 ++#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL ++#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L ++//PA_SC_ENHANCE ++#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 ++#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 ++#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 ++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 ++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 ++#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 ++#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 ++#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 ++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 ++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 ++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa ++#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb ++#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc ++#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe ++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 ++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 ++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 ++#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 ++#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 ++#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 ++#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a ++#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b ++#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c ++#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d ++#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L ++#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L ++#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L ++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L ++#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L ++#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L ++#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L ++#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L ++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L ++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L ++#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L ++#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L ++#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L ++#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L ++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L ++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L ++#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L ++#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L ++#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L ++#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L ++#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L ++#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L ++#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L ++#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L ++#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L ++//PA_SC_ENHANCE_1 ++#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 ++#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 ++#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 ++#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 ++#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 ++#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 ++#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 ++#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 ++#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 ++#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa ++#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb ++#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc ++#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd ++#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe ++#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf ++#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 ++#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 ++#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 ++#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 ++#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 ++#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 ++#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 ++#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 ++#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 ++#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 ++#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a ++#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b ++#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c ++#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d ++#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e ++#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x1f ++#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L ++#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L ++#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L ++#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L ++#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L ++#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L ++#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L ++#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L ++#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L ++#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L ++#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L ++#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L ++#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L ++#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L ++#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L ++#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L ++#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L ++#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L ++#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L ++#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L ++#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L ++#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L ++#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L ++#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L ++#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L ++#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L ++#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L ++#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L ++#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L ++#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L ++#define PA_SC_ENHANCE_1__RSVD_MASK 0x80000000L ++//PA_SC_DSM_CNTL ++#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 ++#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 ++#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L ++#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L ++//PA_SC_TILE_STEERING_CREST_OVERRIDE ++#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 ++#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 ++#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 ++#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L ++#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L ++#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L ++ ++ ++// addressBlock: gc_sqdec ++//SQ_CONFIG ++#define SQ_CONFIG__UNUSED__SHIFT 0x0 ++#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 ++#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 ++#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9 ++#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa ++#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb ++#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc ++#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd ++#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe ++#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf ++#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 ++#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 ++#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 ++#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 ++#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 ++#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c ++#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d ++#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e ++#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f ++#define SQ_CONFIG__UNUSED_MASK 0x0000007FL ++#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L ++#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L ++#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L ++#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L ++#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L ++#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L ++#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L ++#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L ++#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L ++#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L ++#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L ++#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L ++#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L ++#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L ++#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L ++#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L ++#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L ++#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L ++//SQC_CONFIG ++#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 ++#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 ++#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 ++#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 ++#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 ++#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 ++#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 ++#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa ++#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb ++#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc ++#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe ++#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf ++#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 ++#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 ++#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a ++#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L ++#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL ++#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L ++#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L ++#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L ++#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L ++#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L ++#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L ++#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L ++#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L ++#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L ++#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L ++#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L ++#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L ++#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L ++//LDS_CONFIG ++#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 ++#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x2 ++#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L ++#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000004L ++//SQ_RANDOM_WAVE_PRI ++#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 ++#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 ++#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa ++#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL ++#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L ++#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L ++//SQ_REG_CREDITS ++#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 ++#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 ++#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c ++#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d ++#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e ++#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f ++#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL ++#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L ++#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L ++#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L ++#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L ++#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L ++//SQ_FIFO_SIZES ++#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 ++#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 ++#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 ++#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 ++#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL ++#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L ++#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L ++#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L ++//SQ_DSM_CNTL ++#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 ++#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 ++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 ++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 ++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 ++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 ++#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 ++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 ++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 ++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 ++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 ++#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a ++#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L ++#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L ++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L ++#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L ++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L ++#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L ++#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L ++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L ++#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L ++#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L ++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L ++#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L ++#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L ++//SQ_DSM_CNTL2 ++#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb ++#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe ++#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 ++#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a ++#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L ++#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L ++#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L ++//SQ_RUNTIME_CONFIG ++#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 ++#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L ++//SH_MEM_BASES ++#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 ++#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 ++#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL ++#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L ++//SH_MEM_CONFIG ++#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 ++#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 ++#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc ++#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd ++#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L ++#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L ++#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L ++#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L ++//CC_GC_SHADER_RATE_CONFIG ++#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 ++#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 ++#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 ++#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L ++#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L ++#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L ++//GC_USER_SHADER_RATE_CONFIG ++#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 ++#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 ++#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 ++#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L ++#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L ++#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L ++//SQ_INTERRUPT_AUTO_MASK ++#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 ++#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL ++//SQ_INTERRUPT_MSG_CTRL ++#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 ++#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L ++//SQ_UTCL1_CNTL1 ++#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 ++#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 ++#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 ++#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 ++#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 ++#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 ++#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 ++#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 ++#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 ++#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a ++#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b ++#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c ++#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e ++#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L ++#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L ++#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L ++#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L ++#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L ++#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L ++#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L ++#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L ++#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L ++#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L ++#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L ++#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L ++#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L ++#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L ++//SQ_UTCL1_CNTL2 ++#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 ++#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 ++#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 ++#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa ++#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc ++#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd ++#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe ++#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf ++#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 ++#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a ++#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c ++#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL ++#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L ++#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L ++#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L ++#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L ++#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L ++#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L ++#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L ++#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L ++#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L ++#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L ++//SQ_UTCL1_STATUS ++#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 ++#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 ++#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L ++#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L ++//SQ_SHADER_TBA_LO ++#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 ++#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL ++//SQ_SHADER_TBA_HI ++#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 ++#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL ++//SQ_SHADER_TMA_LO ++#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 ++#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL ++//SQ_SHADER_TMA_HI ++#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 ++#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL ++//SQC_DSM_CNTL ++#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++//SQC_DSM_CNTLA ++#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 ++#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 ++#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 ++#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a ++#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L ++#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L ++#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L ++#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L ++//SQC_DSM_CNTLB ++#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 ++#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 ++#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 ++#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a ++#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L ++#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L ++#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L ++#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L ++//SQC_DSM_CNTL2 ++#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb ++#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe ++#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a ++#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L ++//SQC_DSM_CNTL2A ++#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 ++#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a ++#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L ++#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L ++//SQC_DSM_CNTL2B ++#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 ++#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a ++#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L ++#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L ++//SQ_REG_TIMESTAMP ++#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 ++#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL ++//SQ_CMD_TIMESTAMP ++#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 ++#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL ++//SQ_IND_INDEX ++#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 ++#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 ++#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 ++#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc ++#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd ++#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe ++#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf ++#define SQ_IND_INDEX__INDEX__SHIFT 0x10 ++#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL ++#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L ++#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L ++#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L ++#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L ++#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L ++#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L ++#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L ++//SQ_IND_DATA ++#define SQ_IND_DATA__DATA__SHIFT 0x0 ++#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL ++//SQ_CMD ++#define SQ_CMD__CMD__SHIFT 0x0 ++#define SQ_CMD__MODE__SHIFT 0x4 ++#define SQ_CMD__CHECK_VMID__SHIFT 0x7 ++#define SQ_CMD__DATA__SHIFT 0x8 ++#define SQ_CMD__WAVE_ID__SHIFT 0x10 ++#define SQ_CMD__SIMD_ID__SHIFT 0x14 ++#define SQ_CMD__QUEUE_ID__SHIFT 0x18 ++#define SQ_CMD__VM_ID__SHIFT 0x1c ++#define SQ_CMD__CMD_MASK 0x00000007L ++#define SQ_CMD__MODE_MASK 0x00000070L ++#define SQ_CMD__CHECK_VMID_MASK 0x00000080L ++#define SQ_CMD__DATA_MASK 0x00000F00L ++#define SQ_CMD__WAVE_ID_MASK 0x000F0000L ++#define SQ_CMD__SIMD_ID_MASK 0x00300000L ++#define SQ_CMD__QUEUE_ID_MASK 0x07000000L ++#define SQ_CMD__VM_ID_MASK 0xF0000000L ++//SQ_TIME_HI ++#define SQ_TIME_HI__TIME__SHIFT 0x0 ++#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL ++//SQ_TIME_LO ++#define SQ_TIME_LO__TIME__SHIFT 0x0 ++#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL ++//SQ_DS_0 ++#define SQ_DS_0__OFFSET0__SHIFT 0x0 ++#define SQ_DS_0__OFFSET1__SHIFT 0x8 ++#define SQ_DS_0__GDS__SHIFT 0x10 ++#define SQ_DS_0__OP__SHIFT 0x11 ++#define SQ_DS_0__ENCODING__SHIFT 0x1a ++#define SQ_DS_0__OFFSET0_MASK 0x000000FFL ++#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L ++#define SQ_DS_0__GDS_MASK 0x00010000L ++#define SQ_DS_0__OP_MASK 0x01FE0000L ++#define SQ_DS_0__ENCODING_MASK 0xFC000000L ++//SQ_DS_1 ++#define SQ_DS_1__ADDR__SHIFT 0x0 ++#define SQ_DS_1__DATA0__SHIFT 0x8 ++#define SQ_DS_1__DATA1__SHIFT 0x10 ++#define SQ_DS_1__VDST__SHIFT 0x18 ++#define SQ_DS_1__ADDR_MASK 0x000000FFL ++#define SQ_DS_1__DATA0_MASK 0x0000FF00L ++#define SQ_DS_1__DATA1_MASK 0x00FF0000L ++#define SQ_DS_1__VDST_MASK 0xFF000000L ++//SQ_EXP_0 ++#define SQ_EXP_0__EN__SHIFT 0x0 ++#define SQ_EXP_0__TGT__SHIFT 0x4 ++#define SQ_EXP_0__COMPR__SHIFT 0xa ++#define SQ_EXP_0__DONE__SHIFT 0xb ++#define SQ_EXP_0__VM__SHIFT 0xc ++#define SQ_EXP_0__ENCODING__SHIFT 0x1a ++#define SQ_EXP_0__EN_MASK 0x0000000FL ++#define SQ_EXP_0__TGT_MASK 0x000003F0L ++#define SQ_EXP_0__COMPR_MASK 0x00000400L ++#define SQ_EXP_0__DONE_MASK 0x00000800L ++#define SQ_EXP_0__VM_MASK 0x00001000L ++#define SQ_EXP_0__ENCODING_MASK 0xFC000000L ++//SQ_EXP_1 ++#define SQ_EXP_1__VSRC0__SHIFT 0x0 ++#define SQ_EXP_1__VSRC1__SHIFT 0x8 ++#define SQ_EXP_1__VSRC2__SHIFT 0x10 ++#define SQ_EXP_1__VSRC3__SHIFT 0x18 ++#define SQ_EXP_1__VSRC0_MASK 0x000000FFL ++#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L ++#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L ++#define SQ_EXP_1__VSRC3_MASK 0xFF000000L ++//SQ_FLAT_0 ++#define SQ_FLAT_0__OFFSET__SHIFT 0x0 ++#define SQ_FLAT_0__LDS__SHIFT 0xd ++#define SQ_FLAT_0__SEG__SHIFT 0xe ++#define SQ_FLAT_0__GLC__SHIFT 0x10 ++#define SQ_FLAT_0__SLC__SHIFT 0x11 ++#define SQ_FLAT_0__OP__SHIFT 0x12 ++#define SQ_FLAT_0__ENCODING__SHIFT 0x1a ++#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL ++#define SQ_FLAT_0__LDS_MASK 0x00002000L ++#define SQ_FLAT_0__SEG_MASK 0x0000C000L ++#define SQ_FLAT_0__GLC_MASK 0x00010000L ++#define SQ_FLAT_0__SLC_MASK 0x00020000L ++#define SQ_FLAT_0__OP_MASK 0x01FC0000L ++#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L ++//SQ_FLAT_1 ++#define SQ_FLAT_1__ADDR__SHIFT 0x0 ++#define SQ_FLAT_1__DATA__SHIFT 0x8 ++#define SQ_FLAT_1__SADDR__SHIFT 0x10 ++#define SQ_FLAT_1__NV__SHIFT 0x17 ++#define SQ_FLAT_1__VDST__SHIFT 0x18 ++#define SQ_FLAT_1__ADDR_MASK 0x000000FFL ++#define SQ_FLAT_1__DATA_MASK 0x0000FF00L ++#define SQ_FLAT_1__SADDR_MASK 0x007F0000L ++#define SQ_FLAT_1__NV_MASK 0x00800000L ++#define SQ_FLAT_1__VDST_MASK 0xFF000000L ++//SQ_GLBL_0 ++#define SQ_GLBL_0__OFFSET__SHIFT 0x0 ++#define SQ_GLBL_0__LDS__SHIFT 0xd ++#define SQ_GLBL_0__SEG__SHIFT 0xe ++#define SQ_GLBL_0__GLC__SHIFT 0x10 ++#define SQ_GLBL_0__SLC__SHIFT 0x11 ++#define SQ_GLBL_0__OP__SHIFT 0x12 ++#define SQ_GLBL_0__ENCODING__SHIFT 0x1a ++#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL ++#define SQ_GLBL_0__LDS_MASK 0x00002000L ++#define SQ_GLBL_0__SEG_MASK 0x0000C000L ++#define SQ_GLBL_0__GLC_MASK 0x00010000L ++#define SQ_GLBL_0__SLC_MASK 0x00020000L ++#define SQ_GLBL_0__OP_MASK 0x01FC0000L ++#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L ++//SQ_GLBL_1 ++#define SQ_GLBL_1__ADDR__SHIFT 0x0 ++#define SQ_GLBL_1__DATA__SHIFT 0x8 ++#define SQ_GLBL_1__SADDR__SHIFT 0x10 ++#define SQ_GLBL_1__NV__SHIFT 0x17 ++#define SQ_GLBL_1__VDST__SHIFT 0x18 ++#define SQ_GLBL_1__ADDR_MASK 0x000000FFL ++#define SQ_GLBL_1__DATA_MASK 0x0000FF00L ++#define SQ_GLBL_1__SADDR_MASK 0x007F0000L ++#define SQ_GLBL_1__NV_MASK 0x00800000L ++#define SQ_GLBL_1__VDST_MASK 0xFF000000L ++//SQ_INST ++#define SQ_INST__ENCODING__SHIFT 0x0 ++#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL ++//SQ_MIMG_0 ++#define SQ_MIMG_0__OPM__SHIFT 0x0 ++#define SQ_MIMG_0__DMASK__SHIFT 0x8 ++#define SQ_MIMG_0__UNORM__SHIFT 0xc ++#define SQ_MIMG_0__GLC__SHIFT 0xd ++#define SQ_MIMG_0__DA__SHIFT 0xe ++#define SQ_MIMG_0__A16__SHIFT 0xf ++#define SQ_MIMG_0__TFE__SHIFT 0x10 ++#define SQ_MIMG_0__LWE__SHIFT 0x11 ++#define SQ_MIMG_0__OP__SHIFT 0x12 ++#define SQ_MIMG_0__SLC__SHIFT 0x19 ++#define SQ_MIMG_0__ENCODING__SHIFT 0x1a ++#define SQ_MIMG_0__OPM_MASK 0x00000001L ++#define SQ_MIMG_0__DMASK_MASK 0x00000F00L ++#define SQ_MIMG_0__UNORM_MASK 0x00001000L ++#define SQ_MIMG_0__GLC_MASK 0x00002000L ++#define SQ_MIMG_0__DA_MASK 0x00004000L ++#define SQ_MIMG_0__A16_MASK 0x00008000L ++#define SQ_MIMG_0__TFE_MASK 0x00010000L ++#define SQ_MIMG_0__LWE_MASK 0x00020000L ++#define SQ_MIMG_0__OP_MASK 0x01FC0000L ++#define SQ_MIMG_0__SLC_MASK 0x02000000L ++#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L ++//SQ_MIMG_1 ++#define SQ_MIMG_1__VADDR__SHIFT 0x0 ++#define SQ_MIMG_1__VDATA__SHIFT 0x8 ++#define SQ_MIMG_1__SRSRC__SHIFT 0x10 ++#define SQ_MIMG_1__SSAMP__SHIFT 0x15 ++#define SQ_MIMG_1__D16__SHIFT 0x1f ++#define SQ_MIMG_1__VADDR_MASK 0x000000FFL ++#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L ++#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L ++#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L ++#define SQ_MIMG_1__D16_MASK 0x80000000L ++//SQ_MTBUF_0 ++#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 ++#define SQ_MTBUF_0__OFFEN__SHIFT 0xc ++#define SQ_MTBUF_0__IDXEN__SHIFT 0xd ++#define SQ_MTBUF_0__GLC__SHIFT 0xe ++#define SQ_MTBUF_0__OP__SHIFT 0xf ++#define SQ_MTBUF_0__DFMT__SHIFT 0x13 ++#define SQ_MTBUF_0__NFMT__SHIFT 0x17 ++#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a ++#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL ++#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L ++#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L ++#define SQ_MTBUF_0__GLC_MASK 0x00004000L ++#define SQ_MTBUF_0__OP_MASK 0x00078000L ++#define SQ_MTBUF_0__DFMT_MASK 0x00780000L ++#define SQ_MTBUF_0__NFMT_MASK 0x03800000L ++#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L ++//SQ_MTBUF_1 ++#define SQ_MTBUF_1__VADDR__SHIFT 0x0 ++#define SQ_MTBUF_1__VDATA__SHIFT 0x8 ++#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 ++#define SQ_MTBUF_1__SLC__SHIFT 0x16 ++#define SQ_MTBUF_1__TFE__SHIFT 0x17 ++#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 ++#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL ++#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L ++#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L ++#define SQ_MTBUF_1__SLC_MASK 0x00400000L ++#define SQ_MTBUF_1__TFE_MASK 0x00800000L ++#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L ++//SQ_MUBUF_0 ++#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 ++#define SQ_MUBUF_0__OFFEN__SHIFT 0xc ++#define SQ_MUBUF_0__IDXEN__SHIFT 0xd ++#define SQ_MUBUF_0__GLC__SHIFT 0xe ++#define SQ_MUBUF_0__LDS__SHIFT 0x10 ++#define SQ_MUBUF_0__SLC__SHIFT 0x11 ++#define SQ_MUBUF_0__OP__SHIFT 0x12 ++#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a ++#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL ++#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L ++#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L ++#define SQ_MUBUF_0__GLC_MASK 0x00004000L ++#define SQ_MUBUF_0__LDS_MASK 0x00010000L ++#define SQ_MUBUF_0__SLC_MASK 0x00020000L ++#define SQ_MUBUF_0__OP_MASK 0x01FC0000L ++#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L ++//SQ_MUBUF_1 ++#define SQ_MUBUF_1__VADDR__SHIFT 0x0 ++#define SQ_MUBUF_1__VDATA__SHIFT 0x8 ++#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 ++#define SQ_MUBUF_1__TFE__SHIFT 0x17 ++#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 ++#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL ++#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L ++#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L ++#define SQ_MUBUF_1__TFE_MASK 0x00800000L ++#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L ++//SQ_SCRATCH_0 ++#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 ++#define SQ_SCRATCH_0__LDS__SHIFT 0xd ++#define SQ_SCRATCH_0__SEG__SHIFT 0xe ++#define SQ_SCRATCH_0__GLC__SHIFT 0x10 ++#define SQ_SCRATCH_0__SLC__SHIFT 0x11 ++#define SQ_SCRATCH_0__OP__SHIFT 0x12 ++#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a ++#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL ++#define SQ_SCRATCH_0__LDS_MASK 0x00002000L ++#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L ++#define SQ_SCRATCH_0__GLC_MASK 0x00010000L ++#define SQ_SCRATCH_0__SLC_MASK 0x00020000L ++#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L ++#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L ++//SQ_SCRATCH_1 ++#define SQ_SCRATCH_1__ADDR__SHIFT 0x0 ++#define SQ_SCRATCH_1__DATA__SHIFT 0x8 ++#define SQ_SCRATCH_1__SADDR__SHIFT 0x10 ++#define SQ_SCRATCH_1__NV__SHIFT 0x17 ++#define SQ_SCRATCH_1__VDST__SHIFT 0x18 ++#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL ++#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L ++#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L ++#define SQ_SCRATCH_1__NV_MASK 0x00800000L ++#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L ++//SQ_SMEM_0 ++#define SQ_SMEM_0__SBASE__SHIFT 0x0 ++#define SQ_SMEM_0__SDATA__SHIFT 0x6 ++#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe ++#define SQ_SMEM_0__NV__SHIFT 0xf ++#define SQ_SMEM_0__GLC__SHIFT 0x10 ++#define SQ_SMEM_0__IMM__SHIFT 0x11 ++#define SQ_SMEM_0__OP__SHIFT 0x12 ++#define SQ_SMEM_0__ENCODING__SHIFT 0x1a ++#define SQ_SMEM_0__SBASE_MASK 0x0000003FL ++#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L ++#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L ++#define SQ_SMEM_0__NV_MASK 0x00008000L ++#define SQ_SMEM_0__GLC_MASK 0x00010000L ++#define SQ_SMEM_0__IMM_MASK 0x00020000L ++#define SQ_SMEM_0__OP_MASK 0x03FC0000L ++#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L ++//SQ_SMEM_1 ++#define SQ_SMEM_1__OFFSET__SHIFT 0x0 ++#define SQ_SMEM_1__SOFFSET__SHIFT 0x19 ++#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL ++#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L ++//SQ_SOP1 ++#define SQ_SOP1__SSRC0__SHIFT 0x0 ++#define SQ_SOP1__OP__SHIFT 0x8 ++#define SQ_SOP1__SDST__SHIFT 0x10 ++#define SQ_SOP1__ENCODING__SHIFT 0x17 ++#define SQ_SOP1__SSRC0_MASK 0x000000FFL ++#define SQ_SOP1__OP_MASK 0x0000FF00L ++#define SQ_SOP1__SDST_MASK 0x007F0000L ++#define SQ_SOP1__ENCODING_MASK 0xFF800000L ++//SQ_SOP2 ++#define SQ_SOP2__SSRC0__SHIFT 0x0 ++#define SQ_SOP2__SSRC1__SHIFT 0x8 ++#define SQ_SOP2__SDST__SHIFT 0x10 ++#define SQ_SOP2__OP__SHIFT 0x17 ++#define SQ_SOP2__ENCODING__SHIFT 0x1e ++#define SQ_SOP2__SSRC0_MASK 0x000000FFL ++#define SQ_SOP2__SSRC1_MASK 0x0000FF00L ++#define SQ_SOP2__SDST_MASK 0x007F0000L ++#define SQ_SOP2__OP_MASK 0x3F800000L ++#define SQ_SOP2__ENCODING_MASK 0xC0000000L ++//SQ_SOPC ++#define SQ_SOPC__SSRC0__SHIFT 0x0 ++#define SQ_SOPC__SSRC1__SHIFT 0x8 ++#define SQ_SOPC__OP__SHIFT 0x10 ++#define SQ_SOPC__ENCODING__SHIFT 0x17 ++#define SQ_SOPC__SSRC0_MASK 0x000000FFL ++#define SQ_SOPC__SSRC1_MASK 0x0000FF00L ++#define SQ_SOPC__OP_MASK 0x007F0000L ++#define SQ_SOPC__ENCODING_MASK 0xFF800000L ++//SQ_SOPK ++#define SQ_SOPK__SIMM16__SHIFT 0x0 ++#define SQ_SOPK__SDST__SHIFT 0x10 ++#define SQ_SOPK__OP__SHIFT 0x17 ++#define SQ_SOPK__ENCODING__SHIFT 0x1c ++#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL ++#define SQ_SOPK__SDST_MASK 0x007F0000L ++#define SQ_SOPK__OP_MASK 0x0F800000L ++#define SQ_SOPK__ENCODING_MASK 0xF0000000L ++//SQ_SOPP ++#define SQ_SOPP__SIMM16__SHIFT 0x0 ++#define SQ_SOPP__OP__SHIFT 0x10 ++#define SQ_SOPP__ENCODING__SHIFT 0x17 ++#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL ++#define SQ_SOPP__OP_MASK 0x007F0000L ++#define SQ_SOPP__ENCODING_MASK 0xFF800000L ++//SQ_VINTRP ++#define SQ_VINTRP__VSRC__SHIFT 0x0 ++#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 ++#define SQ_VINTRP__ATTR__SHIFT 0xa ++#define SQ_VINTRP__OP__SHIFT 0x10 ++#define SQ_VINTRP__VDST__SHIFT 0x12 ++#define SQ_VINTRP__ENCODING__SHIFT 0x1a ++#define SQ_VINTRP__VSRC_MASK 0x000000FFL ++#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L ++#define SQ_VINTRP__ATTR_MASK 0x0000FC00L ++#define SQ_VINTRP__OP_MASK 0x00030000L ++#define SQ_VINTRP__VDST_MASK 0x03FC0000L ++#define SQ_VINTRP__ENCODING_MASK 0xFC000000L ++//SQ_VOP1 ++#define SQ_VOP1__SRC0__SHIFT 0x0 ++#define SQ_VOP1__OP__SHIFT 0x9 ++#define SQ_VOP1__VDST__SHIFT 0x11 ++#define SQ_VOP1__ENCODING__SHIFT 0x19 ++#define SQ_VOP1__SRC0_MASK 0x000001FFL ++#define SQ_VOP1__OP_MASK 0x0001FE00L ++#define SQ_VOP1__VDST_MASK 0x01FE0000L ++#define SQ_VOP1__ENCODING_MASK 0xFE000000L ++//SQ_VOP2 ++#define SQ_VOP2__SRC0__SHIFT 0x0 ++#define SQ_VOP2__VSRC1__SHIFT 0x9 ++#define SQ_VOP2__VDST__SHIFT 0x11 ++#define SQ_VOP2__OP__SHIFT 0x19 ++#define SQ_VOP2__ENCODING__SHIFT 0x1f ++#define SQ_VOP2__SRC0_MASK 0x000001FFL ++#define SQ_VOP2__VSRC1_MASK 0x0001FE00L ++#define SQ_VOP2__VDST_MASK 0x01FE0000L ++#define SQ_VOP2__OP_MASK 0x7E000000L ++#define SQ_VOP2__ENCODING_MASK 0x80000000L ++//SQ_VOP3P_0 ++#define SQ_VOP3P_0__VDST__SHIFT 0x0 ++#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 ++#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb ++#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe ++#define SQ_VOP3P_0__CLAMP__SHIFT 0xf ++#define SQ_VOP3P_0__OP__SHIFT 0x10 ++#define SQ_VOP3P_0__ENCODING__SHIFT 0x17 ++#define SQ_VOP3P_0__VDST_MASK 0x000000FFL ++#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L ++#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L ++#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L ++#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L ++#define SQ_VOP3P_0__OP_MASK 0x007F0000L ++#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L ++//SQ_VOP3P_1 ++#define SQ_VOP3P_1__SRC0__SHIFT 0x0 ++#define SQ_VOP3P_1__SRC1__SHIFT 0x9 ++#define SQ_VOP3P_1__SRC2__SHIFT 0x12 ++#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b ++#define SQ_VOP3P_1__NEG__SHIFT 0x1d ++#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL ++#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L ++#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L ++#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L ++#define SQ_VOP3P_1__NEG_MASK 0xE0000000L ++//SQ_VOP3_0 ++#define SQ_VOP3_0__VDST__SHIFT 0x0 ++#define SQ_VOP3_0__ABS__SHIFT 0x8 ++#define SQ_VOP3_0__OP_SEL__SHIFT 0xb ++#define SQ_VOP3_0__CLAMP__SHIFT 0xf ++#define SQ_VOP3_0__OP__SHIFT 0x10 ++#define SQ_VOP3_0__ENCODING__SHIFT 0x1a ++#define SQ_VOP3_0__VDST_MASK 0x000000FFL ++#define SQ_VOP3_0__ABS_MASK 0x00000700L ++#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L ++#define SQ_VOP3_0__CLAMP_MASK 0x00008000L ++#define SQ_VOP3_0__OP_MASK 0x03FF0000L ++#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L ++//SQ_VOP3_0_SDST_ENC ++#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 ++#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 ++#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf ++#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 ++#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a ++#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL ++#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L ++#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L ++#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L ++#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L ++//SQ_VOP3_1 ++#define SQ_VOP3_1__SRC0__SHIFT 0x0 ++#define SQ_VOP3_1__SRC1__SHIFT 0x9 ++#define SQ_VOP3_1__SRC2__SHIFT 0x12 ++#define SQ_VOP3_1__OMOD__SHIFT 0x1b ++#define SQ_VOP3_1__NEG__SHIFT 0x1d ++#define SQ_VOP3_1__SRC0_MASK 0x000001FFL ++#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L ++#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L ++#define SQ_VOP3_1__OMOD_MASK 0x18000000L ++#define SQ_VOP3_1__NEG_MASK 0xE0000000L ++//SQ_VOPC ++#define SQ_VOPC__SRC0__SHIFT 0x0 ++#define SQ_VOPC__VSRC1__SHIFT 0x9 ++#define SQ_VOPC__OP__SHIFT 0x11 ++#define SQ_VOPC__ENCODING__SHIFT 0x19 ++#define SQ_VOPC__SRC0_MASK 0x000001FFL ++#define SQ_VOPC__VSRC1_MASK 0x0001FE00L ++#define SQ_VOPC__OP_MASK 0x01FE0000L ++#define SQ_VOPC__ENCODING_MASK 0xFE000000L ++//SQ_VOP_DPP ++#define SQ_VOP_DPP__SRC0__SHIFT 0x0 ++#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 ++#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 ++#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 ++#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 ++#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 ++#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 ++#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 ++#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c ++#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL ++#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L ++#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L ++#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L ++#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L ++#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L ++#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L ++#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L ++#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L ++//SQ_VOP_SDWA ++#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 ++#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 ++#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb ++#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd ++#define SQ_VOP_SDWA__OMOD__SHIFT 0xe ++#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 ++#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 ++#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 ++#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 ++#define SQ_VOP_SDWA__S0__SHIFT 0x17 ++#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 ++#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b ++#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c ++#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d ++#define SQ_VOP_SDWA__S1__SHIFT 0x1f ++#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL ++#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L ++#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L ++#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L ++#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L ++#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L ++#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L ++#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L ++#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L ++#define SQ_VOP_SDWA__S0_MASK 0x00800000L ++#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L ++#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L ++#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L ++#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L ++#define SQ_VOP_SDWA__S1_MASK 0x80000000L ++//SQ_VOP_SDWA_SDST_ENC ++#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 ++#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 ++#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 ++#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d ++#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL ++#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L ++#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L ++#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L ++#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L ++#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L ++//SQ_LB_CTR_CTRL ++#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 ++#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 ++#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 ++#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L ++#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L ++#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L ++//SQ_LB_DATA0 ++#define SQ_LB_DATA0__DATA__SHIFT 0x0 ++#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL ++//SQ_LB_DATA1 ++#define SQ_LB_DATA1__DATA__SHIFT 0x0 ++#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL ++//SQ_LB_DATA2 ++#define SQ_LB_DATA2__DATA__SHIFT 0x0 ++#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL ++//SQ_LB_DATA3 ++#define SQ_LB_DATA3__DATA__SHIFT 0x0 ++#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL ++//SQ_LB_CTR_SEL ++#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 ++#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 ++#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 ++#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc ++#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL ++#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L ++#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L ++#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L ++//SQ_LB_CTR0_CU ++#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 ++#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 ++#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL ++#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L ++//SQ_LB_CTR1_CU ++#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 ++#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 ++#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL ++#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L ++//SQ_LB_CTR2_CU ++#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 ++#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 ++#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL ++#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L ++//SQ_LB_CTR3_CU ++#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 ++#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 ++#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL ++#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L ++//SQ_THREAD_TRACE_WORD_CMN ++#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL ++#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L ++//SQ_THREAD_TRACE_WORD_EVENT ++#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 ++#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa ++#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL ++#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L ++#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L ++#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L ++#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L ++//SQ_THREAD_TRACE_WORD_INST ++#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 ++#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb ++#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL ++#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L ++#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L ++#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L ++#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L ++//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L ++#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L ++//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L ++//SQ_THREAD_TRACE_WORD_ISSUE ++#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a ++#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L ++#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L ++#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L ++//SQ_THREAD_TRACE_WORD_MISC ++#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc ++#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd ++#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL ++#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L ++#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L ++#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L ++//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L ++#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L ++//SQ_THREAD_TRACE_WORD_REG_1_OF_2 ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L ++#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L ++//SQ_THREAD_TRACE_WORD_REG_2_OF_2 ++#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L ++#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L ++//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 ++#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL ++//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 ++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 ++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L ++//SQ_THREAD_TRACE_WORD_WAVE ++#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 ++#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa ++#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe ++#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL ++#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L ++#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L ++#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L ++#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L ++#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L ++//SQ_THREAD_TRACE_WORD_WAVE_START ++#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 ++#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 ++#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 ++#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa ++#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe ++#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 ++#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 ++#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 ++#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d ++#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL ++#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L ++#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L ++//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 ++#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL ++//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL ++//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 ++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 ++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 ++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL ++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L ++#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L ++//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 ++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL ++//SQ_WREXEC_EXEC_HI ++#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 ++#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a ++#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b ++#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c ++#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f ++#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL ++#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L ++#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L ++#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L ++#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L ++//SQ_WREXEC_EXEC_LO ++#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 ++#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL ++//SQ_BUF_RSRC_WORD0 ++#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 ++#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL ++//SQ_BUF_RSRC_WORD1 ++#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 ++#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 ++#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e ++#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f ++#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL ++#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L ++#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L ++#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L ++//SQ_BUF_RSRC_WORD2 ++#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 ++#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL ++//SQ_BUF_RSRC_WORD3 ++#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 ++#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 ++#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 ++#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 ++#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc ++#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf ++#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 ++#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 ++#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 ++#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 ++#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b ++#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e ++#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L ++#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L ++#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L ++#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L ++#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L ++#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L ++#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L ++#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L ++#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L ++#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L ++#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L ++#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L ++//SQ_IMG_RSRC_WORD0 ++#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL ++//SQ_IMG_RSRC_WORD1 ++#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 ++#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 ++#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a ++#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e ++#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f ++#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL ++#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L ++#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L ++#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L ++#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L ++#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L ++//SQ_IMG_RSRC_WORD2 ++#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe ++#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c ++#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL ++#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L ++#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L ++//SQ_IMG_RSRC_WORD3 ++#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 ++#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 ++#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 ++#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc ++#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 ++#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 ++#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c ++#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L ++#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L ++#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L ++#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L ++#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L ++#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L ++#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L ++#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L ++//SQ_IMG_RSRC_WORD4 ++#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd ++#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d ++#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL ++#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L ++#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L ++//SQ_IMG_RSRC_WORD5 ++#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd ++#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 ++#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 ++#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a ++#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b ++#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c ++#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL ++#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L ++#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L ++#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L ++#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L ++#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L ++#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L ++//SQ_IMG_RSRC_WORD6 ++#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc ++#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 ++#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 ++#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 ++#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 ++#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 ++#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c ++#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL ++#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L ++#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L ++#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L ++#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L ++#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L ++#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L ++#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L ++//SQ_IMG_RSRC_WORD7 ++#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 ++#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL ++//SQ_IMG_SAMP_WORD0 ++#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 ++#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 ++#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 ++#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 ++#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc ++#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf ++#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 ++#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 ++#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 ++#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 ++#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b ++#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c ++#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d ++#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f ++#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L ++#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L ++#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L ++#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L ++#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L ++#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L ++#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L ++#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L ++#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L ++#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L ++#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L ++#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L ++#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L ++#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L ++//SQ_IMG_SAMP_WORD1 ++#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 ++#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc ++#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 ++#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c ++#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL ++#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L ++#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L ++#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L ++//SQ_IMG_SAMP_WORD2 ++#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 ++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe ++#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 ++#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 ++#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 ++#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a ++#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c ++#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d ++#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e ++#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f ++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL ++#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L ++#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L ++#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L ++#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L ++#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L ++#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L ++#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L ++#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L ++#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L ++//SQ_IMG_SAMP_WORD3 ++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 ++#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc ++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e ++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL ++#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L ++#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L ++//SQ_FLAT_SCRATCH_WORD0 ++#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 ++#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL ++//SQ_FLAT_SCRATCH_WORD1 ++#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 ++#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL ++//SQ_M0_GPR_IDX_WORD ++#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 ++#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc ++#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd ++#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe ++#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf ++#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL ++#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L ++#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L ++#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L ++#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L ++//SQC_ICACHE_UTCL1_CNTL1 ++#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 ++#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 ++#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 ++#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 ++#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 ++#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 ++#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 ++#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 ++#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 ++#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 ++#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 ++#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 ++#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a ++#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b ++#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c ++#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e ++#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L ++#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L ++#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L ++#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L ++#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L ++#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L ++#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L ++#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L ++#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L ++#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L ++#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L ++#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L ++#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L ++#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L ++#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L ++#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L ++//SQC_ICACHE_UTCL1_CNTL2 ++#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 ++#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 ++#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 ++#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa ++#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc ++#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd ++#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe ++#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf ++#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 ++#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 ++#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 ++#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 ++#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 ++#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a ++#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL ++#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L ++#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L ++#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L ++#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L ++#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L ++#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L ++#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L ++#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L ++#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L ++#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L ++#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L ++#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L ++#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L ++//SQC_DCACHE_UTCL1_CNTL1 ++#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 ++#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 ++#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 ++#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 ++#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 ++#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 ++#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 ++#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 ++#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 ++#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 ++#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 ++#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 ++#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a ++#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b ++#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c ++#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e ++#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L ++#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L ++#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L ++#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L ++#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L ++#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L ++#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L ++#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L ++#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L ++#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L ++#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L ++#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L ++#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L ++#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L ++#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L ++#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L ++//SQC_DCACHE_UTCL1_CNTL2 ++#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 ++#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 ++#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 ++#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa ++#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc ++#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd ++#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe ++#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf ++#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 ++#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 ++#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 ++#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 ++#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 ++#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a ++#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL ++#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L ++#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L ++#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L ++#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L ++#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L ++#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L ++#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L ++#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L ++#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L ++#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L ++#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L ++#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L ++#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L ++//SQC_ICACHE_UTCL1_STATUS ++#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++//SQC_DCACHE_UTCL1_STATUS ++#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++ ++ ++// addressBlock: gc_shsdec ++//SX_DEBUG_1 ++#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 ++#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 ++#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 ++#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa ++#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb ++#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc ++#define SX_DEBUG_1__DISABLE_SX_DB_FGCG__SHIFT 0xd ++#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe ++#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL ++#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L ++#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L ++#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L ++#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L ++#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L ++#define SX_DEBUG_1__DISABLE_SX_DB_FGCG_MASK 0x00002000L ++#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L ++//SPI_PS_MAX_WAVE_ID ++#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 ++#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 ++#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL ++#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L ++//SPI_START_PHASE ++#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 ++#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 ++#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 ++#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L ++#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL ++#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L ++//SPI_GFX_CNTL ++#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 ++#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L ++//SPI_DSM_CNTL ++#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 ++#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L ++//SPI_DSM_CNTL2 ++#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 ++#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa ++#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L ++#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L ++//SPI_DEBUG_BUSY ++#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0 ++#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1 ++#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x2 ++#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x3 ++#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x4 ++#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x5 ++#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x6 ++#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x7 ++#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x8 ++#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x9 ++#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xa ++#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xb ++#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xc ++#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xd ++#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0xe ++#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0xf ++#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x10 ++#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x11 ++#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x12 ++#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x13 ++#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x14 ++#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x15 ++#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000001L ++#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000002L ++#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000004L ++#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000008L ++#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000010L ++#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000020L ++#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000040L ++#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000080L ++#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000100L ++#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000200L ++#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00000400L ++#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00000800L ++#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00001000L ++#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00002000L ++#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00004000L ++#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00008000L ++#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00010000L ++#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00020000L ++#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00040000L ++#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00080000L ++#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00100000L ++#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00200000L ++//SPI_CONFIG_PS_CU_EN ++#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 ++#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 ++#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 ++#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L ++#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL ++#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L ++//SPI_WF_LIFETIME_CNTL ++#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 ++#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 ++#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL ++#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L ++//SPI_WF_LIFETIME_LIMIT_0 ++#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_1 ++#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_2 ++#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_3 ++#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_4 ++#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_5 ++#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_6 ++#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_7 ++#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_8 ++#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_LIMIT_9 ++#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f ++#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_0 ++#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_1 ++#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_2 ++#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_3 ++#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_4 ++#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_5 ++#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_6 ++#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_7 ++#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_8 ++#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_9 ++#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_10 ++#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_11 ++#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_12 ++#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_13 ++#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_14 ++#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_15 ++#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_16 ++#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_17 ++#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_18 ++#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_19 ++#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L ++//SPI_WF_LIFETIME_STATUS_20 ++#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 ++#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f ++#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL ++#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L ++//SPI_LB_CTR_CTRL ++#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 ++#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 ++#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 ++#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 ++#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L ++#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L ++#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L ++#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L ++//SPI_LB_CU_MASK ++#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 ++#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL ++//SPI_LB_DATA_REG ++#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 ++#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL ++//SPI_PG_ENABLE_STATIC_CU_MASK ++#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 ++#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL ++//SPI_GDS_CREDITS ++#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 ++#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 ++#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 ++#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL ++#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L ++#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L ++//SPI_SX_EXPORT_BUFFER_SIZES ++#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 ++#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 ++#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL ++#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L ++//SPI_SX_SCOREBOARD_BUFFER_SIZES ++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 ++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 ++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL ++#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L ++//SPI_CSQ_WF_ACTIVE_STATUS ++#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL ++//SPI_CSQ_WF_ACTIVE_COUNT_0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L ++//SPI_CSQ_WF_ACTIVE_COUNT_1 ++#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L ++//SPI_CSQ_WF_ACTIVE_COUNT_2 ++#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L ++//SPI_CSQ_WF_ACTIVE_COUNT_3 ++#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L ++//SPI_CSQ_WF_ACTIVE_COUNT_4 ++#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L ++//SPI_CSQ_WF_ACTIVE_COUNT_5 ++#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L ++//SPI_CSQ_WF_ACTIVE_COUNT_6 ++#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L ++//SPI_CSQ_WF_ACTIVE_COUNT_7 ++#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 ++#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 ++#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL ++#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L ++//SPI_LB_DATA_WAVES ++#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 ++#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 ++#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL ++#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L ++//SPI_LB_DATA_PERCU_WAVE_HSGS ++#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 ++#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 ++#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL ++#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L ++//SPI_LB_DATA_PERCU_WAVE_VSPS ++#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 ++#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 ++#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL ++#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L ++//SPI_LB_DATA_PERCU_WAVE_CS ++#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 ++#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL ++//SPI_P0_TRAP_SCREEN_PSBA_LO ++#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 ++#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_P0_TRAP_SCREEN_PSBA_HI ++#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 ++#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL ++//SPI_P0_TRAP_SCREEN_PSMA_LO ++#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 ++#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_P0_TRAP_SCREEN_PSMA_HI ++#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 ++#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL ++//SPI_P0_TRAP_SCREEN_GPR_MIN ++#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 ++#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 ++#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL ++#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L ++//SPI_P1_TRAP_SCREEN_PSBA_LO ++#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 ++#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_P1_TRAP_SCREEN_PSBA_HI ++#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 ++#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL ++//SPI_P1_TRAP_SCREEN_PSMA_LO ++#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 ++#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_P1_TRAP_SCREEN_PSMA_HI ++#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 ++#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL ++//SPI_P1_TRAP_SCREEN_GPR_MIN ++#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 ++#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 ++#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL ++#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L ++ ++ ++// addressBlock: gc_tpdec ++//TD_CNTL ++#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 ++#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 ++#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 ++#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 ++#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb ++#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf ++#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 ++#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 ++#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 ++#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 ++#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 ++#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 ++#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18 ++#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L ++#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L ++#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L ++#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L ++#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L ++#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L ++#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L ++#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L ++#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L ++#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L ++#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L ++#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L ++#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L ++//TD_STATUS ++#define TD_STATUS__BUSY__SHIFT 0x1f ++#define TD_STATUS__BUSY_MASK 0x80000000L ++//TD_DSM_CNTL ++#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++//TD_DSM_CNTL2 ++#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a ++#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L ++//TD_SCRATCH ++#define TD_SCRATCH__SCRATCH__SHIFT 0x0 ++#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL ++//TA_CNTL ++#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 ++#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 ++#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd ++#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 ++#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 ++#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL ++#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L ++#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L ++#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L ++#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L ++//TA_CNTL_AUX ++#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 ++#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 ++#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 ++#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 ++#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 ++#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9 ++#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa ++#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc ++#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd ++#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe ++#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf ++#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 ++#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 ++#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 ++#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 ++#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 ++#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 ++#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 ++#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 ++#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 ++#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 ++#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a ++#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b ++#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c ++#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d ++#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e ++#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L ++#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL ++#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L ++#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L ++#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L ++#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L ++#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L ++#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L ++#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L ++#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L ++#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L ++#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L ++#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L ++#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L ++#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L ++#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L ++#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L ++#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L ++#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L ++#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L ++#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L ++#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L ++#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L ++#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L ++#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L ++#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L ++//TA_RESERVED_010C ++#define TA_RESERVED_010C__Unused__SHIFT 0x0 ++#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL ++//TA_STATUS ++#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc ++#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd ++#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe ++#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 ++#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 ++#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 ++#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 ++#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 ++#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 ++#define TA_STATUS__IN_BUSY__SHIFT 0x18 ++#define TA_STATUS__FG_BUSY__SHIFT 0x19 ++#define TA_STATUS__LA_BUSY__SHIFT 0x1a ++#define TA_STATUS__FL_BUSY__SHIFT 0x1b ++#define TA_STATUS__TA_BUSY__SHIFT 0x1c ++#define TA_STATUS__FA_BUSY__SHIFT 0x1d ++#define TA_STATUS__AL_BUSY__SHIFT 0x1e ++#define TA_STATUS__BUSY__SHIFT 0x1f ++#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L ++#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L ++#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L ++#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L ++#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L ++#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L ++#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L ++#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L ++#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L ++#define TA_STATUS__IN_BUSY_MASK 0x01000000L ++#define TA_STATUS__FG_BUSY_MASK 0x02000000L ++#define TA_STATUS__LA_BUSY_MASK 0x04000000L ++#define TA_STATUS__FL_BUSY_MASK 0x08000000L ++#define TA_STATUS__TA_BUSY_MASK 0x10000000L ++#define TA_STATUS__FA_BUSY_MASK 0x20000000L ++#define TA_STATUS__AL_BUSY_MASK 0x40000000L ++#define TA_STATUS__BUSY_MASK 0x80000000L ++//TA_SCRATCH ++#define TA_SCRATCH__SCRATCH__SHIFT 0x0 ++#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gc_gdsdec ++//GDS_CONFIG ++#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 ++#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 ++#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 ++#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 ++#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L ++#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L ++#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L ++#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L ++//GDS_CNTL_STATUS ++#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 ++#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 ++#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 ++#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 ++#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 ++#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 ++#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 ++#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 ++#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 ++#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 ++#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa ++#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb ++#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc ++#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd ++#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe ++#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L ++#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L ++#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L ++#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L ++#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L ++#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L ++#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L ++#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L ++#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L ++#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L ++#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L ++#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L ++#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L ++#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L ++#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L ++//GDS_ENHANCE2 ++#define GDS_ENHANCE2__MISC__SHIFT 0x0 ++#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 ++#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL ++#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L ++//GDS_PROTECTION_FAULT ++#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 ++#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 ++#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 ++#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 ++#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa ++#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc ++#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 ++#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L ++#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L ++#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L ++#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L ++#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L ++#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L ++#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L ++//GDS_VM_PROTECTION_FAULT ++#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 ++#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 ++#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 ++#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 ++#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 ++#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 ++#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L ++#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L ++#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L ++#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L ++#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L ++#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L ++//GDS_DSM_CNTL ++#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 ++#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 ++#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 ++#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 ++#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 ++#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa ++#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd ++#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf ++#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L ++#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L ++#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L ++#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L ++#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L ++#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L ++#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L ++//GDS_DSM_CNTL2 ++#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf ++#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a ++#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L ++#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L ++//GDS_WD_GDS_CSB ++#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 ++#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd ++#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL ++#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L ++ ++ ++// addressBlock: gc_rbdec ++//DB_DEBUG ++#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 ++#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 ++#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 ++#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 ++#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 ++#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 ++#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 ++#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 ++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa ++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc ++#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe ++#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf ++#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 ++#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 ++#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 ++#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 ++#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 ++#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 ++#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 ++#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 ++#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c ++#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d ++#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e ++#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f ++#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L ++#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L ++#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L ++#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L ++#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L ++#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L ++#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L ++#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L ++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L ++#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L ++#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L ++#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L ++#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L ++#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L ++#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L ++#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L ++#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L ++#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L ++#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L ++#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L ++#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L ++#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L ++#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L ++#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L ++//DB_DEBUG2 ++#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 ++#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 ++#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 ++#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 ++#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 ++#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 ++#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 ++#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 ++#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 ++#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 ++#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe ++#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf ++#define DB_DEBUG2__RESERVED__SHIFT 0x10 ++#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 ++#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 ++#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 ++#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a ++#define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b ++#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c ++#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d ++#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e ++#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f ++#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L ++#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L ++#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L ++#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L ++#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L ++#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L ++#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L ++#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L ++#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L ++#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L ++#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L ++#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L ++#define DB_DEBUG2__RESERVED_MASK 0x00010000L ++#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L ++#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L ++#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L ++#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L ++#define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L ++#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L ++#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L ++#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L ++#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L ++//DB_DEBUG3 ++#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 ++#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 ++#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 ++#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 ++#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 ++#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 ++#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 ++#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 ++#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 ++#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 ++#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa ++#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb ++#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc ++#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd ++#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe ++#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf ++#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 ++#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 ++#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 ++#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 ++#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 ++#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 ++#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 ++#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 ++#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 ++#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 ++#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a ++#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b ++#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c ++#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d ++#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e ++#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f ++#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L ++#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L ++#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L ++#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L ++#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L ++#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L ++#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L ++#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L ++#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L ++#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L ++#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L ++#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L ++#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L ++#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L ++#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L ++#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L ++#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L ++#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L ++#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L ++#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L ++#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L ++#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L ++#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L ++#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L ++#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L ++#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L ++#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L ++#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L ++#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L ++#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L ++#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L ++#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L ++//DB_DEBUG4 ++#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 ++#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 ++#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 ++#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 ++#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 ++#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 ++#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 ++#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 ++#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 ++#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 ++#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa ++#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb ++#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc ++#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd ++#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe ++#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf ++#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 ++#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 ++#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 ++#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13 ++#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT 0x1e ++#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0x1f ++#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L ++#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L ++#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L ++#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L ++#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L ++#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L ++#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L ++#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L ++#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L ++#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L ++#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L ++#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L ++#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L ++#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L ++#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L ++#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L ++#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L ++#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L ++#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L ++#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0x3FF80000L ++#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK 0x40000000L ++#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x80000000L ++//DB_CREDIT_LIMIT ++#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 ++#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 ++#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa ++#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 ++#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL ++#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L ++#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L ++#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L ++//DB_WATERMARKS ++#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 ++#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 ++#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb ++#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf ++#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 ++#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e ++#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f ++#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL ++#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L ++#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L ++#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L ++#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L ++#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L ++#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L ++//DB_SUBTILE_CONTROL ++#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 ++#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 ++#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 ++#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 ++#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 ++#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa ++#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc ++#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe ++#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 ++#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 ++#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L ++#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL ++#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L ++#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L ++#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L ++#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L ++#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L ++#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L ++#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L ++#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L ++//DB_FREE_CACHELINES ++#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 ++#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 ++#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe ++#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 ++#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 ++#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL ++#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L ++#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L ++#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L ++#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L ++//DB_FIFO_DEPTH1 ++#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 ++#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 ++#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa ++#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 ++#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 ++#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL ++#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L ++#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L ++#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L ++#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L ++//DB_FIFO_DEPTH2 ++#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 ++#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 ++#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf ++#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 ++#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL ++#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L ++#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L ++#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L ++//DB_EXCEPTION_CONTROL ++#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 ++#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 ++#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 ++#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L ++#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L ++#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L ++//DB_RING_CONTROL ++#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 ++#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L ++//DB_MEM_ARB_WATERMARKS ++#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 ++#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 ++#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 ++#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 ++#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L ++#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L ++#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L ++#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L ++//DB_RMI_CACHE_POLICY ++#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 ++#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 ++#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 ++#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 ++#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 ++#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa ++#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb ++#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 ++#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 ++#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 ++#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 ++#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 ++#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 ++#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a ++#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b ++#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L ++#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L ++#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L ++#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L ++#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L ++#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L ++#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L ++#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L ++#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L ++#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L ++#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L ++#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L ++#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L ++#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L ++#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L ++//DB_DFSM_CONFIG ++#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 ++#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 ++#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 ++#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 ++#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 ++#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L ++#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L ++#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L ++#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L ++#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L ++//DB_DFSM_WATERMARK ++#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 ++#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 ++#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL ++#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L ++//DB_DFSM_TILES_IN_FLIGHT ++#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 ++#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 ++#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL ++#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L ++//DB_DFSM_PRIMS_IN_FLIGHT ++#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 ++#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 ++#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL ++#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L ++//DB_DFSM_WATCHDOG ++#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 ++#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL ++//DB_DFSM_FLUSH_ENABLE ++#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 ++#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 ++#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c ++#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL ++#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L ++#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L ++//DB_DFSM_FLUSH_AUX_EVENT ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L ++#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L ++//CC_RB_REDUNDANCY ++#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 ++#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc ++#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 ++#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 ++#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L ++#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L ++#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L ++#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L ++//CC_RB_BACKEND_DISABLE ++#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 ++#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L ++//GB_ADDR_CONFIG ++#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 ++#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 ++#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 ++#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc ++#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 ++#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 ++#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 ++#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 ++#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a ++#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c ++#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e ++#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f ++#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L ++#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L ++#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L ++#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L ++#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L ++#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L ++#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L ++#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L ++#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L ++#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L ++#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L ++#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L ++#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L ++//GB_BACKEND_MAP ++#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 ++#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL ++//GB_GPU_ID ++#define GB_GPU_ID__GPU_ID__SHIFT 0x0 ++#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL ++//CC_RB_DAISY_CHAIN ++#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 ++#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 ++#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 ++#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc ++#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 ++#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 ++#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 ++#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c ++#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL ++#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L ++#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L ++#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L ++#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L ++#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L ++#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L ++#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L ++//GB_ADDR_CONFIG_READ ++#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 ++#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 ++#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 ++#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc ++#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 ++#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 ++#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 ++#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 ++#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a ++#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c ++#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e ++#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f ++#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L ++#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L ++#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L ++#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L ++#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L ++#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L ++#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L ++#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L ++#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L ++#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L ++#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L ++#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L ++#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L ++//GB_TILE_MODE0 ++#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE1 ++#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE2 ++#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE3 ++#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE4 ++#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE5 ++#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE6 ++#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE7 ++#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE8 ++#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE9 ++#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE10 ++#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE11 ++#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE12 ++#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE13 ++#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE14 ++#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE15 ++#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE16 ++#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE17 ++#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE18 ++#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE19 ++#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE20 ++#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE21 ++#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE22 ++#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE23 ++#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE24 ++#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE25 ++#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE26 ++#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE27 ++#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE28 ++#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE29 ++#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE30 ++#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_TILE_MODE31 ++#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 ++#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 ++#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb ++#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 ++#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 ++#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL ++#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L ++#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L ++#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L ++#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L ++//GB_MACROTILE_MODE0 ++#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE1 ++#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE2 ++#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE3 ++#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE4 ++#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE5 ++#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE6 ++#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE7 ++#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE8 ++#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE9 ++#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE10 ++#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE11 ++#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE12 ++#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE13 ++#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE14 ++#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L ++//GB_MACROTILE_MODE15 ++#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 ++#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 ++#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 ++#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 ++#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L ++#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL ++#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L ++#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L ++//CB_HW_CONTROL ++#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 ++#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 ++#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc ++#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 ++#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 ++#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 ++#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 ++#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 ++#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b ++#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c ++#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d ++#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e ++#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f ++#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL ++#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L ++#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L ++#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L ++#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L ++#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L ++#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L ++#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L ++#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L ++#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L ++#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L ++#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L ++#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L ++#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L ++//CB_HW_CONTROL_1 ++#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 ++#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 ++#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb ++#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 ++#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a ++#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL ++#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L ++#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L ++#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L ++#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L ++//CB_HW_CONTROL_2 ++#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 ++#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 ++#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf ++#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 ++#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c ++#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL ++#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L ++#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L ++#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L ++#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L ++//CB_HW_CONTROL_3 ++#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 ++#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 ++#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 ++#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 ++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 ++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 ++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 ++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 ++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 ++#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 ++#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa ++#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb ++#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc ++#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd ++#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe ++#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf ++#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 ++#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 ++#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a ++#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b ++#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c ++#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L ++#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L ++#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L ++#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L ++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L ++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L ++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L ++#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L ++#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L ++#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L ++#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L ++#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L ++#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L ++#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L ++#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L ++#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L ++#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L ++#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L ++#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L ++#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L ++#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L ++#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L ++#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L ++//CB_HW_MEM_ARBITER_RD ++#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 ++#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 ++#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 ++#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 ++#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a ++#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d ++#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L ++#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL ++#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L ++#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L ++#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L ++#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L ++#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L ++//CB_HW_MEM_ARBITER_WR ++#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 ++#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 ++#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 ++#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 ++#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a ++#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d ++#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L ++#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL ++#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L ++#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L ++#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L ++#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L ++#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L ++//CB_DCC_CONFIG ++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 ++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 ++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 ++#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 ++#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 ++#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 ++#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 ++#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c ++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL ++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L ++#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L ++#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L ++#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L ++#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L ++#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L ++#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L ++//GC_USER_RB_REDUNDANCY ++#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 ++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc ++#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 ++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 ++#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L ++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L ++#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L ++#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L ++//GC_USER_RB_BACKEND_DISABLE ++#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 ++#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L ++ ++ ++// addressBlock: gc_ea_gceadec2 ++//GCEA_PERFCOUNTER_RSLT_CNTL ++#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++//GCEA_DSM_CNTL ++#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 ++#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 ++#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L ++#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L ++//GCEA_DSM_CNTLA ++#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++//GCEA_DSM_CNTLB ++#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++//GCEA_DSM_CNTL2 ++#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a ++#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L ++//GCEA_DSM_CNTL2A ++#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++//GCEA_DSM_CNTL2B ++#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++//GCEA_TCC_XBR_CREDITS ++#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 ++#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 ++#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 ++#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe ++#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 ++#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 ++#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 ++#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e ++#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL ++#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L ++#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L ++#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L ++#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L ++#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L ++#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L ++#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L ++//GCEA_TCC_XBR_MAXBURST ++#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 ++#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 ++#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 ++#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc ++#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL ++#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L ++#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L ++#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L ++//GCEA_PROBE_CNTL ++#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 ++#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 ++#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL ++#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L ++//GCEA_PROBE_MAP ++#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 ++#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 ++#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 ++#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 ++#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 ++#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 ++#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 ++#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 ++#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 ++#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 ++#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa ++#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb ++#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc ++#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd ++#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe ++#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf ++#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 ++#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L ++#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L ++#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L ++#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L ++#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L ++#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L ++#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L ++#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L ++#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L ++#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L ++#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L ++#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L ++#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L ++#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L ++#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L ++#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L ++#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L ++//GCEA_ERR_STATUS ++#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 ++#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 ++#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 ++#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa ++#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb ++#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc ++#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd ++#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL ++#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L ++#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L ++#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L ++#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L ++#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L ++#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L ++//GCEA_MISC2 ++#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 ++#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 ++#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 ++#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 ++#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc ++#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L ++#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L ++#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL ++#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L ++#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L ++//GCEA_DRAM_BANK_ARB ++#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0 ++#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1 ++#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x8 ++#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xe ++#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L ++#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000000FEL ++#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00003F00L ++#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00004000L ++//GCEA_SDP_BACKDOOR_CMDCREDITS0 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L ++#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L ++//GCEA_SDP_BACKDOOR_CMDCREDITS1 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L ++#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L ++//GCEA_SDP_BACKDOOR_DATACREDITS0 ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L ++#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L ++//GCEA_SDP_BACKDOOR_DATACREDITS1 ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L ++#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L ++//GCEA_SDP_BACKDOOR_MISCCREDITS ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10 ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17 ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L ++#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L ++//GCEA_SDP_ENABLE ++#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 ++#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L ++ ++ ++// addressBlock: gc_rmi_rmidec ++//RMI_GENERAL_CNTL ++#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 ++#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 ++#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 ++#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 ++#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 ++#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 ++#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 ++#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a ++#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b ++#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c ++#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d ++#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e ++#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L ++#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL ++#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L ++#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L ++#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L ++#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L ++#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L ++#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L ++#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L ++#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L ++#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L ++#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L ++//RMI_GENERAL_CNTL1 ++#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 ++#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 ++#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 ++#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 ++#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 ++#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa ++#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb ++#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc ++#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL ++#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L ++#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L ++#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L ++#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L ++#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L ++#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L ++#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L ++//RMI_GENERAL_STATUS ++#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 ++#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 ++#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 ++#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 ++#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 ++#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 ++#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 ++#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 ++#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 ++#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 ++#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa ++#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb ++#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc ++#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd ++#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe ++#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf ++#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 ++#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 ++#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 ++#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 ++#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 ++#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 ++#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d ++#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e ++#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f ++#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L ++#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L ++#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L ++#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L ++#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L ++#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L ++#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L ++#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L ++#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L ++#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L ++#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L ++#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L ++#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L ++#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L ++#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L ++#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L ++#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L ++#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L ++#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L ++#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L ++#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L ++#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L ++#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L ++#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L ++#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L ++//RMI_SUBBLOCK_STATUS0 ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 ++#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L ++#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L ++#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L ++//RMI_SUBBLOCK_STATUS1 ++#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 ++#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa ++#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 ++#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL ++#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L ++#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L ++//RMI_SUBBLOCK_STATUS2 ++#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 ++#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 ++#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL ++#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L ++//RMI_SUBBLOCK_STATUS3 ++#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 ++#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa ++#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL ++#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L ++//RMI_XBAR_CONFIG ++#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 ++#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 ++#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 ++#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe ++#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L ++#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL ++#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L ++#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L ++#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L ++//RMI_PROBE_POP_LOGIC_CNTL ++#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 ++#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 ++#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 ++#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa ++#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 ++#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL ++#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L ++#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L ++#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L ++#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L ++//RMI_UTC_XNACK_N_MISC_CNTL ++#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 ++#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 ++#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc ++#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd ++#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL ++#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L ++#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L ++#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L ++//RMI_DEMUX_CNTL ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L ++#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L ++#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L ++//RMI_UTCL1_CNTL1 ++#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 ++#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 ++#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 ++#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 ++#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 ++#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 ++#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 ++#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 ++#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 ++#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 ++#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 ++#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 ++#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 ++#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a ++#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b ++#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c ++#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e ++#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L ++#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L ++#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L ++#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L ++#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L ++#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L ++#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L ++#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L ++#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L ++#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L ++#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L ++#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L ++#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L ++#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L ++#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L ++#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L ++#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L ++//RMI_UTCL1_CNTL2 ++#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 ++#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 ++#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa ++#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc ++#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd ++#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe ++#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf ++#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 ++#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 ++#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 ++#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 ++#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 ++#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 ++#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a ++#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL ++#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L ++#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L ++#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L ++#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L ++#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L ++#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L ++#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L ++#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L ++#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L ++#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L ++#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L ++#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L ++#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L ++//RMI_TCIW_FORMATTER0_CNTL ++#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 ++#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 ++#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 ++#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 ++#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b ++#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c ++#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d ++#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e ++#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f ++#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L ++#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL ++#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L ++#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L ++#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L ++#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L ++#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L ++#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L ++#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L ++//RMI_TCIW_FORMATTER1_CNTL ++#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 ++#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 ++#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 ++#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 ++#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b ++#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c ++#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d ++#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e ++#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f ++#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L ++#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL ++#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L ++#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L ++#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L ++#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L ++#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L ++#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L ++#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L ++//RMI_SCOREBOARD_CNTL ++#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 ++#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 ++#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 ++#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 ++#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 ++#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 ++#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 ++#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 ++#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 ++#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 ++#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L ++#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L ++#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L ++#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L ++#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L ++#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L ++#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L ++#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L ++#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L ++#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L ++//RMI_SCOREBOARD_STATUS0 ++#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 ++#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 ++#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L ++#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L ++#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L ++//RMI_SCOREBOARD_STATUS1 ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd ++#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c ++#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d ++#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L ++#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L ++#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L ++#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L ++#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L ++//RMI_SCOREBOARD_STATUS2 ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 ++#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a ++#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L ++#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L ++#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L ++#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L ++#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L ++//RMI_XBAR_ARBITER_CONFIG ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L ++#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L ++//RMI_XBAR_ARBITER_CONFIG_1 ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L ++#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L ++//RMI_CLOCK_CNTRL ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 ++#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa ++#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL ++#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L ++#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L ++#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L ++//RMI_UTCL1_STATUS ++#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++//RMI_SPARE ++#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 ++#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 ++#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 ++#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 ++#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 ++#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 ++#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 ++#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 ++#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 ++#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 ++#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L ++#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L ++#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L ++#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L ++#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L ++#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L ++#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L ++#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L ++#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L ++#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L ++//RMI_SPARE_1 ++#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 ++#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 ++#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 ++#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 ++#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 ++#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 ++#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 ++#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 ++#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 ++#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 ++#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L ++#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L ++#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L ++#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L ++#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L ++#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L ++#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L ++#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L ++#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L ++#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L ++//RMI_SPARE_2 ++#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 ++#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 ++#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 ++#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 ++#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 ++#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 ++#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 ++#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 ++#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 ++#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc ++#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 ++#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 ++#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L ++#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L ++#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L ++#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L ++#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L ++#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L ++#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L ++#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L ++#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L ++#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L ++#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L ++#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L ++ ++ ++// addressBlock: gc_utcl2_atcl2dec ++//ATC_L2_CNTL ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 ++#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 ++#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L ++#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L ++#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L ++//ATC_L2_CNTL2 ++#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 ++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 ++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf ++#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L ++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L ++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L ++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L ++//ATC_L2_CACHE_DATA0 ++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 ++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 ++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 ++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L ++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L ++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL ++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L ++//ATC_L2_CACHE_DATA1 ++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL ++//ATC_L2_CACHE_DATA2 ++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL ++//ATC_L2_CNTL3 ++#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 ++#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 ++#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 ++#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L ++#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L ++#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L ++//ATC_L2_STATUS ++#define ATC_L2_STATUS__BUSY__SHIFT 0x0 ++#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 ++#define ATC_L2_STATUS__BUSY_MASK 0x00000001L ++#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL ++//ATC_L2_STATUS2 ++#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 ++#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 ++#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL ++#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L ++//ATC_L2_MISC_CG ++#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 ++#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 ++#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L ++#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L ++#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L ++//ATC_L2_MEM_POWER_LS ++#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 ++#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 ++#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL ++#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L ++//ATC_L2_CGTT_CLK_CTRL ++#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++ ++ ++// addressBlock: gc_utcl2_vml2pfdec ++//VM_L2_CNTL ++#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 ++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 ++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 ++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 ++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 ++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 ++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa ++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb ++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc ++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf ++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 ++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 ++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 ++#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a ++#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L ++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L ++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL ++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L ++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L ++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L ++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L ++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L ++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L ++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L ++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L ++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L ++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L ++#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L ++//VM_L2_CNTL2 ++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 ++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 ++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 ++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 ++#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 ++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a ++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c ++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L ++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L ++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L ++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L ++#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L ++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L ++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L ++//VM_L2_CNTL3 ++#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf ++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 ++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 ++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d ++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e ++#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f ++#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L ++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L ++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L ++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L ++#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L ++//VM_L2_STATUS ++#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 ++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 ++#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 ++#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 ++#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 ++#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 ++#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 ++#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L ++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL ++#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L ++#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L ++#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L ++#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L ++#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L ++//VM_DUMMY_PAGE_FAULT_CNTL ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL ++//VM_DUMMY_PAGE_FAULT_ADDR_LO32 ++#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 ++#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//VM_DUMMY_PAGE_FAULT_ADDR_HI32 ++#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 ++#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL ++//VM_L2_PROTECTION_FAULT_CNTL ++#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 ++#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 ++#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 ++#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 ++#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 ++#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 ++#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb ++#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd ++#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f ++#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L ++#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L ++#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L ++#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L ++#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L ++#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L ++#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L ++#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L ++#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L ++#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L ++//VM_L2_PROTECTION_FAULT_CNTL2 ++#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 ++#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 ++#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL ++#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L ++#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L ++//VM_L2_PROTECTION_FAULT_MM_CNTL3 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_MM_CNTL4 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_STATUS ++#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 ++#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 ++#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 ++#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 ++#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 ++#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 ++#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 ++#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 ++#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 ++#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L ++#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL ++#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L ++#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L ++#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L ++#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L ++#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L ++#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L ++#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L ++#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L ++//VM_L2_PROTECTION_FAULT_ADDR_LO32 ++#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_ADDR_HI32 ++#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL ++//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL ++//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL ++//VM_L2_CNTL4 ++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 ++#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 ++#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 ++#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 ++#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 ++#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c ++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL ++#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L ++#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L ++#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L ++#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L ++#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L ++//VM_L2_MM_GROUP_RT_CLASSES ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L ++//VM_L2_BANK_SELECT_RESERVED_CID ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa ++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L ++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L ++//VM_L2_BANK_SELECT_RESERVED_CID2 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa ++#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L ++#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L ++//VM_L2_CACHE_PARITY_CNTL ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L ++//VM_L2_CGTT_CLK_CTRL ++#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++ ++ ++// addressBlock: gc_utcl2_vml2vcdec ++//VM_CONTEXT0_CNTL ++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT1_CNTL ++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT2_CNTL ++#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT3_CNTL ++#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT4_CNTL ++#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT5_CNTL ++#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT6_CNTL ++#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT7_CNTL ++#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT8_CNTL ++#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT9_CNTL ++#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT10_CNTL ++#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT11_CNTL ++#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT12_CNTL ++#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT13_CNTL ++#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT14_CNTL ++#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT15_CNTL ++#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXTS_DISABLE ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L ++//VM_INVALIDATE_ENG0_SEM ++#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG1_SEM ++#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG2_SEM ++#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG3_SEM ++#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG4_SEM ++#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG5_SEM ++#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG6_SEM ++#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG7_SEM ++#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG8_SEM ++#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG9_SEM ++#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG10_SEM ++#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG11_SEM ++#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG12_SEM ++#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG13_SEM ++#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG14_SEM ++#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG15_SEM ++#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG16_SEM ++#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG17_SEM ++#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG0_REQ ++#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG1_REQ ++#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG2_REQ ++#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG3_REQ ++#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG4_REQ ++#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG5_REQ ++#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG6_REQ ++#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG7_REQ ++#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG8_REQ ++#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG9_REQ ++#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG10_REQ ++#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG11_REQ ++#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG12_REQ ++#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG13_REQ ++#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG14_REQ ++#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG15_REQ ++#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG16_REQ ++#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG17_REQ ++#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG0_ACK ++#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG1_ACK ++#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG2_ACK ++#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG3_ACK ++#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG4_ACK ++#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG5_ACK ++#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG6_ACK ++#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG7_ACK ++#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG8_ACK ++#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG9_ACK ++#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG10_ACK ++#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG11_ACK ++#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG12_ACK ++#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG13_ACK ++#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG14_ACK ++#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG15_ACK ++#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG16_ACK ++#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG17_ACK ++#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++ ++ ++// addressBlock: gc_utcl2_vmsharedpfdec ++//MC_VM_NB_MMIOBASE ++#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 ++#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL ++//MC_VM_NB_MMIOLIMIT ++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 ++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL ++//MC_VM_NB_PCI_CTRL ++#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 ++#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L ++//MC_VM_NB_PCI_ARB ++#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 ++#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L ++//MC_VM_NB_TOP_OF_DRAM_SLOT1 ++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 ++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L ++//MC_VM_NB_LOWER_TOP_OF_DRAM2 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L ++//MC_VM_NB_UPPER_TOP_OF_DRAM2 ++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 ++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL ++//MC_VM_FB_OFFSET ++#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 ++#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL ++//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL ++//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL ++//MC_VM_STEERING ++#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 ++#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L ++//MC_SHARED_VIRT_RESET_REQ ++#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL ++#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//MC_MEM_POWER_LS ++#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 ++#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 ++#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL ++#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L ++//MC_VM_CACHEABLE_DRAM_ADDRESS_START ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_CACHEABLE_DRAM_ADDRESS_END ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_APT_CNTL ++#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 ++#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 ++#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L ++#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L ++//MC_VM_LOCAL_HBM_ADDRESS_START ++#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 ++#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_LOCAL_HBM_ADDRESS_END ++#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 ++#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL ++#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 ++#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L ++//MC_VM_XGMI_LFB_CNTL ++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 ++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x3 ++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L ++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000038L ++//MC_VM_XGMI_LFB_SIZE ++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 ++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL ++ ++ ++// addressBlock: gc_utcl2_vmsharedvcdec ++//MC_VM_FB_LOCATION_BASE ++#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 ++#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL ++//MC_VM_FB_LOCATION_TOP ++#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 ++#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL ++//MC_VM_AGP_TOP ++#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 ++#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL ++//MC_VM_AGP_BOT ++#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 ++#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL ++//MC_VM_AGP_BASE ++#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 ++#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL ++//MC_VM_SYSTEM_APERTURE_LOW_ADDR ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL ++//MC_VM_SYSTEM_APERTURE_HIGH_ADDR ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL ++//MC_VM_MX_L1_TLB_CNTL ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 ++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 ++#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb ++#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L ++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L ++#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L ++#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L ++ ++ ++// addressBlock: gc_ea_gceadec ++//GCEA_DRAM_RD_CLI2GRP_MAP0 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//GCEA_DRAM_RD_CLI2GRP_MAP1 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//GCEA_DRAM_WR_CLI2GRP_MAP0 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//GCEA_DRAM_WR_CLI2GRP_MAP1 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//GCEA_DRAM_RD_GRP2VC_MAP ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//GCEA_DRAM_WR_GRP2VC_MAP ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//GCEA_DRAM_RD_LAZY ++#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++//GCEA_DRAM_WR_LAZY ++#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++//GCEA_DRAM_RD_CAM_CNTL ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++//GCEA_DRAM_WR_CAM_CNTL ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++//GCEA_DRAM_PAGE_BURST ++#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//GCEA_DRAM_RD_PRI_AGE ++#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//GCEA_DRAM_WR_PRI_AGE ++#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//GCEA_DRAM_RD_PRI_QUEUING ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//GCEA_DRAM_WR_PRI_QUEUING ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//GCEA_DRAM_RD_PRI_FIXED ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//GCEA_DRAM_WR_PRI_FIXED ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//GCEA_DRAM_RD_PRI_URGENCY ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//GCEA_DRAM_WR_PRI_URGENCY ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//GCEA_DRAM_RD_PRI_QUANT_PRI1 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_DRAM_RD_PRI_QUANT_PRI2 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_DRAM_RD_PRI_QUANT_PRI3 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_DRAM_WR_PRI_QUANT_PRI1 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_DRAM_WR_PRI_QUANT_PRI2 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_DRAM_WR_PRI_QUANT_PRI3 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_ADDRNORM_BASE_ADDR0 ++#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 ++#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 ++#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 ++#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc ++#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L ++#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L ++#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L ++#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L ++//GCEA_ADDRNORM_LIMIT_ADDR0 ++#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 ++#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa ++#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc ++#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL ++#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L ++#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L ++//GCEA_ADDRNORM_BASE_ADDR1 ++#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 ++#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 ++#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 ++#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc ++#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L ++#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L ++#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L ++#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L ++//GCEA_ADDRNORM_LIMIT_ADDR1 ++#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 ++#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa ++#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc ++#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL ++#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L ++#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L ++//GCEA_ADDRNORM_OFFSET_ADDR1 ++#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 ++#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 ++#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L ++#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L ++//GCEA_ADDRNORMDRAM_HOLE_CNTL ++#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 ++#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 ++#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L ++#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L ++//GCEA_ADDRNORMDRAM_TRICHANNEL_CFG ++#define GCEA_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0 ++#define GCEA_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL ++//GCEA_ADDRDEC_BANK_CFG ++#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 ++#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 ++#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL ++#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L ++#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L ++//GCEA_ADDRDEC_MISC_CFG ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 ++#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 ++#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 ++#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc ++#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 ++#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 ++#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 ++#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a ++#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L ++#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L ++#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L ++#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L ++#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L ++#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L ++#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L ++#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L ++#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L ++#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L ++//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L ++//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L ++//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L ++//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L ++//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL ++#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L ++//GCEA_ADDRDECDRAM_ADDR_HASH_PC ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L ++//GCEA_ADDRDECDRAM_ADDR_HASH_PC2 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL ++//GCEA_ADDRDECDRAM_ADDR_HASH_CS0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDECDRAM_ADDR_HASH_CS1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDECDRAM_HARVEST_ENABLE ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L ++#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L ++//GCEA_ADDRDEC0_BASE_ADDR_CS0 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_BASE_ADDR_CS1 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_BASE_ADDR_CS2 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_BASE_ADDR_CS3 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_BASE_ADDR_SECCS0 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_BASE_ADDR_SECCS1 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_BASE_ADDR_SECCS2 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_BASE_ADDR_SECCS3 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_ADDR_MASK_CS01 ++#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_ADDR_MASK_CS23 ++#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_ADDR_MASK_SECCS01 ++#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_ADDR_MASK_SECCS23 ++#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC0_ADDR_CFG_CS01 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//GCEA_ADDRDEC0_ADDR_CFG_CS23 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//GCEA_ADDRDEC0_ADDR_SEL_CS01 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//GCEA_ADDRDEC0_ADDR_SEL_CS23 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//GCEA_ADDRDEC0_COL_SEL_LO_CS01 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//GCEA_ADDRDEC0_COL_SEL_LO_CS23 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//GCEA_ADDRDEC0_COL_SEL_HI_CS01 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//GCEA_ADDRDEC0_COL_SEL_HI_CS23 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//GCEA_ADDRDEC0_RM_SEL_CS01 ++#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_ADDRDEC0_RM_SEL_CS23 ++#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_ADDRDEC0_RM_SEL_SECCS01 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_ADDRDEC0_RM_SEL_SECCS23 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_ADDRDEC1_BASE_ADDR_CS0 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_BASE_ADDR_CS1 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_BASE_ADDR_CS2 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_BASE_ADDR_CS3 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_BASE_ADDR_SECCS0 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_BASE_ADDR_SECCS1 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_BASE_ADDR_SECCS2 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_BASE_ADDR_SECCS3 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_ADDR_MASK_CS01 ++#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_ADDR_MASK_CS23 ++#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_ADDR_MASK_SECCS01 ++#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_ADDR_MASK_SECCS23 ++#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//GCEA_ADDRDEC1_ADDR_CFG_CS01 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//GCEA_ADDRDEC1_ADDR_CFG_CS23 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//GCEA_ADDRDEC1_ADDR_SEL_CS01 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//GCEA_ADDRDEC1_ADDR_SEL_CS23 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//GCEA_ADDRDEC1_COL_SEL_LO_CS01 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//GCEA_ADDRDEC1_COL_SEL_LO_CS23 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//GCEA_ADDRDEC1_COL_SEL_HI_CS01 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//GCEA_ADDRDEC1_COL_SEL_HI_CS23 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//GCEA_ADDRDEC1_RM_SEL_CS01 ++#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_ADDRDEC1_RM_SEL_CS23 ++#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_ADDRDEC1_RM_SEL_SECCS01 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_ADDRDEC1_RM_SEL_SECCS23 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//GCEA_IO_RD_CLI2GRP_MAP0 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//GCEA_IO_RD_CLI2GRP_MAP1 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//GCEA_IO_WR_CLI2GRP_MAP0 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//GCEA_IO_WR_CLI2GRP_MAP1 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//GCEA_IO_RD_COMBINE_FLUSH ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//GCEA_IO_WR_COMBINE_FLUSH ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//GCEA_IO_GROUP_BURST ++#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//GCEA_IO_RD_PRI_AGE ++#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//GCEA_IO_WR_PRI_AGE ++#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//GCEA_IO_RD_PRI_QUEUING ++#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//GCEA_IO_WR_PRI_QUEUING ++#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//GCEA_IO_RD_PRI_FIXED ++#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//GCEA_IO_WR_PRI_FIXED ++#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//GCEA_IO_RD_PRI_URGENCY ++#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//GCEA_IO_WR_PRI_URGENCY ++#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//GCEA_IO_RD_PRI_URGENCY_MASK ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L ++#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L ++//GCEA_IO_WR_PRI_URGENCY_MASK ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L ++#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L ++//GCEA_IO_RD_PRI_QUANT_PRI1 ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_IO_RD_PRI_QUANT_PRI2 ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_IO_RD_PRI_QUANT_PRI3 ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_IO_WR_PRI_QUANT_PRI1 ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_IO_WR_PRI_QUANT_PRI2 ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_IO_WR_PRI_QUANT_PRI3 ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//GCEA_SDP_ARB_DRAM ++#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 ++#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 ++#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 ++#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL ++#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L ++#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L ++#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L ++//GCEA_SDP_ARB_FINAL ++#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 ++#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 ++#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa ++#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 ++#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 ++#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a ++#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL ++#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L ++#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L ++#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L ++#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L ++#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L ++#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L ++//GCEA_SDP_DRAM_PRIORITY ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//GCEA_SDP_IO_PRIORITY ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//GCEA_SDP_CREDITS ++#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 ++#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 ++#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 ++#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 ++#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL ++#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L ++#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L ++#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L ++//GCEA_SDP_TAG_RESERVE0 ++#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 ++#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 ++#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 ++#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 ++#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL ++#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L ++#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L ++#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L ++//GCEA_SDP_TAG_RESERVE1 ++#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 ++#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 ++#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 ++#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 ++#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL ++#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L ++#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L ++#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L ++//GCEA_SDP_VCC_RESERVE0 ++#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//GCEA_SDP_VCC_RESERVE1 ++#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//GCEA_SDP_VCD_RESERVE0 ++#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//GCEA_SDP_VCD_RESERVE1 ++#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//GCEA_SDP_REQ_CNTL ++#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 ++#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 ++#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 ++#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 ++#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 ++#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L ++#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L ++#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L ++#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L ++#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L ++//GCEA_MISC ++#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 ++#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 ++#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 ++#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 ++#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 ++#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd ++#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe ++#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf ++#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 ++#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 ++#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 ++#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a ++#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b ++#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c ++#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d ++#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e ++#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f ++#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L ++#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L ++#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L ++#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L ++#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L ++#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L ++#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L ++#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L ++#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L ++#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L ++#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L ++#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L ++#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L ++#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L ++#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L ++#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L ++#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L ++#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L ++//GCEA_LATENCY_SAMPLING ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L ++#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L ++#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L ++//GCEA_PERFCOUNTER_LO ++#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//GCEA_PERFCOUNTER_HI ++#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//GCEA_PERFCOUNTER0_CFG ++#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//GCEA_PERFCOUNTER1_CFG ++#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++ ++ ++// addressBlock: gc_tcdec ++//TCP_INVALIDATE ++#define TCP_INVALIDATE__START__SHIFT 0x0 ++#define TCP_INVALIDATE__START_MASK 0x00000001L ++//TCP_STATUS ++#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 ++#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 ++#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 ++#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 ++#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 ++#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 ++#define TCP_STATUS__READ_BUSY__SHIFT 0x6 ++#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 ++#define TCP_STATUS__VM_BUSY__SHIFT 0x8 ++#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L ++#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L ++#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L ++#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L ++#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L ++#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L ++#define TCP_STATUS__READ_BUSY_MASK 0x00000040L ++#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L ++#define TCP_STATUS__VM_BUSY_MASK 0x00000100L ++//TCP_CNTL ++#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 ++#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 ++#define TCP_CNTL__L1_SIZE__SHIFT 0x2 ++#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 ++#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 ++#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf ++#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 ++#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c ++#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d ++#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e ++#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L ++#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L ++#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL ++#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L ++#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L ++#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L ++#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L ++#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L ++#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L ++#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L ++//TCP_CHAN_STEER_LO ++#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 ++#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 ++#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 ++#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc ++#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 ++#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 ++#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 ++#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c ++#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL ++#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L ++#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L ++#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L ++#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L ++#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L ++#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L ++#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L ++//TCP_CHAN_STEER_HI ++#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 ++#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 ++#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 ++#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc ++#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 ++#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 ++#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 ++#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c ++#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL ++#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L ++#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L ++#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L ++#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L ++#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L ++#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L ++#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L ++//TCP_ADDR_CONFIG ++#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 ++#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 ++#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 ++#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 ++#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL ++#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L ++#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L ++#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L ++//TCP_CREDIT ++#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 ++#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 ++#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d ++#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL ++#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L ++#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L ++//TCP_BUFFER_ADDR_HASH_CNTL ++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 ++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 ++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 ++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 ++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L ++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L ++#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L ++#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L ++//TC_CFG_L1_LOAD_POLICY0 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L ++#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L ++//TC_CFG_L1_LOAD_POLICY1 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L ++#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L ++//TC_CFG_L1_STORE_POLICY ++#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 ++#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 ++#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 ++#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 ++#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 ++#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 ++#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 ++#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 ++#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 ++#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 ++#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa ++#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb ++#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc ++#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd ++#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe ++#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf ++#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 ++#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 ++#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 ++#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 ++#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 ++#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 ++#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 ++#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 ++#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 ++#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 ++#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a ++#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b ++#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c ++#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d ++#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e ++#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f ++#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L ++#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L ++#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L ++#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L ++#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L ++#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L ++#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L ++#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L ++#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L ++#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L ++#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L ++#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L ++#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L ++#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L ++//TC_CFG_L2_LOAD_POLICY0 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L ++#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L ++//TC_CFG_L2_LOAD_POLICY1 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L ++#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L ++//TC_CFG_L2_STORE_POLICY0 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa ++#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc ++#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe ++#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 ++#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a ++#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c ++#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e ++#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL ++#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L ++#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L ++//TC_CFG_L2_STORE_POLICY1 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa ++#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc ++#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe ++#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 ++#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a ++#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c ++#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e ++#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL ++#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L ++#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L ++//TC_CFG_L2_ATOMIC_POLICY ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L ++#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L ++//TC_CFG_L1_VOLATILE ++#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 ++#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL ++//TC_CFG_L2_VOLATILE ++#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 ++#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL ++//TCI_STATUS ++#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 ++#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L ++//TCI_CNTL_1 ++#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 ++#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 ++#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 ++#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL ++#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L ++#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L ++//TCI_CNTL_2 ++#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 ++#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 ++#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L ++#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL ++//TCC_CTRL ++#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 ++#define TCC_CTRL__RATE__SHIFT 0x2 ++#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 ++#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 ++#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc ++#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 ++#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15 ++#define TCC_CTRL__MDC_SIZE__SHIFT 0x18 ++#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a ++#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c ++#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L ++#define TCC_CTRL__RATE_MASK 0x0000000CL ++#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L ++#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L ++#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L ++#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L ++#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L ++#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L ++#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L ++#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L ++//TCC_CTRL2 ++#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 ++#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL ++//TCC_REDUNDANCY ++#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 ++#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 ++#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L ++#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L ++//TCC_EXE_DISABLE ++#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 ++#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L ++//TCC_DSM_CNTL ++#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 ++#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 ++#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 ++#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 ++#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 ++#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 ++#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 ++#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a ++#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b ++#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d ++#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L ++#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L ++#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L ++#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L ++#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L ++#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L ++#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L ++#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L ++#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L ++#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L ++#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L ++#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L ++//TCC_DSM_CNTLA ++#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 ++#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 ++#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 ++#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 ++#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 ++#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 ++#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 ++#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb ++#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc ++#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe ++#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf ++#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 ++#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 ++#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 ++#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15 ++#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 ++#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18 ++#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a ++#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b ++#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d ++#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L ++#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L ++#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L ++#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L ++#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L ++#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L ++#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L ++#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L ++#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L ++#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L ++#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L ++#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L ++#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L ++#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L ++#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L ++#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L ++#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L ++#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L ++#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L ++#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L ++//TCC_DSM_CNTL2 ++#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a ++#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L ++//TCC_DSM_CNTL2A ++#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb ++#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe ++#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 ++#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a ++#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b ++#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d ++#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L ++#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L ++#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L ++#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L ++//TCC_DSM_CNTL2B ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L ++//TCC_WBINVL2 ++#define TCC_WBINVL2__DONE__SHIFT 0x4 ++#define TCC_WBINVL2__DONE_MASK 0x00000010L ++//TCC_SOFT_RESET ++#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 ++#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L ++//TCA_CTRL ++#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 ++#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 ++#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 ++#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 ++#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 ++#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL ++#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L ++#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L ++#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L ++#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L ++//TCA_BURST_MASK ++#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 ++#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL ++//TCA_BURST_CTRL ++#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 ++#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3 ++#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 ++#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 ++#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 ++#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 ++#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8 ++#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9 ++#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa ++#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb ++#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc ++#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd ++#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe ++#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L ++#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L ++#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L ++#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L ++#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L ++#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L ++#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L ++#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L ++#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L ++#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L ++#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L ++#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L ++#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L ++//TCA_DSM_CNTL ++#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 ++#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 ++#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 ++#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 ++#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L ++#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L ++#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L ++#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L ++//TCA_DSM_CNTL2 ++#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a ++#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L ++ ++ ++// addressBlock: gc_shdec ++//SPI_SHADER_PGM_RSRC3_PS ++#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a ++#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL ++#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L ++#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L ++#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L ++//SPI_SHADER_PGM_LO_PS ++#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_HI_PS ++#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL ++//SPI_SHADER_PGM_RSRC1_PS ++#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa ++#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc ++#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 ++#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 ++#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 ++#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 ++#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d ++#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL ++#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L ++#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L ++#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L ++#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L ++#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L ++#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L ++#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L ++#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L ++#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L ++#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L ++//SPI_SHADER_PGM_RSRC2_PS ++#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 ++#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 ++#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 ++#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 ++#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a ++#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b ++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L ++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL ++#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L ++#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L ++#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L ++#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L ++#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L ++#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L ++#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L ++#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L ++//SPI_SHADER_USER_DATA_PS_0 ++#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_1 ++#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_2 ++#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_3 ++#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_4 ++#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_5 ++#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_6 ++#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_7 ++#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_8 ++#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_9 ++#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_10 ++#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_11 ++#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_12 ++#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_13 ++#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_14 ++#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_15 ++#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_16 ++#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_17 ++#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_18 ++#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_19 ++#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_20 ++#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_21 ++#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_22 ++#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_23 ++#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_24 ++#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_25 ++#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_26 ++#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_27 ++#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_28 ++#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_29 ++#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_30 ++#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_PS_31 ++#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_RSRC3_VS ++#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a ++#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL ++#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L ++#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L ++#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L ++//SPI_SHADER_LATE_ALLOC_VS ++#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 ++#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL ++//SPI_SHADER_PGM_LO_VS ++#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_HI_VS ++#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL ++//SPI_SHADER_PGM_RSRC1_VS ++#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa ++#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc ++#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 ++#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 ++#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 ++#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 ++#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a ++#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e ++#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f ++#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL ++#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L ++#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L ++#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L ++#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L ++#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L ++#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L ++#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L ++#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L ++#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L ++#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L ++#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L ++//SPI_SHADER_PGM_RSRC2_VS ++#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 ++#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb ++#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc ++#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd ++#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 ++#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b ++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L ++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL ++#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L ++#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L ++#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L ++#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L ++#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L ++#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L ++#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L ++#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L ++#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L ++//SPI_SHADER_USER_DATA_VS_0 ++#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_1 ++#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_2 ++#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_3 ++#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_4 ++#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_5 ++#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_6 ++#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_7 ++#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_8 ++#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_9 ++#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_10 ++#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_11 ++#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_12 ++#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_13 ++#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_14 ++#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_15 ++#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_16 ++#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_17 ++#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_18 ++#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_19 ++#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_20 ++#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_21 ++#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_22 ++#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_23 ++#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_24 ++#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_25 ++#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_26 ++#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_27 ++#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_28 ++#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_29 ++#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_30 ++#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_VS_31 ++#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_RSRC2_GS_VS ++#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 ++#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 ++#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 ++#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 ++#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b ++#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L ++#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL ++#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L ++#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L ++#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L ++#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L ++#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L ++#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L ++#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L ++//SPI_SHADER_PGM_RSRC4_GS ++#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 ++#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL ++#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L ++//SPI_SHADER_USER_DATA_ADDR_LO_GS ++#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ADDR_HI_GS ++#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_LO_ES ++#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_HI_ES ++#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL ++//SPI_SHADER_PGM_RSRC3_GS ++#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a ++#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL ++#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L ++#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L ++#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L ++//SPI_SHADER_PGM_LO_GS ++#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_HI_GS ++#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL ++//SPI_SHADER_PGM_RSRC1_GS ++#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa ++#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc ++#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 ++#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 ++#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 ++#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 ++#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d ++#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f ++#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL ++#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L ++#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L ++#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L ++#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L ++#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L ++#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L ++#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L ++#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L ++#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L ++#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L ++#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L ++//SPI_SHADER_PGM_RSRC2_GS ++#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 ++#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 ++#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 ++#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 ++#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b ++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L ++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL ++#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L ++#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L ++#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L ++#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L ++#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L ++#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L ++#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L ++//SPI_SHADER_USER_DATA_ES_0 ++#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_1 ++#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_2 ++#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_3 ++#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_4 ++#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_5 ++#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_6 ++#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_7 ++#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_8 ++#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_9 ++#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_10 ++#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_11 ++#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_12 ++#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_13 ++#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_14 ++#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_15 ++#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_16 ++#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_17 ++#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_18 ++#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_19 ++#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_20 ++#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_21 ++#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_22 ++#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_23 ++#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_24 ++#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_25 ++#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_26 ++#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_27 ++#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_28 ++#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_29 ++#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_30 ++#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ES_31 ++#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_RSRC4_HS ++#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL ++//SPI_SHADER_USER_DATA_ADDR_LO_HS ++#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_ADDR_HI_HS ++#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_LO_LS ++#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_HI_LS ++#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL ++//SPI_SHADER_PGM_RSRC3_HS ++#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa ++#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL ++#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L ++#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L ++#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L ++//SPI_SHADER_PGM_LO_HS ++#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL ++//SPI_SHADER_PGM_HI_HS ++#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 ++#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL ++//SPI_SHADER_PGM_RSRC1_HS ++#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa ++#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc ++#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 ++#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 ++#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 ++#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 ++#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b ++#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e ++#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL ++#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L ++#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L ++#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L ++#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L ++#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L ++#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L ++#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L ++#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L ++#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L ++#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L ++//SPI_SHADER_PGM_RSRC2_HS ++#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 ++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 ++#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 ++#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 ++#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 ++#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b ++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c ++#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L ++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL ++#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L ++#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L ++#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L ++#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L ++#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L ++//SPI_SHADER_USER_DATA_LS_0 ++#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_1 ++#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_2 ++#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_3 ++#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_4 ++#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_5 ++#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_6 ++#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_7 ++#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_8 ++#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_9 ++#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_10 ++#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_11 ++#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_12 ++#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_13 ++#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_14 ++#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_15 ++#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_16 ++#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_17 ++#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_18 ++#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_19 ++#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_20 ++#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_21 ++#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_22 ++#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_23 ++#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_24 ++#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_25 ++#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_26 ++#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_27 ++#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_28 ++#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_29 ++#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_30 ++#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_LS_31 ++#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_0 ++#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_1 ++#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_2 ++#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_3 ++#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_4 ++#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_5 ++#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_6 ++#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_7 ++#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_8 ++#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_9 ++#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_10 ++#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_11 ++#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_12 ++#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_13 ++#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_14 ++#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_15 ++#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_16 ++#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_17 ++#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_18 ++#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_19 ++#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_20 ++#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_21 ++#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_22 ++#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_23 ++#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_24 ++#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_25 ++#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_26 ++#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_27 ++#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_28 ++#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_29 ++#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_30 ++#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL ++//SPI_SHADER_USER_DATA_COMMON_31 ++#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 ++#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_DISPATCH_INITIATOR ++#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 ++#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 ++#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 ++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 ++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 ++#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 ++#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 ++#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa ++#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb ++#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc ++#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe ++#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L ++#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L ++#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L ++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L ++#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L ++#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L ++#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L ++#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L ++#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L ++#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L ++#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L ++//COMPUTE_DIM_X ++#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 ++#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL ++//COMPUTE_DIM_Y ++#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 ++#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL ++//COMPUTE_DIM_Z ++#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 ++#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL ++//COMPUTE_START_X ++#define COMPUTE_START_X__START__SHIFT 0x0 ++#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL ++//COMPUTE_START_Y ++#define COMPUTE_START_Y__START__SHIFT 0x0 ++#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL ++//COMPUTE_START_Z ++#define COMPUTE_START_Z__START__SHIFT 0x0 ++#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL ++//COMPUTE_NUM_THREAD_X ++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 ++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 ++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL ++#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L ++//COMPUTE_NUM_THREAD_Y ++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 ++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 ++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL ++#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L ++//COMPUTE_NUM_THREAD_Z ++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 ++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 ++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL ++#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L ++//COMPUTE_PIPELINESTAT_ENABLE ++#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 ++#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L ++//COMPUTE_PERFCOUNT_ENABLE ++#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 ++#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L ++//COMPUTE_PGM_LO ++#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 ++#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_PGM_HI ++#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 ++#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL ++//COMPUTE_DISPATCH_PKT_ADDR_LO ++#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 ++#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_DISPATCH_PKT_ADDR_HI ++#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 ++#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL ++//COMPUTE_DISPATCH_SCRATCH_BASE_LO ++#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 ++#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_DISPATCH_SCRATCH_BASE_HI ++#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 ++#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL ++//COMPUTE_PGM_RSRC1 ++#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 ++#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 ++#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa ++#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc ++#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 ++#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 ++#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 ++#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 ++#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 ++#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 ++#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a ++#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL ++#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L ++#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L ++#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L ++#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L ++#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L ++#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L ++#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L ++#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L ++#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L ++#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L ++//COMPUTE_PGM_RSRC2 ++#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 ++#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 ++#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 ++#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 ++#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 ++#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 ++#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa ++#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb ++#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd ++#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf ++#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 ++#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f ++#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L ++#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL ++#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L ++#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L ++#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L ++#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L ++#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L ++#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L ++#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L ++#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L ++#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L ++#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L ++//COMPUTE_VMID ++#define COMPUTE_VMID__DATA__SHIFT 0x0 ++#define COMPUTE_VMID__DATA_MASK 0x0000000FL ++//COMPUTE_RESOURCE_LIMITS ++#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 ++#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc ++#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 ++#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 ++#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 ++#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 ++#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b ++#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL ++#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L ++#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L ++#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L ++#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L ++#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L ++#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L ++//COMPUTE_STATIC_THREAD_MGMT_SE0 ++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 ++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 ++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL ++#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L ++//COMPUTE_STATIC_THREAD_MGMT_SE1 ++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 ++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 ++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL ++#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L ++//COMPUTE_TMPRING_SIZE ++#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 ++#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc ++#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL ++#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L ++//COMPUTE_STATIC_THREAD_MGMT_SE2 ++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 ++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 ++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL ++#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L ++//COMPUTE_STATIC_THREAD_MGMT_SE3 ++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 ++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 ++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL ++#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L ++//COMPUTE_RESTART_X ++#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 ++#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL ++//COMPUTE_RESTART_Y ++#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 ++#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL ++//COMPUTE_RESTART_Z ++#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 ++#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL ++//COMPUTE_THREAD_TRACE_ENABLE ++#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 ++#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L ++//COMPUTE_MISC_RESERVED ++#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 ++#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 ++#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 ++#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 ++#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 ++#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L ++#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L ++#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L ++#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L ++#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L ++//COMPUTE_DISPATCH_ID ++#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 ++#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL ++//COMPUTE_THREADGROUP_ID ++#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 ++#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL ++//COMPUTE_RELAUNCH ++#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 ++#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e ++#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f ++#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL ++#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L ++#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L ++//COMPUTE_WAVE_RESTORE_ADDR_LO ++#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 ++#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL ++//COMPUTE_WAVE_RESTORE_ADDR_HI ++#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 ++#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL ++//COMPUTE_SHADER_CHKSUM ++#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 ++#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_0 ++#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_1 ++#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_2 ++#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_3 ++#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_4 ++#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_5 ++#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_6 ++#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_7 ++#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_8 ++#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_9 ++#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_10 ++#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_11 ++#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_12 ++#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_13 ++#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_14 ++#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_USER_DATA_15 ++#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 ++#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_DISPATCH_END ++#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 ++#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL ++//COMPUTE_NOWHERE ++#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 ++#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gc_cppdec ++//CP_DFY_CNTL ++#define CP_DFY_CNTL__POLICY__SHIFT 0x0 ++#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 ++#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a ++#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c ++#define CP_DFY_CNTL__MODE__SHIFT 0x1d ++#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f ++#define CP_DFY_CNTL__POLICY_MASK 0x00000001L ++#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL ++#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L ++#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L ++#define CP_DFY_CNTL__MODE_MASK 0x60000000L ++#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L ++//CP_DFY_STAT ++#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 ++#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 ++#define CP_DFY_STAT__BUSY__SHIFT 0x1f ++#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL ++#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L ++#define CP_DFY_STAT__BUSY_MASK 0x80000000L ++//CP_DFY_ADDR_HI ++#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL ++//CP_DFY_ADDR_LO ++#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 ++#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L ++//CP_DFY_DATA_0 ++#define CP_DFY_DATA_0__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_1 ++#define CP_DFY_DATA_1__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_2 ++#define CP_DFY_DATA_2__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_3 ++#define CP_DFY_DATA_3__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_4 ++#define CP_DFY_DATA_4__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_5 ++#define CP_DFY_DATA_5__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_6 ++#define CP_DFY_DATA_6__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_7 ++#define CP_DFY_DATA_7__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_8 ++#define CP_DFY_DATA_8__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_9 ++#define CP_DFY_DATA_9__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_10 ++#define CP_DFY_DATA_10__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_11 ++#define CP_DFY_DATA_11__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_12 ++#define CP_DFY_DATA_12__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_13 ++#define CP_DFY_DATA_13__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_14 ++#define CP_DFY_DATA_14__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_DATA_15 ++#define CP_DFY_DATA_15__DATA__SHIFT 0x0 ++#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL ++//CP_DFY_CMD ++#define CP_DFY_CMD__OFFSET__SHIFT 0x0 ++#define CP_DFY_CMD__SIZE__SHIFT 0x10 ++#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL ++#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L ++//CP_EOPQ_WAIT_TIME ++#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 ++#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa ++#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL ++#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L ++//CP_CPC_MGCG_SYNC_CNTL ++#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 ++#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 ++#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL ++#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L ++//CPC_INT_INFO ++#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 ++#define CPC_INT_INFO__TYPE__SHIFT 0x10 ++#define CPC_INT_INFO__VMID__SHIFT 0x14 ++#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c ++#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL ++#define CPC_INT_INFO__TYPE_MASK 0x00010000L ++#define CPC_INT_INFO__VMID_MASK 0x00F00000L ++#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L ++//CP_VIRT_STATUS ++#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 ++#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL ++//CPC_INT_ADDR ++#define CPC_INT_ADDR__ADDR__SHIFT 0x0 ++#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL ++//CPC_INT_PASID ++#define CPC_INT_PASID__PASID__SHIFT 0x0 ++#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL ++//CP_GFX_ERROR ++#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 ++#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 ++#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 ++#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 ++#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 ++#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 ++#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa ++#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb ++#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc ++#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd ++#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe ++#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf ++#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 ++#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 ++#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 ++#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 ++#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 ++#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 ++#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 ++#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 ++#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 ++#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 ++#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a ++#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b ++#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c ++#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d ++#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e ++#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f ++#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L ++#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L ++#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L ++#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L ++#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L ++#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L ++#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L ++#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L ++#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L ++#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L ++#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L ++#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L ++#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L ++#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L ++#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L ++#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L ++#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L ++#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L ++#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L ++#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L ++#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L ++#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L ++#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L ++#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L ++#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L ++#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L ++#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L ++#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L ++//CPG_UTCL1_CNTL ++#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 ++#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 ++#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 ++#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a ++#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c ++#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e ++#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L ++#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L ++#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L ++#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L ++#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L ++#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L ++//CPC_UTCL1_CNTL ++#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 ++#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 ++#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a ++#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c ++#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e ++#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L ++#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L ++#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L ++#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L ++#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L ++//CPF_UTCL1_CNTL ++#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 ++#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 ++#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 ++#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a ++#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c ++#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e ++#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f ++#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L ++#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L ++#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L ++#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L ++#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L ++#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L ++#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L ++//CP_AQL_SMM_STATUS ++#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 ++#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL ++//CP_RB0_BASE ++#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 ++#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL ++//CP_RB_BASE ++#define CP_RB_BASE__RB_BASE__SHIFT 0x0 ++#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL ++//CP_RB0_CNTL ++#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 ++#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 ++#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 ++#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 ++#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 ++#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 ++#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b ++#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f ++#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL ++#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L ++#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L ++#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L ++#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L ++#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L ++#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L ++#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L ++//CP_RB_CNTL ++#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 ++#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 ++#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 ++#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 ++#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 ++#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b ++#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f ++#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL ++#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L ++#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L ++#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L ++#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L ++#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L ++#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L ++//CP_RB_RPTR_WR ++#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 ++#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL ++//CP_RB0_RPTR_ADDR ++#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 ++#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL ++//CP_RB_RPTR_ADDR ++#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 ++#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL ++//CP_RB0_RPTR_ADDR_HI ++#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 ++#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL ++//CP_RB_RPTR_ADDR_HI ++#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 ++#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL ++//CP_RB0_BUFSZ_MASK ++#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 ++#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL ++//CP_RB_BUFSZ_MASK ++#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 ++#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL ++//CP_RB_WPTR_POLL_ADDR_LO ++#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 ++#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL ++//CP_RB_WPTR_POLL_ADDR_HI ++#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 ++#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL ++//CP_INT_CNTL ++#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb ++#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 ++#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 ++#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 ++#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 ++#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 ++#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L ++#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L ++#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L ++#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L ++#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L ++#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L ++#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_INT_STATUS ++#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb ++#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe ++#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 ++#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 ++#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 ++#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 ++#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 ++#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 ++#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 ++#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 ++#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 ++#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a ++#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b ++#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d ++#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e ++#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f ++#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L ++#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L ++#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L ++#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L ++#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L ++#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L ++#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L ++#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L ++#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L ++#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L ++#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L ++#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L ++#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L ++#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L ++#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L ++#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L ++//CP_DEVICE_ID ++#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 ++#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL ++//CP_ME0_PIPE_PRIORITY_CNTS ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L ++#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L ++//CP_RING_PRIORITY_CNTS ++#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 ++#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 ++#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 ++#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 ++#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL ++#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L ++#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L ++#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L ++//CP_ME0_PIPE0_PRIORITY ++#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_RING0_PRIORITY ++#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME0_PIPE1_PRIORITY ++#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_RING1_PRIORITY ++#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME0_PIPE2_PRIORITY ++#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_RING2_PRIORITY ++#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_FATAL_ERROR ++#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 ++#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 ++#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 ++#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 ++#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 ++#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L ++#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L ++#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L ++#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L ++#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L ++//CP_RB_VMID ++#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 ++#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 ++#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 ++#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL ++#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L ++#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L ++//CP_ME0_PIPE0_VMID ++#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 ++#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL ++//CP_ME0_PIPE1_VMID ++#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 ++#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL ++//CP_RB0_WPTR ++#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 ++#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL ++//CP_RB_WPTR ++#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 ++#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL ++//CP_RB0_WPTR_HI ++#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 ++#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL ++//CP_RB_WPTR_HI ++#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 ++#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL ++//CP_RB1_WPTR ++#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 ++#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL ++//CP_RB1_WPTR_HI ++#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 ++#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL ++//CP_RB2_WPTR ++#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 ++#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL ++//CP_RB_DOORBELL_CONTROL ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_RANGE_LOWER ++#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 ++#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL ++//CP_RB_DOORBELL_RANGE_UPPER ++#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 ++#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL ++//CP_MEC_DOORBELL_RANGE_LOWER ++#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 ++#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL ++//CP_MEC_DOORBELL_RANGE_UPPER ++#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 ++#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL ++//CPG_UTCL1_ERROR ++#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 ++#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L ++//CPC_UTCL1_ERROR ++#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 ++#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L ++//CP_RB1_BASE ++#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 ++#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL ++//CP_RB1_CNTL ++#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 ++#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 ++#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 ++#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 ++#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 ++#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b ++#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f ++#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL ++#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L ++#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L ++#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L ++#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L ++#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L ++#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L ++//CP_RB1_RPTR_ADDR ++#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 ++#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL ++//CP_RB1_RPTR_ADDR_HI ++#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 ++#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL ++//CP_RB2_BASE ++#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 ++#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL ++//CP_RB2_CNTL ++#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 ++#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 ++#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 ++#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 ++#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 ++#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b ++#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f ++#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL ++#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L ++#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L ++#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L ++#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L ++#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L ++#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L ++//CP_RB2_RPTR_ADDR ++#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 ++#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL ++//CP_RB2_RPTR_ADDR_HI ++#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 ++#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL ++//CP_RB0_ACTIVE ++#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 ++#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L ++//CP_RB_ACTIVE ++#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 ++#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L ++//CP_INT_CNTL_RING0 ++#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb ++#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 ++#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 ++#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 ++#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 ++#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 ++#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L ++#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L ++#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L ++#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L ++#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L ++#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L ++#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_INT_CNTL_RING1 ++#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb ++#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 ++#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 ++#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 ++#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 ++#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 ++#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L ++#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L ++#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L ++#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L ++#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L ++#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L ++#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_INT_CNTL_RING2 ++#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb ++#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 ++#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 ++#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 ++#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 ++#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 ++#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L ++#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L ++#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L ++#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L ++#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L ++#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L ++#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_INT_STATUS_RING0 ++#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb ++#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe ++#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 ++#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 ++#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 ++#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 ++#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 ++#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 ++#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 ++#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 ++#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 ++#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a ++#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b ++#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d ++#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e ++#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f ++#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L ++#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L ++#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L ++#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L ++#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L ++#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L ++#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L ++#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L ++#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L ++#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L ++#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L ++#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L ++#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L ++#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L ++#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L ++#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L ++//CP_INT_STATUS_RING1 ++#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb ++#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe ++#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 ++#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 ++#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 ++#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 ++#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 ++#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 ++#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 ++#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 ++#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 ++#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a ++#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b ++#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d ++#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e ++#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f ++#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L ++#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L ++#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L ++#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L ++#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L ++#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L ++#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L ++#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L ++#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L ++#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L ++#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L ++#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L ++#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L ++#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L ++#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L ++#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L ++//CP_INT_STATUS_RING2 ++#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb ++#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe ++#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 ++#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 ++#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 ++#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 ++#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 ++#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 ++#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 ++#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 ++#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 ++#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a ++#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b ++#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d ++#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e ++#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f ++#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L ++#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L ++#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L ++#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L ++#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L ++#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L ++#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L ++#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L ++#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L ++#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L ++#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L ++#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L ++#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L ++#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L ++#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L ++#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L ++//CP_PWR_CNTL ++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 ++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 ++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L ++#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L ++#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L ++//CP_MEM_SLP_CNTL ++#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 ++#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 ++#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 ++#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 ++#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 ++#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 ++#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 ++#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L ++#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L ++#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL ++#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L ++#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L ++#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L ++#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L ++//CP_ECC_FIRSTOCCURRENCE ++#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 ++#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 ++#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 ++#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa ++#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc ++#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 ++#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L ++#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L ++#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L ++#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L ++#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L ++#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L ++//CP_ECC_FIRSTOCCURRENCE_RING0 ++#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 ++#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL ++//CP_ECC_FIRSTOCCURRENCE_RING1 ++#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 ++#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL ++//CP_ECC_FIRSTOCCURRENCE_RING2 ++#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 ++#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL ++//CP_PQ_WPTR_POLL_CNTL ++#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 ++#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d ++#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e ++#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f ++#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL ++#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L ++#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L ++#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L ++//CP_PQ_WPTR_POLL_CNTL1 ++#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 ++#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL ++//CP_ME1_PIPE0_INT_CNTL ++#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME1_PIPE1_INT_CNTL ++#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME1_PIPE2_INT_CNTL ++#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME1_PIPE3_INT_CNTL ++#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME2_PIPE0_INT_CNTL ++#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME2_PIPE1_INT_CNTL ++#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME2_PIPE2_INT_CNTL ++#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME2_PIPE3_INT_CNTL ++#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CP_ME1_PIPE0_INT_STATUS ++#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME1_PIPE1_INT_STATUS ++#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME1_PIPE2_INT_STATUS ++#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME1_PIPE3_INT_STATUS ++#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME2_PIPE0_INT_STATUS ++#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME2_PIPE1_INT_STATUS ++#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME2_PIPE2_INT_STATUS ++#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME2_PIPE3_INT_STATUS ++#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_ME1_PIPE_PRIORITY_CNTS ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L ++#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L ++//CP_ME1_PIPE0_PRIORITY ++#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME1_PIPE1_PRIORITY ++#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME1_PIPE2_PRIORITY ++#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME1_PIPE3_PRIORITY ++#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME2_PIPE_PRIORITY_CNTS ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L ++#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L ++//CP_ME2_PIPE0_PRIORITY ++#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME2_PIPE1_PRIORITY ++#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME2_PIPE2_PRIORITY ++#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_ME2_PIPE3_PRIORITY ++#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 ++#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L ++//CP_CE_PRGRM_CNTR_START ++#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 ++#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL ++//CP_PFP_PRGRM_CNTR_START ++#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 ++#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL ++//CP_ME_PRGRM_CNTR_START ++#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 ++#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL ++//CP_MEC1_PRGRM_CNTR_START ++#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 ++#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL ++//CP_MEC2_PRGRM_CNTR_START ++#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 ++#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL ++//CP_CE_INTR_ROUTINE_START ++#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 ++#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL ++//CP_PFP_INTR_ROUTINE_START ++#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 ++#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL ++//CP_ME_INTR_ROUTINE_START ++#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 ++#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL ++//CP_MEC1_INTR_ROUTINE_START ++#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 ++#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL ++//CP_MEC2_INTR_ROUTINE_START ++#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 ++#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL ++//CP_CONTEXT_CNTL ++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 ++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 ++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 ++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 ++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L ++#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L ++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L ++#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L ++//CP_MAX_CONTEXT ++#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 ++#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L ++//CP_IQ_WAIT_TIME1 ++#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 ++#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 ++#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 ++#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 ++#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL ++#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L ++#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L ++#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L ++//CP_IQ_WAIT_TIME2 ++#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 ++#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 ++#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 ++#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 ++#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL ++#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L ++#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L ++#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L ++//CP_RB0_BASE_HI ++#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 ++#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL ++//CP_RB1_BASE_HI ++#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 ++#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL ++//CP_VMID_RESET ++#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 ++#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL ++//CPC_INT_CNTL ++#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc ++#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd ++#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe ++#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf ++#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 ++#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 ++#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 ++#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 ++#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a ++#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b ++#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d ++#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e ++#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f ++#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L ++#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L ++#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L ++#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L ++#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L ++#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L ++#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L ++#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L ++#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L ++#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L ++#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L ++#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L ++#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L ++//CPC_INT_STATUS ++#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc ++#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd ++#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe ++#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf ++#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 ++#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 ++#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 ++#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 ++#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a ++#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b ++#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d ++#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e ++#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f ++#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L ++#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L ++#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L ++#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L ++#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L ++#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L ++#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L ++#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L ++#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L ++#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L ++#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L ++#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L ++#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L ++//CP_VMID_PREEMPT ++#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 ++#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 ++#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL ++#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L ++//CPC_INT_CNTX_ID ++#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 ++#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL ++//CP_PQ_STATUS ++#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 ++#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 ++#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L ++#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L ++//CP_CPC_IC_BASE_LO ++#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc ++#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L ++//CP_CPC_IC_BASE_HI ++#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 ++#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL ++//CP_CPC_IC_BASE_CNTL ++#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 ++#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 ++#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL ++#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L ++//CP_CPC_IC_OP_CNTL ++#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 ++#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 ++#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 ++#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L ++#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L ++#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L ++//CP_MEC1_F32_INT_DIS ++#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 ++#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 ++#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 ++#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 ++#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 ++#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa ++#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb ++#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc ++#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe ++#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L ++#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L ++#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L ++#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L ++#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L ++#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L ++#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L ++#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L ++#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L ++//CP_MEC2_F32_INT_DIS ++#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 ++#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 ++#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 ++#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 ++#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 ++#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa ++#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb ++#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc ++#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe ++#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L ++#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L ++#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L ++#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L ++#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L ++#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L ++#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L ++#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L ++#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L ++//CP_VMID_STATUS ++#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 ++#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 ++#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL ++#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L ++ ++ ++// addressBlock: gc_cppdec2 ++//CP_RB_DOORBELL_CONTROL_SCH_0 ++#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CONTROL_SCH_1 ++#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CONTROL_SCH_2 ++#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CONTROL_SCH_3 ++#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CONTROL_SCH_4 ++#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CONTROL_SCH_5 ++#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CONTROL_SCH_6 ++#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CONTROL_SCH_7 ++#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e ++#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f ++#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L ++#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L ++//CP_RB_DOORBELL_CLEAR ++#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 ++#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 ++#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 ++#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa ++#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb ++#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc ++#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd ++#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L ++#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L ++#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L ++#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L ++#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L ++#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L ++#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L ++//CP_GFX_MQD_CONTROL ++#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 ++#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 ++#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 ++#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL ++#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L ++#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L ++//CP_GFX_MQD_BASE_ADDR ++#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 ++#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL ++//CP_GFX_MQD_BASE_ADDR_HI ++#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 ++#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL ++//CP_RB_STATUS ++#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 ++#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 ++#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L ++#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L ++//CPG_UTCL1_STATUS ++#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 ++#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 ++#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 ++#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L ++#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L ++#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L ++//CPC_UTCL1_STATUS ++#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 ++#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 ++#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 ++#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L ++#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L ++#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L ++//CPF_UTCL1_STATUS ++#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 ++#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 ++#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 ++#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L ++#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L ++#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L ++//CP_SD_CNTL ++#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 ++#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 ++#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 ++#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 ++#define CP_SD_CNTL__SPI_EN__SHIFT 0x4 ++#define CP_SD_CNTL__WD_EN__SHIFT 0x5 ++#define CP_SD_CNTL__IA_EN__SHIFT 0x6 ++#define CP_SD_CNTL__PA_EN__SHIFT 0x7 ++#define CP_SD_CNTL__RMI_EN__SHIFT 0x8 ++#define CP_SD_CNTL__EA_EN__SHIFT 0x9 ++#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L ++#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L ++#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L ++#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L ++#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L ++#define CP_SD_CNTL__WD_EN_MASK 0x00000020L ++#define CP_SD_CNTL__IA_EN_MASK 0x00000040L ++#define CP_SD_CNTL__PA_EN_MASK 0x00000080L ++#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L ++#define CP_SD_CNTL__EA_EN_MASK 0x00000200L ++//CP_SOFT_RESET_CNTL ++#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 ++#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 ++#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 ++#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 ++#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 ++#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 ++#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 ++#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L ++#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L ++#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L ++#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L ++#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L ++#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L ++#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L ++//CP_CPC_GFX_CNTL ++#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 ++#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 ++#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 ++#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 ++#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L ++#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L ++#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L ++#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L ++ ++ ++// addressBlock: gc_spipdec ++//SPI_ARB_PRIORITY ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 ++#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc ++#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe ++#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 ++#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L ++#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L ++#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L ++#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L ++#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L ++#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L ++//SPI_ARB_CYCLES_0 ++#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 ++#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 ++#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL ++#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L ++//SPI_ARB_CYCLES_1 ++#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 ++#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 ++#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL ++#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L ++//SPI_CDBG_SYS_GFX ++#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 ++#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 ++#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 ++#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 ++#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 ++#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 ++#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 ++#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x0001L ++#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x0002L ++#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x0004L ++#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x0008L ++#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x0010L ++#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x0020L ++#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x0040L ++//SPI_CDBG_SYS_HP3D ++#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 ++#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 ++#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 ++#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 ++#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 ++#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 ++#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x0001L ++#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x0002L ++#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x0004L ++#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x0008L ++#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x0010L ++#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x0020L ++//SPI_CDBG_SYS_CS0 ++#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 ++#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 ++#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 ++#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 ++#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL ++#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L ++#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L ++#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L ++//SPI_CDBG_SYS_CS1 ++#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 ++#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 ++#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 ++#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 ++#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0x000000FFL ++#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0x0000FF00L ++#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0x00FF0000L ++#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xFF000000L ++//SPI_WCL_PIPE_PERCENT_GFX ++#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 ++#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc ++#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 ++#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 ++#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL ++#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L ++#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L ++#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L ++#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L ++//SPI_WCL_PIPE_PERCENT_HP3D ++#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc ++#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 ++#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL ++#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L ++#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L ++//SPI_WCL_PIPE_PERCENT_CS0 ++#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL ++//SPI_WCL_PIPE_PERCENT_CS1 ++#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL ++//SPI_WCL_PIPE_PERCENT_CS2 ++#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL ++//SPI_WCL_PIPE_PERCENT_CS3 ++#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL ++//SPI_WCL_PIPE_PERCENT_CS4 ++#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL ++//SPI_WCL_PIPE_PERCENT_CS5 ++#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL ++//SPI_WCL_PIPE_PERCENT_CS6 ++#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL ++//SPI_WCL_PIPE_PERCENT_CS7 ++#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 ++#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL ++//SPI_GDBG_WAVE_CNTL ++#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 ++#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 ++#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L ++#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL ++//SPI_GDBG_TRAP_CONFIG ++#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 ++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 ++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 ++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 ++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 ++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 ++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf ++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 ++#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L ++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL ++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L ++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L ++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L ++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L ++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L ++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L ++//SPI_GDBG_TRAP_MASK ++#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 ++#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 ++#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL ++#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L ++//SPI_GDBG_WAVE_CNTL2 ++#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0 ++#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10 ++#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL ++#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L ++//SPI_GDBG_WAVE_CNTL3 ++#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 ++#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1 ++#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 ++#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 ++#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc ++#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd ++#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c ++#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L ++#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L ++#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L ++#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L ++#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L ++#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L ++#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L ++//SPI_GDBG_TRAP_DATA0 ++#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 ++#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL ++//SPI_GDBG_TRAP_DATA1 ++#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 ++#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL ++//SPI_COMPUTE_QUEUE_RESET ++#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 ++#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L ++//SPI_RESOURCE_RESERVE_CU_0 ++#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_1 ++#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_2 ++#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_3 ++#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_4 ++#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_5 ++#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_6 ++#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_7 ++#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_8 ++#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_9 ++#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_EN_CU_0 ++#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_1 ++#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_2 ++#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_3 ++#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_4 ++#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_5 ++#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_6 ++#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_7 ++#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_8 ++#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_9 ++#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_CU_10 ++#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_11 ++#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_EN_CU_10 ++#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_11 ++#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_CU_12 ++#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_13 ++#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_14 ++#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_CU_15 ++#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 ++#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 ++#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc ++#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf ++#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL ++#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L ++#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L ++#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L ++#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L ++//SPI_RESOURCE_RESERVE_EN_CU_12 ++#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_13 ++#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_14 ++#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_RESOURCE_RESERVE_EN_CU_15 ++#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 ++#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 ++#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 ++#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 ++#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L ++#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL ++#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L ++#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L ++//SPI_COMPUTE_WF_CTX_SAVE ++#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 ++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 ++#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 ++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e ++#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f ++#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L ++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L ++#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L ++#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L ++#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L ++//SPI_ARB_CNTL_0 ++#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 ++#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 ++#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 ++#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL ++#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L ++#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L ++ ++ ++// addressBlock: gc_cpphqddec ++//CP_HQD_GFX_CONTROL ++#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 ++#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 ++#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf ++#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL ++#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L ++#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L ++//CP_HQD_GFX_STATUS ++#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 ++#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL ++//CP_HPD_ROQ_OFFSETS ++#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 ++#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 ++#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 ++#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L ++#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L ++#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L ++//CP_HPD_STATUS0 ++#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 ++#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 ++#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 ++#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 ++#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 ++#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 ++#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 ++#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f ++#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL ++#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L ++#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L ++#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L ++#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L ++#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L ++#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L ++#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L ++//CP_HPD_UTCL1_CNTL ++#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 ++#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL ++//CP_HPD_UTCL1_ERROR ++#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 ++#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 ++#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 ++#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL ++#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L ++#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L ++//CP_HPD_UTCL1_ERROR_ADDR ++#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc ++#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L ++//CP_MQD_BASE_ADDR ++#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 ++#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL ++//CP_MQD_BASE_ADDR_HI ++#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 ++#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL ++//CP_HQD_ACTIVE ++#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 ++#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 ++#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L ++#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L ++//CP_HQD_VMID ++#define CP_HQD_VMID__VMID__SHIFT 0x0 ++#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 ++#define CP_HQD_VMID__VQID__SHIFT 0x10 ++#define CP_HQD_VMID__VMID_MASK 0x0000000FL ++#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L ++#define CP_HQD_VMID__VQID_MASK 0x03FF0000L ++//CP_HQD_PERSISTENT_STATE ++#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 ++#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 ++#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 ++#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 ++#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 ++#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 ++#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 ++#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a ++#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b ++#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c ++#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d ++#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e ++#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f ++#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L ++#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L ++#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L ++#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L ++#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L ++#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L ++#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L ++#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L ++#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L ++#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L ++#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L ++#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L ++#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L ++//CP_HQD_PIPE_PRIORITY ++#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 ++#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L ++//CP_HQD_QUEUE_PRIORITY ++#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 ++#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL ++//CP_HQD_QUANTUM ++#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 ++#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 ++#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 ++#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f ++#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L ++#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L ++#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L ++#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L ++//CP_HQD_PQ_BASE ++#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 ++#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL ++//CP_HQD_PQ_BASE_HI ++#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 ++#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL ++//CP_HQD_PQ_RPTR ++#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 ++#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL ++//CP_HQD_PQ_RPTR_REPORT_ADDR ++#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 ++#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL ++//CP_HQD_PQ_RPTR_REPORT_ADDR_HI ++#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 ++#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL ++//CP_HQD_PQ_WPTR_POLL_ADDR ++#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 ++#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L ++//CP_HQD_PQ_WPTR_POLL_ADDR_HI ++#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 ++#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL ++//CP_HQD_PQ_DOORBELL_CONTROL ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L ++#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L ++//CP_HQD_PQ_CONTROL ++#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 ++#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 ++#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 ++#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 ++#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe ++#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf ++#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 ++#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 ++#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 ++#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 ++#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 ++#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 ++#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b ++#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c ++#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d ++#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e ++#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f ++#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL ++#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L ++#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L ++#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L ++#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L ++#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L ++#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L ++#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L ++#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L ++#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L ++#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L ++#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L ++#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L ++#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L ++#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L ++#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L ++#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L ++//CP_HQD_IB_BASE_ADDR ++#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 ++#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL ++//CP_HQD_IB_BASE_ADDR_HI ++#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 ++#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL ++//CP_HQD_IB_RPTR ++#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 ++#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL ++//CP_HQD_IB_CONTROL ++#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 ++#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 ++#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 ++#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 ++#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f ++#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL ++#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L ++#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L ++#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L ++#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L ++//CP_HQD_IQ_TIMER ++#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 ++#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 ++#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb ++#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc ++#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe ++#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 ++#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 ++#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 ++#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 ++#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 ++#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c ++#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d ++#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e ++#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f ++#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL ++#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L ++#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L ++#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L ++#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L ++#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L ++#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L ++#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L ++#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L ++#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L ++#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L ++#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L ++#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L ++#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L ++//CP_HQD_IQ_RPTR ++#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 ++#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL ++//CP_HQD_DEQUEUE_REQUEST ++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 ++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 ++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 ++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 ++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa ++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L ++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L ++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L ++#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L ++#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L ++//CP_HQD_DMA_OFFLOAD ++#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 ++#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L ++//CP_HQD_OFFLOAD ++#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 ++#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 ++#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 ++#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 ++#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 ++#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 ++#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L ++#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L ++#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L ++#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L ++#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L ++#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L ++//CP_HQD_SEMA_CMD ++#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 ++#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 ++#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L ++#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L ++//CP_HQD_MSG_TYPE ++#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 ++#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 ++#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L ++#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L ++//CP_HQD_ATOMIC0_PREOP_LO ++#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 ++#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_HQD_ATOMIC0_PREOP_HI ++#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 ++#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_HQD_ATOMIC1_PREOP_LO ++#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 ++#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_HQD_ATOMIC1_PREOP_HI ++#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 ++#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_HQD_HQ_SCHEDULER0 ++#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 ++#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL ++//CP_HQD_HQ_STATUS0 ++#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 ++#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 ++#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 ++#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 ++#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 ++#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 ++#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa ++#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e ++#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f ++#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L ++#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL ++#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L ++#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L ++#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L ++#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L ++#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L ++#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L ++#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L ++//CP_HQD_HQ_CONTROL0 ++#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 ++#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL ++//CP_HQD_HQ_SCHEDULER1 ++#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 ++#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL ++//CP_MQD_CONTROL ++#define CP_MQD_CONTROL__VMID__SHIFT 0x0 ++#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 ++#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc ++#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd ++#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 ++#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 ++#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL ++#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L ++#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L ++#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L ++#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L ++#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L ++//CP_HQD_HQ_STATUS1 ++#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 ++#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL ++//CP_HQD_HQ_CONTROL1 ++#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 ++#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL ++//CP_HQD_EOP_BASE_ADDR ++#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 ++#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL ++//CP_HQD_EOP_BASE_ADDR_HI ++#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 ++#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL ++//CP_HQD_EOP_CONTROL ++#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 ++#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 ++#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc ++#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd ++#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe ++#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 ++#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 ++#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 ++#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 ++#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d ++#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f ++#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL ++#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L ++#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L ++#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L ++#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L ++#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L ++#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L ++#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L ++#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L ++#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L ++#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L ++//CP_HQD_EOP_RPTR ++#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 ++#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c ++#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d ++#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e ++#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f ++#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL ++#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L ++#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L ++#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L ++#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L ++//CP_HQD_EOP_WPTR ++#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 ++#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf ++#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 ++#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL ++#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L ++#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L ++//CP_HQD_EOP_EVENTS ++#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 ++#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 ++#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL ++#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L ++//CP_HQD_CTX_SAVE_BASE_ADDR_LO ++#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc ++#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L ++//CP_HQD_CTX_SAVE_BASE_ADDR_HI ++#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_HQD_CTX_SAVE_CONTROL ++#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 ++#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 ++#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L ++#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L ++//CP_HQD_CNTL_STACK_OFFSET ++#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 ++#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL ++//CP_HQD_CNTL_STACK_SIZE ++#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc ++#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L ++//CP_HQD_WG_STATE_OFFSET ++#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 ++#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL ++//CP_HQD_CTX_SAVE_SIZE ++#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc ++#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L ++//CP_HQD_GDS_RESOURCE_STATE ++#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 ++#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 ++#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 ++#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc ++#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L ++#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L ++#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L ++#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L ++//CP_HQD_ERROR ++#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 ++#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 ++#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 ++#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 ++#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa ++#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb ++#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc ++#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd ++#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe ++#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf ++#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 ++#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 ++#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 ++#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 ++#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L ++#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L ++#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L ++#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L ++#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L ++#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L ++#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L ++#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L ++#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L ++#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L ++#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L ++#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L ++#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L ++#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L ++//CP_HQD_EOP_WPTR_MEM ++#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 ++#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL ++//CP_HQD_AQL_CONTROL ++#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 ++#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf ++#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 ++#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f ++#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL ++#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L ++#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L ++#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L ++//CP_HQD_PQ_WPTR_LO ++#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 ++#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL ++//CP_HQD_PQ_WPTR_HI ++#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 ++#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gc_didtdec ++//DIDT_IND_INDEX ++#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 ++#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL ++//DIDT_IND_DATA ++#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 ++#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL ++//DIDT_INDEX_AUTO_INCR_EN ++#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0 ++#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L ++ ++ ++// addressBlock: gc_gccacdec ++//GC_CAC_CTRL_1 ++#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 ++#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 ++#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL ++#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L ++//GC_CAC_CTRL_2 ++#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 ++#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 ++#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2 ++#define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3 ++#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L ++#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L ++#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L ++#define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L ++//GC_CAC_INDEX_AUTO_INCR_EN ++#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x0 ++#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000001L ++//GC_CAC_AGGR_LOWER ++#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 ++#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_AGGR_UPPER ++#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 ++#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL ++//PCC_PERF_COUNTER ++#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 ++#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL ++//GC_CAC_SOFT_CTRL ++#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 ++#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L ++//GC_DIDT_CTRL0 ++#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 ++#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 ++#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 ++#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 ++#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 ++#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L ++#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L ++#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L ++#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L ++#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L ++//GC_DIDT_CTRL1 ++#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 ++#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 ++#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL ++#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L ++//GC_DIDT_CTRL2 ++#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 ++#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 ++#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b ++#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL ++#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L ++#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L ++//GC_DIDT_WEIGHT ++#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 ++#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 ++#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 ++#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 ++#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL ++#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L ++#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L ++#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L ++//GC_EDC_CTRL ++#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 ++#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 ++#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 ++#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 ++#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 ++#define GC_EDC_CTRL__GC_EDC_ONLY_MODE__SHIFT 0xb ++#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xc ++#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x10 ++#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0x14 ++#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L ++#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L ++#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L ++#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L ++#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L ++#define GC_EDC_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000800L ++#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x0000F000L ++#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x000F0000L ++#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL_MASK 0x3FF00000L ++//GC_EDC_THRESHOLD ++#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 ++#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL ++//GC_DIDT_DROOP_CTRL ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0 ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1 ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf ++#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13 ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L ++#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L ++#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L ++//GC_DIDT_DROOP_CTRL1 ++#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_LEVEL_RELEASE_EN__SHIFT 0x0 ++#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_DELTA_THRESHOLD__SHIFT 0x1 ++#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_LEVEL_RELEASE_EN_MASK 0x00000001L ++#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_DELTA_THRESHOLD_MASK 0x00007FFEL ++//GC_EDC_DROOP_CTRL ++#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0 ++#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1 ++#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf ++#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14 ++#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15 ++#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L ++#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL ++#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L ++#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L ++#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L ++//GC_THROTTLE_CTRL ++#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 ++#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x2 ++#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x3 ++#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x7 ++#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0x9 ++#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL__SHIFT 0xa ++#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN__SHIFT 0x14 ++#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX__SHIFT 0x19 ++#define GC_THROTTLE_CTRL__INST_THROT_INCR__SHIFT 0x1e ++#define GC_THROTTLE_CTRL__INST_THROT_DECR__SHIFT 0x1f ++#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L ++#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000004L ++#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000008L ++#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000080L ++#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000200L ++#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL_MASK 0x000FFC00L ++#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN_MASK 0x01F00000L ++#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX_MASK 0x3E000000L ++#define GC_THROTTLE_CTRL__INST_THROT_INCR_MASK 0x40000000L ++#define GC_THROTTLE_CTRL__INST_THROT_DECR_MASK 0x80000000L ++//GC_CAC_IND_INDEX ++#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 ++#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL ++//GC_CAC_IND_DATA ++#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 ++#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL ++//SE_CAC_IND_INDEX ++#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 ++#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL ++//SE_CAC_IND_DATA ++#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 ++#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gc_tcpdec ++//TCP_WATCH0_ADDR_H ++#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 ++#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL ++//TCP_WATCH0_ADDR_L ++#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 ++#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L ++//TCP_WATCH0_CNTL ++#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 ++#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 ++#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c ++#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d ++#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f ++#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL ++#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L ++#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L ++#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L ++#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L ++//TCP_WATCH1_ADDR_H ++#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 ++#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL ++//TCP_WATCH1_ADDR_L ++#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 ++#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L ++//TCP_WATCH1_CNTL ++#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 ++#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 ++#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c ++#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d ++#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f ++#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL ++#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L ++#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L ++#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L ++#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L ++//TCP_WATCH2_ADDR_H ++#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 ++#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL ++//TCP_WATCH2_ADDR_L ++#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 ++#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L ++//TCP_WATCH2_CNTL ++#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 ++#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 ++#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c ++#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d ++#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f ++#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL ++#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L ++#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L ++#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L ++#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L ++//TCP_WATCH3_ADDR_H ++#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 ++#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL ++//TCP_WATCH3_ADDR_L ++#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 ++#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L ++//TCP_WATCH3_CNTL ++#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 ++#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 ++#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c ++#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d ++#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f ++#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL ++#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L ++#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L ++#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L ++#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L ++//TCP_GATCL1_CNTL ++#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 ++#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a ++#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b ++#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c ++#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e ++#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L ++#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L ++#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L ++#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L ++#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L ++//TCP_GATCL1_DSM_CNTL ++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 ++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 ++#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 ++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L ++#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L ++#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L ++//TCP_CNTL2 ++#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 ++#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT 0x8 ++#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9 ++#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL ++#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK 0x00000100L ++#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L ++//TCP_UTCL1_CNTL1 ++#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 ++#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 ++#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 ++#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 ++#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 ++#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 ++#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 ++#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 ++#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 ++#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 ++#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a ++#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c ++#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e ++#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L ++#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L ++#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L ++#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L ++#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L ++#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L ++#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L ++#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L ++#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L ++#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L ++#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L ++#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L ++#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L ++//TCP_UTCL1_CNTL2 ++#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 ++#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 ++#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa ++#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc ++#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe ++#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf ++#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a ++#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL ++#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L ++#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L ++#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L ++#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L ++#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L ++#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L ++//TCP_UTCL1_STATUS ++#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++//TCP_PERFCOUNTER_FILTER ++#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 ++#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 ++#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 ++#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 ++#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb ++#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf ++#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 ++#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 ++#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 ++#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a ++#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b ++#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c ++#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L ++#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L ++#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL ++#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L ++#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L ++#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L ++#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L ++#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L ++#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L ++#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L ++#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L ++#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L ++//TCP_PERFCOUNTER_FILTER_EN ++#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 ++#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 ++#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 ++#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 ++#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 ++#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 ++#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 ++#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 ++#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 ++#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 ++#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa ++#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb ++#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L ++#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L ++#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L ++#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L ++#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L ++#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L ++#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L ++#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L ++#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L ++#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L ++#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L ++#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L ++ ++ ++// addressBlock: gc_gdspdec ++//GDS_VMID0_BASE ++#define GDS_VMID0_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID0_SIZE ++#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID1_BASE ++#define GDS_VMID1_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID1_SIZE ++#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID2_BASE ++#define GDS_VMID2_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID2_SIZE ++#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID3_BASE ++#define GDS_VMID3_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID3_SIZE ++#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID4_BASE ++#define GDS_VMID4_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID4_SIZE ++#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID5_BASE ++#define GDS_VMID5_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID5_SIZE ++#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID6_BASE ++#define GDS_VMID6_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID6_SIZE ++#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID7_BASE ++#define GDS_VMID7_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID7_SIZE ++#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID8_BASE ++#define GDS_VMID8_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID8_SIZE ++#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID9_BASE ++#define GDS_VMID9_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID9_SIZE ++#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID10_BASE ++#define GDS_VMID10_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID10_SIZE ++#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID11_BASE ++#define GDS_VMID11_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID11_SIZE ++#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID12_BASE ++#define GDS_VMID12_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID12_SIZE ++#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID13_BASE ++#define GDS_VMID13_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID13_SIZE ++#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID14_BASE ++#define GDS_VMID14_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID14_SIZE ++#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_VMID15_BASE ++#define GDS_VMID15_BASE__BASE__SHIFT 0x0 ++#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL ++//GDS_VMID15_SIZE ++#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 ++#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL ++//GDS_GWS_VMID0 ++#define GDS_GWS_VMID0__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID1 ++#define GDS_GWS_VMID1__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID2 ++#define GDS_GWS_VMID2__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID3 ++#define GDS_GWS_VMID3__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID4 ++#define GDS_GWS_VMID4__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID5 ++#define GDS_GWS_VMID5__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID6 ++#define GDS_GWS_VMID6__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID7 ++#define GDS_GWS_VMID7__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID8 ++#define GDS_GWS_VMID8__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID9 ++#define GDS_GWS_VMID9__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID10 ++#define GDS_GWS_VMID10__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID11 ++#define GDS_GWS_VMID11__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID12 ++#define GDS_GWS_VMID12__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID13 ++#define GDS_GWS_VMID13__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID14 ++#define GDS_GWS_VMID14__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L ++//GDS_GWS_VMID15 ++#define GDS_GWS_VMID15__BASE__SHIFT 0x0 ++#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 ++#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL ++#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L ++//GDS_OA_VMID0 ++#define GDS_OA_VMID0__MASK__SHIFT 0x0 ++#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID1 ++#define GDS_OA_VMID1__MASK__SHIFT 0x0 ++#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID2 ++#define GDS_OA_VMID2__MASK__SHIFT 0x0 ++#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID3 ++#define GDS_OA_VMID3__MASK__SHIFT 0x0 ++#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID4 ++#define GDS_OA_VMID4__MASK__SHIFT 0x0 ++#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID5 ++#define GDS_OA_VMID5__MASK__SHIFT 0x0 ++#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID6 ++#define GDS_OA_VMID6__MASK__SHIFT 0x0 ++#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID7 ++#define GDS_OA_VMID7__MASK__SHIFT 0x0 ++#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID8 ++#define GDS_OA_VMID8__MASK__SHIFT 0x0 ++#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID9 ++#define GDS_OA_VMID9__MASK__SHIFT 0x0 ++#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID10 ++#define GDS_OA_VMID10__MASK__SHIFT 0x0 ++#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID11 ++#define GDS_OA_VMID11__MASK__SHIFT 0x0 ++#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID12 ++#define GDS_OA_VMID12__MASK__SHIFT 0x0 ++#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID13 ++#define GDS_OA_VMID13__MASK__SHIFT 0x0 ++#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID14 ++#define GDS_OA_VMID14__MASK__SHIFT 0x0 ++#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_VMID15 ++#define GDS_OA_VMID15__MASK__SHIFT 0x0 ++#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 ++#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL ++#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L ++//GDS_GWS_RESET0 ++#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 ++#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 ++#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 ++#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 ++#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 ++#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 ++#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 ++#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 ++#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 ++#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 ++#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa ++#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb ++#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc ++#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd ++#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe ++#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf ++#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 ++#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 ++#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 ++#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 ++#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 ++#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 ++#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 ++#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 ++#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 ++#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 ++#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a ++#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b ++#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c ++#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d ++#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e ++#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f ++#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L ++#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L ++#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L ++#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L ++#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L ++#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L ++#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L ++#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L ++#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L ++#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L ++#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L ++#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L ++#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L ++#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L ++#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L ++#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L ++#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L ++#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L ++#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L ++#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L ++#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L ++#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L ++#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L ++#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L ++#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L ++#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L ++#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L ++#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L ++#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L ++#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L ++#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L ++#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L ++//GDS_GWS_RESET1 ++#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 ++#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 ++#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 ++#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 ++#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 ++#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 ++#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 ++#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 ++#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 ++#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 ++#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa ++#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb ++#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc ++#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd ++#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe ++#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf ++#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 ++#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 ++#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 ++#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 ++#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 ++#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 ++#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 ++#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 ++#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 ++#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 ++#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a ++#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b ++#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c ++#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d ++#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e ++#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f ++#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L ++#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L ++#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L ++#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L ++#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L ++#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L ++#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L ++#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L ++#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L ++#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L ++#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L ++#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L ++#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L ++#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L ++#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L ++#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L ++#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L ++#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L ++#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L ++#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L ++#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L ++#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L ++#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L ++#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L ++#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L ++#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L ++#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L ++#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L ++#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L ++#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L ++#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L ++#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L ++//GDS_GWS_RESOURCE_RESET ++#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 ++#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 ++#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L ++#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L ++//GDS_COMPUTE_MAX_WAVE_ID ++#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 ++#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL ++//GDS_OA_RESET_MASK ++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 ++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 ++#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 ++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 ++#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 ++#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 ++#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 ++#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 ++#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 ++#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 ++#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa ++#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb ++#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc ++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L ++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L ++#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L ++#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L ++#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L ++#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L ++#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L ++#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L ++#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L ++#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L ++#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L ++#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L ++#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L ++//GDS_OA_RESET ++#define GDS_OA_RESET__RESET__SHIFT 0x0 ++#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 ++#define GDS_OA_RESET__RESET_MASK 0x00000001L ++#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L ++//GDS_ENHANCE ++#define GDS_ENHANCE__MISC__SHIFT 0x0 ++#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 ++#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 ++#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 ++#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 ++#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 ++#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 ++#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT 0x16 ++#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT 0x17 ++#define GDS_ENHANCE__UNUSED__SHIFT 0x18 ++#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL ++#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L ++#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L ++#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L ++#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L ++#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L ++#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L ++#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L ++#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK 0x00800000L ++#define GDS_ENHANCE__UNUSED_MASK 0xFF000000L ++//GDS_OA_CGPG_RESTORE ++#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 ++#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 ++#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc ++#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 ++#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 ++#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL ++#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L ++#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L ++#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L ++#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L ++//GDS_CS_CTXSW_STATUS ++#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 ++#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 ++#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 ++#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L ++#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L ++#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL ++//GDS_CS_CTXSW_CNT0 ++#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_CS_CTXSW_CNT1 ++#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_CS_CTXSW_CNT2 ++#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_CS_CTXSW_CNT3 ++#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_GFX_CTXSW_STATUS ++#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 ++#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 ++#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 ++#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L ++#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L ++#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL ++//GDS_VS_CTXSW_CNT0 ++#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_VS_CTXSW_CNT1 ++#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_VS_CTXSW_CNT2 ++#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_VS_CTXSW_CNT3 ++#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS0_CTXSW_CNT0 ++#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS0_CTXSW_CNT1 ++#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS0_CTXSW_CNT2 ++#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS0_CTXSW_CNT3 ++#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS1_CTXSW_CNT0 ++#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS1_CTXSW_CNT1 ++#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS1_CTXSW_CNT2 ++#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS1_CTXSW_CNT3 ++#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS2_CTXSW_CNT0 ++#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS2_CTXSW_CNT1 ++#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS2_CTXSW_CNT2 ++#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS2_CTXSW_CNT3 ++#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS3_CTXSW_CNT0 ++#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS3_CTXSW_CNT1 ++#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS3_CTXSW_CNT2 ++#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS3_CTXSW_CNT3 ++#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS4_CTXSW_CNT0 ++#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS4_CTXSW_CNT1 ++#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS4_CTXSW_CNT2 ++#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS4_CTXSW_CNT3 ++#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS5_CTXSW_CNT0 ++#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS5_CTXSW_CNT1 ++#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS5_CTXSW_CNT2 ++#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS5_CTXSW_CNT3 ++#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS6_CTXSW_CNT0 ++#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS6_CTXSW_CNT1 ++#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS6_CTXSW_CNT2 ++#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS6_CTXSW_CNT3 ++#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_PS7_CTXSW_CNT0 ++#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_PS7_CTXSW_CNT1 ++#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_PS7_CTXSW_CNT2 ++#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_PS7_CTXSW_CNT3 ++#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++//GDS_GS_CTXSW_CNT0 ++#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 ++#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 ++#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL ++#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L ++//GDS_GS_CTXSW_CNT1 ++#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 ++#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 ++#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL ++#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L ++//GDS_GS_CTXSW_CNT2 ++#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 ++#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 ++#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL ++#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L ++//GDS_GS_CTXSW_CNT3 ++#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 ++#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 ++#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL ++#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L ++ ++ ++// addressBlock: gc_rasdec ++//RAS_SIGNATURE_CONTROL ++#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 ++#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L ++//RAS_SIGNATURE_MASK ++#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 ++#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL ++//RAS_SX_SIGNATURE0 ++#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SX_SIGNATURE1 ++#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 ++#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SX_SIGNATURE2 ++#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 ++#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SX_SIGNATURE3 ++#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 ++#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_DB_SIGNATURE0 ++#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_PA_SIGNATURE0 ++#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_VGT_SIGNATURE0 ++#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SQ_SIGNATURE0 ++#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE0 ++#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE1 ++#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE2 ++#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE3 ++#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE4 ++#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE5 ++#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE6 ++#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SC_SIGNATURE7 ++#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 ++#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_IA_SIGNATURE0 ++#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_IA_SIGNATURE1 ++#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 ++#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SPI_SIGNATURE0 ++#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_SPI_SIGNATURE1 ++#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 ++#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_TA_SIGNATURE0 ++#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_TD_SIGNATURE0 ++#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_CB_SIGNATURE0 ++#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_BCI_SIGNATURE0 ++#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 ++#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_BCI_SIGNATURE1 ++#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 ++#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL ++//RAS_TA_SIGNATURE1 ++#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 ++#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gc_gfxdec0 ++//DB_RENDER_CONTROL ++#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 ++#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 ++#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 ++#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 ++#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 ++#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 ++#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 ++#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 ++#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 ++#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc ++#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L ++#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L ++#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L ++#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L ++#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L ++#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L ++#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L ++#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L ++#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L ++#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L ++//DB_COUNT_CONTROL ++#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 ++#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 ++#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 ++#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 ++#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc ++#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 ++#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 ++#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 ++#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c ++#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L ++#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L ++#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L ++#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L ++#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L ++#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L ++#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L ++#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L ++#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L ++//DB_DEPTH_VIEW ++#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 ++#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd ++#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 ++#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 ++#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a ++#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL ++#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L ++#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L ++#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L ++//DB_RENDER_OVERRIDE ++#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 ++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 ++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 ++#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 ++#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 ++#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 ++#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 ++#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa ++#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb ++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc ++#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd ++#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf ++#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 ++#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 ++#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 ++#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 ++#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 ++#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a ++#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b ++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c ++#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d ++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e ++#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f ++#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L ++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL ++#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L ++#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L ++#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L ++#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L ++#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L ++#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L ++#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L ++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L ++#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L ++#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L ++#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L ++#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L ++#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L ++#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L ++#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L ++#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L ++#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L ++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L ++#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L ++#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L ++#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L ++//DB_RENDER_OVERRIDE2 ++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 ++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 ++#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 ++#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 ++#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 ++#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 ++#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 ++#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa ++#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb ++#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc ++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf ++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 ++#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 ++#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 ++#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 ++#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 ++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L ++#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL ++#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L ++#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L ++#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L ++#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L ++#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L ++#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L ++#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L ++#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L ++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L ++#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L ++#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L ++#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L ++#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L ++#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L ++//DB_HTILE_DATA_BASE ++#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 ++#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//DB_HTILE_DATA_BASE_HI ++#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 ++#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL ++//DB_DEPTH_SIZE ++#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 ++#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 ++#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL ++#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L ++//DB_DEPTH_BOUNDS_MIN ++#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 ++#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL ++//DB_DEPTH_BOUNDS_MAX ++#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 ++#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL ++//DB_STENCIL_CLEAR ++#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 ++#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL ++//DB_DEPTH_CLEAR ++#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 ++#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL ++//PA_SC_SCREEN_SCISSOR_TL ++#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 ++#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL ++#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L ++//PA_SC_SCREEN_SCISSOR_BR ++#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 ++#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL ++#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L ++//DB_Z_INFO ++#define DB_Z_INFO__FORMAT__SHIFT 0x0 ++#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 ++#define DB_Z_INFO__SW_MODE__SHIFT 0x4 ++#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc ++#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd ++#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf ++#define DB_Z_INFO__MAXMIP__SHIFT 0x10 ++#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 ++#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b ++#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c ++#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d ++#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e ++#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f ++#define DB_Z_INFO__FORMAT_MASK 0x00000003L ++#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL ++#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L ++#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L ++#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L ++#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L ++#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L ++#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L ++#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L ++#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L ++#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L ++#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L ++#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L ++//DB_STENCIL_INFO ++#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 ++#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 ++#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc ++#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd ++#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf ++#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b ++#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d ++#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e ++#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L ++#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L ++#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L ++#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L ++#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L ++#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L ++#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L ++#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L ++//DB_Z_READ_BASE ++#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 ++#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//DB_Z_READ_BASE_HI ++#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 ++#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL ++//DB_STENCIL_READ_BASE ++#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 ++#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//DB_STENCIL_READ_BASE_HI ++#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 ++#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL ++//DB_Z_WRITE_BASE ++#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 ++#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//DB_Z_WRITE_BASE_HI ++#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 ++#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL ++//DB_STENCIL_WRITE_BASE ++#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 ++#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//DB_STENCIL_WRITE_BASE_HI ++#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 ++#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL ++//DB_DFSM_CONTROL ++#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 ++#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 ++#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 ++#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L ++#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L ++#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L ++//DB_Z_INFO2 ++#define DB_Z_INFO2__EPITCH__SHIFT 0x0 ++#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL ++//DB_STENCIL_INFO2 ++#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 ++#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL ++//TA_BC_BASE_ADDR ++#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 ++#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL ++//TA_BC_BASE_ADDR_HI ++#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 ++#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL ++//COHER_DEST_BASE_HI_0 ++#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL ++//COHER_DEST_BASE_HI_1 ++#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL ++//COHER_DEST_BASE_HI_2 ++#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL ++//COHER_DEST_BASE_HI_3 ++#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL ++//COHER_DEST_BASE_2 ++#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL ++//COHER_DEST_BASE_3 ++#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL ++//PA_SC_WINDOW_OFFSET ++#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 ++#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 ++#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL ++#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L ++//PA_SC_WINDOW_SCISSOR_TL ++#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 ++#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_WINDOW_SCISSOR_BR ++#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 ++#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_RULE ++#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 ++#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL ++//PA_SC_CLIPRECT_0_TL ++#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_0_BR ++#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_1_TL ++#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_1_BR ++#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_2_TL ++#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_2_BR ++#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_3_TL ++#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L ++//PA_SC_CLIPRECT_3_BR ++#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 ++#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_EDGERULE ++#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 ++#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 ++#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 ++#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc ++#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 ++#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 ++#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c ++#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL ++#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L ++#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L ++#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L ++#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L ++#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L ++#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L ++//PA_SU_HARDWARE_SCREEN_OFFSET ++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 ++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 ++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL ++#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L ++//CB_TARGET_MASK ++#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 ++#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 ++#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 ++#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc ++#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 ++#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 ++#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 ++#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c ++#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL ++#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L ++#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L ++#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L ++#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L ++#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L ++#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L ++#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L ++//CB_SHADER_MASK ++#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 ++#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 ++#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 ++#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc ++#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 ++#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 ++#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 ++#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c ++#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL ++#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L ++#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L ++#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L ++#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L ++#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L ++#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L ++#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L ++//PA_SC_GENERIC_SCISSOR_TL ++#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 ++#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_GENERIC_SCISSOR_BR ++#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 ++#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L ++//COHER_DEST_BASE_0 ++#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL ++//COHER_DEST_BASE_1 ++#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 ++#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_SCISSOR_0_TL ++#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_0_BR ++#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_1_TL ++#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_1_BR ++#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_2_TL ++#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_2_BR ++#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_3_TL ++#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_3_BR ++#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_4_TL ++#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_4_BR ++#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_5_TL ++#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_5_BR ++#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_6_TL ++#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_6_BR ++#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_7_TL ++#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_7_BR ++#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_8_TL ++#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_8_BR ++#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_9_TL ++#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_9_BR ++#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_10_TL ++#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_10_BR ++#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_11_TL ++#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_11_BR ++#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_12_TL ++#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_12_BR ++#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_13_TL ++#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_13_BR ++#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_14_TL ++#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_14_BR ++#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_SCISSOR_15_TL ++#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f ++#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L ++#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L ++//PA_SC_VPORT_SCISSOR_15_BR ++#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 ++#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 ++#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL ++#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L ++//PA_SC_VPORT_ZMIN_0 ++#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_0 ++#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_1 ++#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_1 ++#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_2 ++#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_2 ++#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_3 ++#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_3 ++#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_4 ++#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_4 ++#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_5 ++#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_5 ++#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_6 ++#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_6 ++#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_7 ++#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_7 ++#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_8 ++#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_8 ++#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_9 ++#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_9 ++#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_10 ++#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_10 ++#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_11 ++#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_11 ++#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_12 ++#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_12 ++#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_13 ++#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_13 ++#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_14 ++#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_14 ++#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMIN_15 ++#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 ++#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL ++//PA_SC_VPORT_ZMAX_15 ++#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 ++#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL ++//PA_SC_RASTER_CONFIG ++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 ++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 ++#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 ++#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 ++#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 ++#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 ++#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa ++#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc ++#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe ++#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 ++#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 ++#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 ++#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 ++#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a ++#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d ++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L ++#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL ++#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L ++#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L ++#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L ++#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L ++#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L ++#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L ++#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L ++#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L ++#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L ++#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L ++#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L ++#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L ++#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L ++//PA_SC_RASTER_CONFIG_1 ++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 ++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 ++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 ++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L ++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL ++#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L ++//PA_SC_SCREEN_EXTENT_CONTROL ++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 ++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 ++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L ++#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL ++//PA_SC_TILE_STEERING_OVERRIDE ++#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 ++#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 ++#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 ++#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L ++#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L ++#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L ++//CP_PERFMON_CNTX_CNTL ++#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f ++#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L ++//CP_PIPEID ++#define CP_PIPEID__PIPE_ID__SHIFT 0x0 ++#define CP_PIPEID__PIPE_ID_MASK 0x00000003L ++//CP_RINGID ++#define CP_RINGID__RINGID__SHIFT 0x0 ++#define CP_RINGID__RINGID_MASK 0x00000003L ++//CP_VMID ++#define CP_VMID__VMID__SHIFT 0x0 ++#define CP_VMID__VMID_MASK 0x0000000FL ++//PA_SC_RIGHT_VERT_GRID ++#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 ++#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 ++#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 ++#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 ++#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL ++#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L ++#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L ++#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L ++//PA_SC_LEFT_VERT_GRID ++#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 ++#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 ++#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 ++#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 ++#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL ++#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L ++#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L ++#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L ++//PA_SC_HORIZ_GRID ++#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 ++#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 ++#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 ++#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 ++#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL ++#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L ++#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L ++#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L ++//VGT_MULTI_PRIM_IB_RESET_INDX ++#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 ++#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL ++//CB_BLEND_RED ++#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 ++#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL ++//CB_BLEND_GREEN ++#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 ++#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL ++//CB_BLEND_BLUE ++#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 ++#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL ++//CB_BLEND_ALPHA ++#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 ++#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL ++//CB_DCC_CONTROL ++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 ++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 ++#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 ++#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 ++#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa ++#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc ++#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd ++#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe ++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L ++#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL ++#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L ++#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L ++#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L ++#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L ++#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L ++#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L ++//DB_STENCIL_CONTROL ++#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 ++#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 ++#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 ++#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc ++#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 ++#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 ++#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL ++#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L ++#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L ++#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L ++#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L ++#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L ++//DB_STENCILREFMASK ++#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 ++#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 ++#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 ++#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 ++#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL ++#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L ++#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L ++#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L ++//DB_STENCILREFMASK_BF ++#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 ++#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 ++#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 ++#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 ++#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL ++#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L ++#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L ++#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L ++//PA_CL_VPORT_XSCALE ++#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET ++#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE ++#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET ++#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE ++#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET ++#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_1 ++#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_1 ++#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_1 ++#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_1 ++#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_1 ++#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_1 ++#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_2 ++#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_2 ++#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_2 ++#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_2 ++#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_2 ++#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_2 ++#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_3 ++#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_3 ++#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_3 ++#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_3 ++#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_3 ++#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_3 ++#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_4 ++#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_4 ++#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_4 ++#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_4 ++#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_4 ++#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_4 ++#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_5 ++#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_5 ++#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_5 ++#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_5 ++#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_5 ++#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_5 ++#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_6 ++#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_6 ++#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_6 ++#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_6 ++#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_6 ++#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_6 ++#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_7 ++#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_7 ++#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_7 ++#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_7 ++#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_7 ++#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_7 ++#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_8 ++#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_8 ++#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_8 ++#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_8 ++#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_8 ++#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_8 ++#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_9 ++#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_9 ++#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_9 ++#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_9 ++#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_9 ++#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_9 ++#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_10 ++#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_10 ++#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_10 ++#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_10 ++#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_10 ++#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_10 ++#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_11 ++#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_11 ++#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_11 ++#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_11 ++#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_11 ++#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_11 ++#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_12 ++#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_12 ++#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_12 ++#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_12 ++#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_12 ++#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_12 ++#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_13 ++#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_13 ++#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_13 ++#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_13 ++#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_13 ++#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_13 ++#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_14 ++#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_14 ++#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_14 ++#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_14 ++#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_14 ++#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_14 ++#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XSCALE_15 ++#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_XOFFSET_15 ++#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YSCALE_15 ++#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_YOFFSET_15 ++#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZSCALE_15 ++#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 ++#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL ++//PA_CL_VPORT_ZOFFSET_15 ++#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 ++#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL ++//PA_CL_UCP_0_X ++#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_0_Y ++#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_0_Z ++#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_0_W ++#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_1_X ++#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_1_Y ++#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_1_Z ++#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_1_W ++#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_2_X ++#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_2_Y ++#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_2_Z ++#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_2_W ++#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_3_X ++#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_3_Y ++#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_3_Z ++#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_3_W ++#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_4_X ++#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_4_Y ++#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_4_Z ++#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_4_W ++#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_5_X ++#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_5_Y ++#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_5_Z ++#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_UCP_5_W ++#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_PROG_NEAR_CLIP_Z ++#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL ++//SPI_PS_INPUT_CNTL_0 ++#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_1 ++#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_2 ++#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_3 ++#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_4 ++#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_5 ++#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_6 ++#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_7 ++#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_8 ++#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_9 ++#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_10 ++#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_11 ++#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_12 ++#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_13 ++#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_14 ++#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_15 ++#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_16 ++#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_17 ++#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_18 ++#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_19 ++#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd ++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 ++#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 ++#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L ++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L ++#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L ++#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_20 ++#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_21 ++#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_22 ++#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_23 ++#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_24 ++#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_25 ++#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_26 ++#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_27 ++#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_28 ++#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_29 ++#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_30 ++#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L ++//SPI_PS_INPUT_CNTL_31 ++#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 ++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 ++#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa ++#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 ++#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 ++#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 ++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 ++#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 ++#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 ++#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL ++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L ++#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L ++#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L ++#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L ++#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L ++#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L ++#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L ++#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L ++//SPI_VS_OUT_CONFIG ++#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 ++#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 ++#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL ++#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L ++//SPI_PS_INPUT_ENA ++#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 ++#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 ++#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 ++#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 ++#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 ++#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 ++#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 ++#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 ++#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 ++#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 ++#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa ++#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb ++#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc ++#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd ++#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe ++#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf ++#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L ++#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L ++#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L ++#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L ++#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L ++#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L ++#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L ++#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L ++#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L ++#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L ++#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L ++#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L ++#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L ++#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L ++#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L ++#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L ++//SPI_PS_INPUT_ADDR ++#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 ++#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 ++#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 ++#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 ++#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 ++#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 ++#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 ++#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 ++#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 ++#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 ++#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa ++#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb ++#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc ++#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd ++#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe ++#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf ++#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L ++#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L ++#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L ++#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L ++#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L ++#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L ++#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L ++#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L ++#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L ++#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L ++#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L ++#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L ++#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L ++#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L ++#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L ++#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L ++//SPI_INTERP_CONTROL_0 ++#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe ++#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L ++#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L ++//SPI_PS_IN_CONTROL ++#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 ++#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 ++#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 ++#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 ++#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe ++#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL ++#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L ++#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L ++#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L ++#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L ++//SPI_BARYC_CNTL ++#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 ++#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 ++#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 ++#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc ++#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 ++#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 ++#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 ++#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L ++#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L ++#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L ++#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L ++#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L ++#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L ++#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L ++//SPI_TMPRING_SIZE ++#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 ++#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc ++#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL ++#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L ++//SPI_SHADER_POS_FORMAT ++#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 ++#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 ++#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 ++#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc ++#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL ++#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L ++#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L ++#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L ++//SPI_SHADER_Z_FORMAT ++#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 ++#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL ++//SPI_SHADER_COL_FORMAT ++#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 ++#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 ++#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 ++#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc ++#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 ++#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 ++#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 ++#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c ++#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL ++#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L ++#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L ++#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L ++#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L ++#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L ++#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L ++#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L ++//SX_PS_DOWNCONVERT ++#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 ++#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 ++#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 ++#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc ++#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 ++#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 ++#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 ++#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c ++#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL ++#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L ++#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L ++#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L ++#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L ++#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L ++#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L ++#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L ++//SX_BLEND_OPT_EPSILON ++#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 ++#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 ++#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 ++#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc ++#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 ++#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 ++#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 ++#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c ++#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL ++#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L ++#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L ++#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L ++#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L ++#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L ++#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L ++#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L ++//SX_BLEND_OPT_CONTROL ++#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 ++#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 ++#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 ++#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 ++#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 ++#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 ++#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc ++#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd ++#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 ++#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 ++#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 ++#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 ++#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 ++#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 ++#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c ++#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d ++#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f ++#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L ++#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L ++#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L ++#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L ++#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L ++#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L ++#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L ++#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L ++#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L ++#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L ++#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L ++#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L ++#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L ++#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L ++#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L ++#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L ++#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L ++//SX_MRT0_BLEND_OPT ++#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//SX_MRT1_BLEND_OPT ++#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//SX_MRT2_BLEND_OPT ++#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//SX_MRT3_BLEND_OPT ++#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//SX_MRT4_BLEND_OPT ++#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//SX_MRT5_BLEND_OPT ++#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//SX_MRT6_BLEND_OPT ++#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//SX_MRT7_BLEND_OPT ++#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 ++#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 ++#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 ++#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 ++#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 ++#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 ++#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L ++#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L ++#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L ++#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L ++#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L ++#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L ++//CB_BLEND0_CONTROL ++#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_BLEND1_CONTROL ++#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_BLEND2_CONTROL ++#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_BLEND3_CONTROL ++#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_BLEND4_CONTROL ++#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_BLEND5_CONTROL ++#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_BLEND6_CONTROL ++#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_BLEND7_CONTROL ++#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 ++#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 ++#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 ++#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 ++#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 ++#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 ++#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d ++#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e ++#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f ++#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL ++#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L ++#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L ++#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L ++#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L ++#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L ++#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L ++#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L ++#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L ++//CB_MRT0_EPITCH ++#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CB_MRT1_EPITCH ++#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CB_MRT2_EPITCH ++#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CB_MRT3_EPITCH ++#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CB_MRT4_EPITCH ++#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CB_MRT5_EPITCH ++#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CB_MRT6_EPITCH ++#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CB_MRT7_EPITCH ++#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 ++#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL ++//CS_COPY_STATE ++#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 ++#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L ++//GFX_COPY_STATE ++#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 ++#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L ++//PA_CL_POINT_X_RAD ++#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_POINT_Y_RAD ++#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_POINT_SIZE ++#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_POINT_CULL_RAD ++#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL ++//VGT_DMA_BASE_HI ++#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 ++#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL ++//VGT_DMA_BASE ++#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 ++#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL ++//VGT_DRAW_INITIATOR ++#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 ++#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 ++#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 ++#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 ++#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 ++#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 ++#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 ++#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d ++#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L ++#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL ++#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L ++#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L ++#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L ++#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L ++#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L ++#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L ++//VGT_IMMED_DATA ++#define VGT_IMMED_DATA__DATA__SHIFT 0x0 ++#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL ++//VGT_EVENT_ADDRESS_REG ++#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 ++#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL ++//DB_DEPTH_CONTROL ++#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 ++#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 ++#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 ++#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 ++#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 ++#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 ++#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 ++#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 ++#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e ++#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f ++#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L ++#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L ++#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L ++#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L ++#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L ++#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L ++#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L ++#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L ++#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L ++#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L ++//DB_EQAA ++#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 ++#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 ++#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 ++#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc ++#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 ++#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 ++#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 ++#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 ++#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 ++#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 ++#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 ++#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b ++#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L ++#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L ++#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L ++#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L ++#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L ++#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L ++#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L ++#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L ++#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L ++#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L ++#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L ++#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L ++//CB_COLOR_CONTROL ++#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 ++#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 ++#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 ++#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 ++#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L ++#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L ++#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L ++#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L ++//DB_SHADER_CONTROL ++#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 ++#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 ++#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 ++#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 ++#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 ++#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 ++#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 ++#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 ++#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa ++#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb ++#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc ++#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd ++#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf ++#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 ++#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 ++#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 ++#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L ++#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L ++#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L ++#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L ++#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L ++#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L ++#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L ++#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L ++#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L ++#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L ++#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L ++#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L ++#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L ++#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L ++#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L ++#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L ++//PA_CL_CLIP_CNTL ++#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 ++#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 ++#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 ++#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 ++#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 ++#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 ++#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd ++#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe ++#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 ++#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 ++#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 ++#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 ++#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 ++#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 ++#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 ++#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 ++#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 ++#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a ++#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b ++#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c ++#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L ++#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L ++#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L ++#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L ++#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L ++#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L ++#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L ++#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L ++#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L ++#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L ++#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L ++#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L ++#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L ++#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L ++#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L ++#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L ++#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L ++#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L ++#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L ++#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L ++//PA_SU_SC_MODE_CNTL ++#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 ++#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 ++#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 ++#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 ++#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 ++#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 ++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb ++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc ++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd ++#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 ++#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 ++#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 ++#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 ++#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 ++#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 ++#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L ++#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L ++#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L ++#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L ++#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L ++#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L ++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L ++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L ++#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L ++#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L ++#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L ++#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L ++#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L ++#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L ++#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L ++//PA_CL_VTE_CNTL ++#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 ++#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 ++#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 ++#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 ++#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 ++#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 ++#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 ++#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 ++#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa ++#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb ++#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L ++#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L ++#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L ++#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L ++#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L ++#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L ++#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L ++#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L ++#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L ++#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L ++//PA_CL_VS_OUT_CNTL ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf ++#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 ++#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 ++#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 ++#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 ++#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 ++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 ++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 ++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 ++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 ++#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 ++#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a ++#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L ++#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L ++#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L ++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L ++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L ++#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L ++#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L ++#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L ++//PA_CL_NANINF_CNTL ++#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 ++#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 ++#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 ++#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 ++#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 ++#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 ++#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 ++#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 ++#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 ++#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 ++#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa ++#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb ++#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc ++#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd ++#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe ++#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 ++#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L ++#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L ++#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L ++#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L ++#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L ++#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L ++#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L ++#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L ++#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L ++#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L ++#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L ++#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L ++#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L ++#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L ++#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L ++#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L ++//PA_SU_LINE_STIPPLE_CNTL ++#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 ++#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 ++#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 ++#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 ++#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L ++#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L ++#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L ++#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L ++//PA_SU_LINE_STIPPLE_SCALE ++#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 ++#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL ++//PA_SU_PRIM_FILTER_CNTL ++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 ++#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 ++#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 ++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 ++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 ++#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 ++#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 ++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 ++#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 ++#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e ++#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f ++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L ++#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L ++#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L ++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L ++#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L ++#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L ++#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L ++#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L ++#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L ++#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L ++#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L ++//PA_SU_SMALL_PRIM_FILTER_CNTL ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6 ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L ++#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L ++//PA_CL_OBJPRIM_ID_CNTL ++#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 ++#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 ++#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 ++#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L ++#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L ++#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L ++//PA_CL_NGG_CNTL ++#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 ++#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 ++#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L ++#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L ++//PA_SU_OVER_RASTERIZATION_CNTL ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 ++#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L ++#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L ++#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L ++//PA_STEREO_CNTL ++#define PA_STEREO_CNTL__EN_STEREO__SHIFT 0x0 ++#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 ++#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 ++#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 ++#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0xa ++#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0xd ++#define PA_STEREO_CNTL__EN_STEREO_MASK 0x00000001L ++#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL ++#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L ++#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000300L ++#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00001C00L ++#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x0001E000L ++//PA_SU_POINT_SIZE ++#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 ++#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 ++#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL ++#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L ++//PA_SU_POINT_MINMAX ++#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 ++#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 ++#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL ++#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L ++//PA_SU_LINE_CNTL ++#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 ++#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL ++//PA_SC_LINE_STIPPLE ++#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 ++#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 ++#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c ++#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d ++#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL ++#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L ++#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L ++#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L ++//VGT_OUTPUT_PATH_CNTL ++#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 ++#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L ++//VGT_HOS_CNTL ++#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 ++#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L ++//VGT_HOS_MAX_TESS_LEVEL ++#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 ++#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL ++//VGT_HOS_MIN_TESS_LEVEL ++#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 ++#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL ++//VGT_HOS_REUSE_DEPTH ++#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 ++#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL ++//VGT_GROUP_PRIM_TYPE ++#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 ++#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe ++#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf ++#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 ++#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL ++#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L ++#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L ++#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L ++//VGT_GROUP_FIRST_DECR ++#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 ++#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL ++//VGT_GROUP_DECR ++#define VGT_GROUP_DECR__DECR__SHIFT 0x0 ++#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL ++//VGT_GROUP_VECT_0_CNTL ++#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 ++#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 ++#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 ++#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 ++#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 ++#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 ++#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L ++#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L ++#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L ++#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L ++#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L ++#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L ++//VGT_GROUP_VECT_1_CNTL ++#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 ++#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 ++#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 ++#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 ++#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 ++#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 ++#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L ++#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L ++#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L ++#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L ++#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L ++#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L ++//VGT_GROUP_VECT_0_FMT_CNTL ++#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 ++#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 ++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 ++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc ++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 ++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 ++#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 ++#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c ++#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL ++#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L ++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L ++#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L ++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L ++#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L ++#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L ++#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L ++//VGT_GROUP_VECT_1_FMT_CNTL ++#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 ++#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 ++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 ++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc ++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 ++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 ++#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 ++#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c ++#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL ++#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L ++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L ++#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L ++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L ++#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L ++#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L ++#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L ++//VGT_GS_MODE ++#define VGT_GS_MODE__MODE__SHIFT 0x0 ++#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 ++#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 ++#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 ++#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb ++#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc ++#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd ++#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe ++#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf ++#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 ++#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 ++#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 ++#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 ++#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 ++#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 ++#define VGT_GS_MODE__MODE_MASK 0x00000007L ++#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L ++#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L ++#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L ++#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L ++#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L ++#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L ++#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L ++#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L ++#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L ++#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L ++#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L ++#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L ++#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L ++#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L ++//VGT_GS_ONCHIP_CNTL ++#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 ++#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb ++#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 ++#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL ++#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L ++#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L ++//PA_SC_MODE_CNTL_0 ++#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 ++#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 ++#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 ++#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 ++#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 ++#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 ++#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 ++#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L ++#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L ++#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L ++#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L ++#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L ++#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L ++#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L ++//PA_SC_MODE_CNTL_1 ++#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 ++#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 ++#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 ++#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 ++#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 ++#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 ++#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 ++#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 ++#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa ++#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb ++#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc ++#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd ++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe ++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf ++#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 ++#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 ++#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 ++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 ++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 ++#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 ++#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 ++#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a ++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b ++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c ++#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L ++#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L ++#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L ++#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L ++#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L ++#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L ++#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L ++#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L ++#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L ++#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L ++#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L ++#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L ++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L ++#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L ++#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L ++#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L ++#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L ++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L ++#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L ++#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L ++#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L ++#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L ++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L ++#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L ++//VGT_ENHANCE ++#define VGT_ENHANCE__MISC__SHIFT 0x0 ++#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL ++//VGT_GS_PER_ES ++#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 ++#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL ++//VGT_ES_PER_GS ++#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 ++#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL ++//VGT_GS_PER_VS ++#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 ++#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL ++//VGT_GSVS_RING_OFFSET_1 ++#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 ++#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL ++//VGT_GSVS_RING_OFFSET_2 ++#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 ++#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL ++//VGT_GSVS_RING_OFFSET_3 ++#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 ++#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL ++//VGT_GS_OUT_PRIM_TYPE ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 ++#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L ++#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L ++#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L ++//IA_ENHANCE ++#define IA_ENHANCE__MISC__SHIFT 0x0 ++#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL ++//VGT_DMA_SIZE ++#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 ++#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL ++//VGT_DMA_MAX_SIZE ++#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 ++#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL ++//VGT_DMA_INDEX_TYPE ++#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 ++#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 ++#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 ++#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 ++#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 ++#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 ++#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa ++#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L ++#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL ++#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L ++#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L ++#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L ++#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L ++#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L ++//WD_ENHANCE ++#define WD_ENHANCE__MISC__SHIFT 0x0 ++#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL ++//VGT_PRIMITIVEID_EN ++#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 ++#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 ++#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 ++#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L ++#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L ++#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L ++//VGT_DMA_NUM_INSTANCES ++#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 ++#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL ++//VGT_PRIMITIVEID_RESET ++#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 ++#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL ++//VGT_EVENT_INITIATOR ++#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 ++#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa ++#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b ++#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL ++#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L ++#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L ++//VGT_GS_MAX_PRIMS_PER_SUBGROUP ++#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 ++#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL ++//VGT_DRAW_PAYLOAD_CNTL ++#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 ++#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 ++#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 ++#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 ++#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L ++#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L ++#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L ++#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L ++//VGT_INSTANCE_STEP_RATE_0 ++#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 ++#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL ++//VGT_INSTANCE_STEP_RATE_1 ++#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 ++#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL ++//IA_MULTI_VGT_PARAM_BC ++//VGT_ESGS_RING_ITEMSIZE ++#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 ++#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL ++//VGT_GSVS_RING_ITEMSIZE ++#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 ++#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL ++//VGT_REUSE_OFF ++#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 ++#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L ++//VGT_VTX_CNT_EN ++#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 ++#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L ++//DB_HTILE_SURFACE ++#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 ++#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 ++#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 ++#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 ++#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa ++#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 ++#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 ++#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 ++#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L ++#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L ++#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L ++#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L ++#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L ++#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L ++#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L ++#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L ++//DB_SRESULTS_COMPARE_STATE0 ++#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 ++#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 ++#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc ++#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 ++#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L ++#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L ++#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L ++#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L ++//DB_SRESULTS_COMPARE_STATE1 ++#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 ++#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 ++#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc ++#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 ++#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L ++#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L ++#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L ++#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L ++//DB_PRELOAD_CONTROL ++#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 ++#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 ++#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 ++#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 ++#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL ++#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L ++#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L ++#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L ++//VGT_STRMOUT_BUFFER_SIZE_0 ++#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_VTX_STRIDE_0 ++#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 ++#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL ++//VGT_STRMOUT_BUFFER_OFFSET_0 ++#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_BUFFER_SIZE_1 ++#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_VTX_STRIDE_1 ++#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 ++#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL ++//VGT_STRMOUT_BUFFER_OFFSET_1 ++#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_BUFFER_SIZE_2 ++#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_VTX_STRIDE_2 ++#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 ++#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL ++//VGT_STRMOUT_BUFFER_OFFSET_2 ++#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_BUFFER_SIZE_3 ++#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_VTX_STRIDE_3 ++#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 ++#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL ++//VGT_STRMOUT_BUFFER_OFFSET_3 ++#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_DRAW_OPAQUE_OFFSET ++#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 ++#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE ++#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE ++#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 ++#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL ++//VGT_GS_MAX_VERT_OUT ++#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 ++#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL ++//VGT_TESS_DISTRIBUTION ++#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 ++#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 ++#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 ++#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 ++#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d ++#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL ++#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L ++#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L ++#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L ++#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L ++//VGT_SHADER_STAGES_EN ++#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 ++#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 ++#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 ++#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 ++#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 ++#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 ++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa ++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb ++#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc ++#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd ++#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe ++#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf ++#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 ++#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L ++#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L ++#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L ++#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L ++#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L ++#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L ++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L ++#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L ++#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L ++#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L ++#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L ++#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L ++#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L ++//VGT_LS_HS_CONFIG ++#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 ++#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 ++#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe ++#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL ++#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L ++#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L ++//VGT_GS_VERT_ITEMSIZE ++#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 ++#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL ++//VGT_GS_VERT_ITEMSIZE_1 ++#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 ++#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL ++//VGT_GS_VERT_ITEMSIZE_2 ++#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 ++#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL ++//VGT_GS_VERT_ITEMSIZE_3 ++#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 ++#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL ++//VGT_TF_PARAM ++#define VGT_TF_PARAM__TYPE__SHIFT 0x0 ++#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 ++#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 ++#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 ++#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 ++#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe ++#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf ++#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 ++#define VGT_TF_PARAM__TYPE_MASK 0x00000003L ++#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL ++#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L ++#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L ++#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L ++#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L ++#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L ++#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L ++//DB_ALPHA_TO_MASK ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe ++#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L ++#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L ++#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L ++//VGT_DISPATCH_DRAW_INDEX ++#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 ++#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL ++//PA_SU_POLY_OFFSET_DB_FMT_CNTL ++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 ++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 ++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL ++#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L ++//PA_SU_POLY_OFFSET_CLAMP ++#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 ++#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL ++//PA_SU_POLY_OFFSET_FRONT_SCALE ++#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 ++#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL ++//PA_SU_POLY_OFFSET_FRONT_OFFSET ++#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 ++#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL ++//PA_SU_POLY_OFFSET_BACK_SCALE ++#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 ++#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL ++//PA_SU_POLY_OFFSET_BACK_OFFSET ++#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 ++#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL ++//VGT_GS_INSTANCE_CNT ++#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 ++#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 ++#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L ++#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL ++//VGT_STRMOUT_CONFIG ++#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 ++#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 ++#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 ++#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 ++#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 ++#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 ++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 ++#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f ++#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L ++#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L ++#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L ++#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L ++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L ++#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L ++#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L ++#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L ++//VGT_STRMOUT_BUFFER_CONFIG ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L ++#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L ++//VGT_DMA_EVENT_INITIATOR ++#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 ++#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa ++#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b ++#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL ++#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L ++#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L ++//PA_SC_CENTROID_PRIORITY_0 ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L ++#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L ++//PA_SC_CENTROID_PRIORITY_1 ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L ++#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L ++//PA_SC_LINE_CNTL ++#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 ++#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa ++#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb ++#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc ++#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd ++#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L ++#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L ++#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L ++#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L ++#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L ++//PA_SC_AA_CONFIG ++#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 ++#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 ++#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd ++#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 ++#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 ++#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a ++#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L ++#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L ++#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L ++#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L ++#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L ++#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L ++//PA_SU_VTX_CNTL ++#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 ++#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 ++#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 ++#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L ++#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L ++#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L ++//PA_CL_GB_VERT_CLIP_ADJ ++#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_GB_VERT_DISC_ADJ ++#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_GB_HORZ_CLIP_ADJ ++#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_CL_GB_HORZ_DISC_ADJ ++#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 ++#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L ++//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L ++#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L ++//PA_SC_AA_MASK_X0Y0_X1Y0 ++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 ++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 ++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL ++#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L ++//PA_SC_AA_MASK_X0Y1_X1Y1 ++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 ++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 ++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL ++#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L ++//PA_SC_SHADER_CONTROL ++#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 ++#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 ++#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 ++#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L ++#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L ++#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L ++//PA_SC_BINNER_CNTL_0 ++#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 ++#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa ++#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd ++#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 ++#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 ++#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b ++#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c ++#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L ++#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L ++#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L ++#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L ++#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L ++#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L ++#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L ++#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L ++//PA_SC_BINNER_CNTL_1 ++#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 ++#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 ++#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL ++#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L ++//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L ++#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L ++//PA_SC_NGG_MODE_CNTL ++#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 ++#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL ++//VGT_VERTEX_REUSE_BLOCK_CNTL ++#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 ++#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL ++//VGT_OUT_DEALLOC_CNTL ++#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 ++#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL ++//CB_COLOR0_BASE ++#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR0_BASE_EXT ++#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR0_ATTRIB2 ++#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR0_VIEW ++#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR0_INFO ++#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR0_ATTRIB ++#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR0_DCC_CONTROL ++#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR0_CMASK ++#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR0_CMASK_BASE_EXT ++#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR0_FMASK ++#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR0_FMASK_BASE_EXT ++#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR0_CLEAR_WORD0 ++#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR0_CLEAR_WORD1 ++#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR0_DCC_BASE ++#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR0_DCC_BASE_EXT ++#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR1_BASE ++#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR1_BASE_EXT ++#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR1_ATTRIB2 ++#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR1_VIEW ++#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR1_INFO ++#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR1_ATTRIB ++#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR1_DCC_CONTROL ++#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR1_CMASK ++#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR1_CMASK_BASE_EXT ++#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR1_FMASK ++#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR1_FMASK_BASE_EXT ++#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR1_CLEAR_WORD0 ++#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR1_CLEAR_WORD1 ++#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR1_DCC_BASE ++#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR1_DCC_BASE_EXT ++#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR2_BASE ++#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR2_BASE_EXT ++#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR2_ATTRIB2 ++#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR2_VIEW ++#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR2_INFO ++#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR2_ATTRIB ++#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR2_DCC_CONTROL ++#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR2_CMASK ++#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR2_CMASK_BASE_EXT ++#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR2_FMASK ++#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR2_FMASK_BASE_EXT ++#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR2_CLEAR_WORD0 ++#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR2_CLEAR_WORD1 ++#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR2_DCC_BASE ++#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR2_DCC_BASE_EXT ++#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR3_BASE ++#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR3_BASE_EXT ++#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR3_ATTRIB2 ++#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR3_VIEW ++#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR3_INFO ++#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR3_ATTRIB ++#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR3_DCC_CONTROL ++#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR3_CMASK ++#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR3_CMASK_BASE_EXT ++#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR3_FMASK ++#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR3_FMASK_BASE_EXT ++#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR3_CLEAR_WORD0 ++#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR3_CLEAR_WORD1 ++#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR3_DCC_BASE ++#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR3_DCC_BASE_EXT ++#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR4_BASE ++#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR4_BASE_EXT ++#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR4_ATTRIB2 ++#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR4_VIEW ++#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR4_INFO ++#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR4_ATTRIB ++#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR4_DCC_CONTROL ++#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR4_CMASK ++#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR4_CMASK_BASE_EXT ++#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR4_FMASK ++#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR4_FMASK_BASE_EXT ++#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR4_CLEAR_WORD0 ++#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR4_CLEAR_WORD1 ++#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR4_DCC_BASE ++#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR4_DCC_BASE_EXT ++#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR5_BASE ++#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR5_BASE_EXT ++#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR5_ATTRIB2 ++#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR5_VIEW ++#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR5_INFO ++#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR5_ATTRIB ++#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR5_DCC_CONTROL ++#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR5_CMASK ++#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR5_CMASK_BASE_EXT ++#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR5_FMASK ++#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR5_FMASK_BASE_EXT ++#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR5_CLEAR_WORD0 ++#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR5_CLEAR_WORD1 ++#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR5_DCC_BASE ++#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR5_DCC_BASE_EXT ++#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR6_BASE ++#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR6_BASE_EXT ++#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR6_ATTRIB2 ++#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR6_VIEW ++#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR6_INFO ++#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR6_ATTRIB ++#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR6_DCC_CONTROL ++#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR6_CMASK ++#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR6_CMASK_BASE_EXT ++#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR6_FMASK ++#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR6_FMASK_BASE_EXT ++#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR6_CLEAR_WORD0 ++#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR6_CLEAR_WORD1 ++#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR6_DCC_BASE ++#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR6_DCC_BASE_EXT ++#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR7_BASE ++#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR7_BASE_EXT ++#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR7_ATTRIB2 ++#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 ++#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe ++#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c ++#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL ++#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L ++#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L ++//CB_COLOR7_VIEW ++#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 ++#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd ++#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 ++#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL ++#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L ++#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L ++//CB_COLOR7_INFO ++#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 ++#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 ++#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 ++#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb ++#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd ++#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe ++#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf ++#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 ++#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 ++#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 ++#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 ++#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 ++#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a ++#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b ++#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c ++#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d ++#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L ++#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL ++#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L ++#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L ++#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L ++#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L ++#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L ++#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L ++#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L ++#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L ++#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L ++#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L ++#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L ++#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L ++#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L ++#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L ++//CB_COLOR7_ATTRIB ++#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 ++#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb ++#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc ++#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf ++#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 ++#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 ++#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 ++#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c ++#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e ++#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f ++#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL ++#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L ++#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L ++#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L ++#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L ++#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L ++#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L ++#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L ++#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L ++#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L ++//CB_COLOR7_DCC_CONTROL ++#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 ++#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 ++#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 ++#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 ++#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 ++#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 ++#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 ++#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa ++#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe ++#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 ++#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 ++#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L ++#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L ++#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL ++#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L ++#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L ++#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L ++#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L ++#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L ++#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L ++#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L ++#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L ++//CB_COLOR7_CMASK ++#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR7_CMASK_BASE_EXT ++#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR7_FMASK ++#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR7_FMASK_BASE_EXT ++#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL ++//CB_COLOR7_CLEAR_WORD0 ++#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 ++#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL ++//CB_COLOR7_CLEAR_WORD1 ++#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 ++#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL ++//CB_COLOR7_DCC_BASE ++#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL ++//CB_COLOR7_DCC_BASE_EXT ++#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 ++#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL ++ ++ ++// addressBlock: gc_gfxudec ++//CP_EOP_DONE_ADDR_LO ++#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 ++#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL ++//CP_EOP_DONE_ADDR_HI ++#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_EOP_DONE_DATA_LO ++#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 ++#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL ++//CP_EOP_DONE_DATA_HI ++#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 ++#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL ++//CP_EOP_LAST_FENCE_LO ++#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 ++#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL ++//CP_EOP_LAST_FENCE_HI ++#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 ++#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL ++//CP_STREAM_OUT_ADDR_LO ++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 ++#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL ++//CP_STREAM_OUT_ADDR_HI ++#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 ++#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT0_LO ++#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT0_HI ++#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT0_LO ++#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT0_HI ++#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT1_LO ++#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT1_HI ++#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT1_LO ++#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT1_HI ++#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT2_LO ++#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT2_HI ++#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT2_LO ++#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT2_HI ++#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT3_LO ++#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_WRITTEN_COUNT3_HI ++#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT3_LO ++#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL ++//CP_NUM_PRIM_NEEDED_COUNT3_HI ++#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 ++#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL ++//CP_PIPE_STATS_ADDR_LO ++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 ++#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL ++//CP_PIPE_STATS_ADDR_HI ++#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 ++#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL ++//CP_VGT_IAVERT_COUNT_LO ++#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_IAVERT_COUNT_HI ++#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_VGT_IAPRIM_COUNT_LO ++#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_IAPRIM_COUNT_HI ++#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_VGT_GSPRIM_COUNT_LO ++#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_GSPRIM_COUNT_HI ++#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_VGT_VSINVOC_COUNT_LO ++#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_VSINVOC_COUNT_HI ++#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_VGT_GSINVOC_COUNT_LO ++#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_GSINVOC_COUNT_HI ++#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_VGT_HSINVOC_COUNT_LO ++#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_HSINVOC_COUNT_HI ++#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_VGT_DSINVOC_COUNT_LO ++#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_DSINVOC_COUNT_HI ++#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_PA_CINVOC_COUNT_LO ++#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 ++#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_PA_CINVOC_COUNT_HI ++#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 ++#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_PA_CPRIM_COUNT_LO ++#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 ++#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_PA_CPRIM_COUNT_HI ++#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 ++#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_SC_PSINVOC_COUNT0_LO ++#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 ++#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL ++//CP_SC_PSINVOC_COUNT0_HI ++#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 ++#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL ++//CP_SC_PSINVOC_COUNT1_LO ++#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 ++#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL ++//CP_SC_PSINVOC_COUNT1_HI ++#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 ++#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL ++//CP_VGT_CSINVOC_COUNT_LO ++#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 ++#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL ++//CP_VGT_CSINVOC_COUNT_HI ++#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 ++#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL ++//CP_PIPE_STATS_CONTROL ++#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 ++#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L ++//CP_STREAM_OUT_CONTROL ++#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 ++#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L ++//CP_STRMOUT_CNTL ++#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 ++#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L ++//SCRATCH_REG0 ++#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 ++#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL ++//SCRATCH_REG1 ++#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 ++#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL ++//SCRATCH_REG2 ++#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 ++#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL ++//SCRATCH_REG3 ++#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 ++#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL ++//SCRATCH_REG4 ++#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 ++#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL ++//SCRATCH_REG5 ++#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 ++#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL ++//SCRATCH_REG6 ++#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 ++#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL ++//SCRATCH_REG7 ++#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 ++#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL ++//CP_APPEND_DATA_HI ++#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 ++#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL ++//CP_APPEND_LAST_CS_FENCE_HI ++#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 ++#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL ++//CP_APPEND_LAST_PS_FENCE_HI ++#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 ++#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL ++//SCRATCH_UMSK ++#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 ++#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 ++#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL ++#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L ++//SCRATCH_ADDR ++#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 ++#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL ++//CP_PFP_ATOMIC_PREOP_LO ++#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 ++#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_PFP_ATOMIC_PREOP_HI ++#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 ++#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_PFP_GDS_ATOMIC0_PREOP_LO ++#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 ++#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_PFP_GDS_ATOMIC0_PREOP_HI ++#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 ++#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_PFP_GDS_ATOMIC1_PREOP_LO ++#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 ++#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_PFP_GDS_ATOMIC1_PREOP_HI ++#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 ++#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_APPEND_ADDR_LO ++#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 ++#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL ++//CP_APPEND_ADDR_HI ++#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 ++#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 ++#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 ++#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d ++#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL ++#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L ++#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L ++#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L ++//CP_APPEND_DATA_LO ++#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 ++#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL ++//CP_APPEND_LAST_CS_FENCE_LO ++#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 ++#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL ++//CP_APPEND_LAST_PS_FENCE_LO ++#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 ++#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL ++//CP_ATOMIC_PREOP_LO ++#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 ++#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_ME_ATOMIC_PREOP_LO ++#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 ++#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_ATOMIC_PREOP_HI ++#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 ++#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_ME_ATOMIC_PREOP_HI ++#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 ++#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_GDS_ATOMIC0_PREOP_LO ++#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 ++#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_ME_GDS_ATOMIC0_PREOP_LO ++#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 ++#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_GDS_ATOMIC0_PREOP_HI ++#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 ++#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_ME_GDS_ATOMIC0_PREOP_HI ++#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 ++#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_GDS_ATOMIC1_PREOP_LO ++#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 ++#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_ME_GDS_ATOMIC1_PREOP_LO ++#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 ++#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL ++//CP_GDS_ATOMIC1_PREOP_HI ++#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 ++#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_ME_GDS_ATOMIC1_PREOP_HI ++#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 ++#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL ++//CP_ME_MC_WADDR_LO ++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 ++#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL ++//CP_ME_MC_WADDR_HI ++#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 ++#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 ++#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL ++#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L ++//CP_ME_MC_WDATA_LO ++#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 ++#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL ++//CP_ME_MC_WDATA_HI ++#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 ++#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL ++//CP_ME_MC_RADDR_LO ++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 ++#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL ++//CP_ME_MC_RADDR_HI ++#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 ++#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 ++#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL ++#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L ++//CP_SEM_WAIT_TIMER ++#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 ++#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL ++//CP_SIG_SEM_ADDR_LO ++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 ++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 ++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L ++#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L ++//CP_SIG_SEM_ADDR_HI ++#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 ++#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 ++#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 ++#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 ++#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d ++#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL ++#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L ++#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L ++#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L ++#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L ++//CP_WAIT_REG_MEM_TIMEOUT ++#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 ++#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL ++//CP_WAIT_SEM_ADDR_LO ++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 ++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 ++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L ++#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L ++//CP_WAIT_SEM_ADDR_HI ++#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 ++#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 ++#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 ++#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 ++#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d ++#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL ++#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L ++#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L ++#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L ++#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L ++//CP_DMA_PFP_CONTROL ++#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa ++#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd ++#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 ++#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 ++#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d ++#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L ++#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L ++#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L ++#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L ++#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L ++//CP_DMA_ME_CONTROL ++#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa ++#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd ++#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 ++#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 ++#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d ++#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L ++#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L ++#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L ++#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L ++#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L ++//CP_COHER_BASE_HI ++#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 ++#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL ++//CP_COHER_START_DELAY ++#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 ++#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL ++//CP_COHER_CNTL ++#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 ++#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 ++#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 ++#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf ++#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 ++#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 ++#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 ++#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 ++#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a ++#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b ++#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c ++#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d ++#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e ++#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L ++#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L ++#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L ++#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L ++#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L ++#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L ++#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L ++#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L ++#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L ++#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L ++#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L ++#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L ++#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L ++//CP_COHER_SIZE ++#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 ++#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL ++//CP_COHER_BASE ++#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 ++#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL ++//CP_COHER_STATUS ++#define CP_COHER_STATUS__MEID__SHIFT 0x18 ++#define CP_COHER_STATUS__STATUS__SHIFT 0x1f ++#define CP_COHER_STATUS__MEID_MASK 0x03000000L ++#define CP_COHER_STATUS__STATUS_MASK 0x80000000L ++//CP_DMA_ME_SRC_ADDR ++#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 ++#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL ++//CP_DMA_ME_SRC_ADDR_HI ++#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 ++#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL ++//CP_DMA_ME_DST_ADDR ++#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 ++#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL ++//CP_DMA_ME_DST_ADDR_HI ++#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 ++#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL ++//CP_DMA_ME_COMMAND ++#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 ++#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a ++#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b ++#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c ++#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d ++#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e ++#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f ++#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL ++#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L ++#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L ++#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L ++#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L ++#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L ++#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L ++//CP_DMA_PFP_SRC_ADDR ++#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 ++#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL ++//CP_DMA_PFP_SRC_ADDR_HI ++#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 ++#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL ++//CP_DMA_PFP_DST_ADDR ++#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 ++#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL ++//CP_DMA_PFP_DST_ADDR_HI ++#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 ++#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL ++//CP_DMA_PFP_COMMAND ++#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 ++#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a ++#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b ++#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c ++#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d ++#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e ++#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f ++#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL ++#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L ++#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L ++#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L ++#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L ++#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L ++#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L ++//CP_DMA_CNTL ++#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 ++#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 ++#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 ++#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c ++#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d ++#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e ++#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L ++#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L ++#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L ++#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L ++#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L ++#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L ++//CP_DMA_READ_TAGS ++#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 ++#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c ++#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL ++#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L ++//CP_COHER_SIZE_HI ++#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 ++#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL ++//CP_PFP_IB_CONTROL ++#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 ++#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL ++//CP_PFP_LOAD_CONTROL ++#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 ++#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 ++#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 ++#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 ++#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L ++#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L ++#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L ++#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L ++//CP_SCRATCH_INDEX ++#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 ++#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL ++//CP_SCRATCH_DATA ++#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 ++#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL ++//CP_RB_OFFSET ++#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 ++#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL ++//CP_IB1_OFFSET ++#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 ++#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL ++//CP_IB2_OFFSET ++#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 ++#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL ++//CP_IB1_PREAMBLE_BEGIN ++#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 ++#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL ++//CP_IB1_PREAMBLE_END ++#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 ++#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL ++//CP_IB2_PREAMBLE_BEGIN ++#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 ++#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL ++//CP_IB2_PREAMBLE_END ++#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 ++#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL ++//CP_CE_IB1_OFFSET ++#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 ++#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL ++//CP_CE_IB2_OFFSET ++#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 ++#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL ++//CP_CE_COUNTER ++#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 ++#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL ++//CP_CE_RB_OFFSET ++#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 ++#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL ++//CP_CE_INIT_CMD_BUFSZ ++#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 ++#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL ++//CP_CE_IB1_CMD_BUFSZ ++#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 ++#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL ++//CP_CE_IB2_CMD_BUFSZ ++#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 ++#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL ++//CP_IB1_CMD_BUFSZ ++#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 ++#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL ++//CP_IB2_CMD_BUFSZ ++#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 ++#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL ++//CP_ST_CMD_BUFSZ ++#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 ++#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL ++//CP_CE_INIT_BASE_LO ++#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 ++#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L ++//CP_CE_INIT_BASE_HI ++#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 ++#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL ++//CP_CE_INIT_BUFSZ ++#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 ++#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL ++//CP_CE_IB1_BASE_LO ++#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 ++#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL ++//CP_CE_IB1_BASE_HI ++#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 ++#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL ++//CP_CE_IB1_BUFSZ ++#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 ++#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL ++//CP_CE_IB2_BASE_LO ++#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 ++#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL ++//CP_CE_IB2_BASE_HI ++#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 ++#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL ++//CP_CE_IB2_BUFSZ ++#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 ++#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL ++//CP_IB1_BASE_LO ++#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 ++#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL ++//CP_IB1_BASE_HI ++#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 ++#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL ++//CP_IB1_BUFSZ ++#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 ++#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL ++//CP_IB2_BASE_LO ++#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 ++#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL ++//CP_IB2_BASE_HI ++#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 ++#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL ++//CP_IB2_BUFSZ ++#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 ++#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL ++//CP_ST_BASE_LO ++#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 ++#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL ++//CP_ST_BASE_HI ++#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 ++#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL ++//CP_ST_BUFSZ ++#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 ++#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL ++//CP_EOP_DONE_EVENT_CNTL ++#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 ++#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc ++#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 ++#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c ++#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL ++#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L ++#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L ++#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L ++//CP_EOP_DONE_DATA_CNTL ++#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 ++#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 ++#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d ++#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L ++#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L ++#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L ++//CP_EOP_DONE_CNTX_ID ++#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 ++#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL ++//CP_PFP_COMPLETION_STATUS ++#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 ++#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L ++//CP_CE_COMPLETION_STATUS ++#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 ++#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L ++//CP_PRED_NOT_VISIBLE ++#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 ++#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L ++//CP_PFP_METADATA_BASE_ADDR ++#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 ++#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL ++//CP_PFP_METADATA_BASE_ADDR_HI ++#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_CE_METADATA_BASE_ADDR ++#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 ++#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL ++//CP_CE_METADATA_BASE_ADDR_HI ++#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_DRAW_INDX_INDR_ADDR ++#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 ++#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL ++//CP_DRAW_INDX_INDR_ADDR_HI ++#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_DISPATCH_INDR_ADDR ++#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 ++#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL ++//CP_DISPATCH_INDR_ADDR_HI ++#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_INDEX_BASE_ADDR ++#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 ++#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL ++//CP_INDEX_BASE_ADDR_HI ++#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_INDEX_TYPE ++#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 ++#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L ++//CP_GDS_BKUP_ADDR ++#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 ++#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL ++//CP_GDS_BKUP_ADDR_HI ++#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 ++#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL ++//CP_SAMPLE_STATUS ++#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 ++#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 ++#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 ++#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 ++#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 ++#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 ++#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 ++#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 ++#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L ++#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L ++#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L ++#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L ++#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L ++#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L ++#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L ++#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L ++//CP_ME_COHER_CNTL ++#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 ++#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 ++#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 ++#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 ++#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 ++#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 ++#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa ++#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb ++#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc ++#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd ++#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe ++#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 ++#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 ++#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L ++#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L ++#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L ++#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L ++#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L ++#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L ++#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L ++#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L ++#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L ++#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L ++#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L ++#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L ++#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L ++//CP_ME_COHER_SIZE ++#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 ++#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL ++//CP_ME_COHER_SIZE_HI ++#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 ++#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL ++//CP_ME_COHER_BASE ++#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 ++#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL ++//CP_ME_COHER_BASE_HI ++#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 ++#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL ++//CP_ME_COHER_STATUS ++#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 ++#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f ++#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL ++#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L ++//RLC_GPM_PERF_COUNT_0 ++#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 ++#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 ++#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 ++#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc ++#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 ++#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 ++#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 ++#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 ++#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL ++#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L ++#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L ++#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L ++#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L ++#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L ++#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L ++#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L ++//RLC_GPM_PERF_COUNT_1 ++#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 ++#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 ++#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 ++#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc ++#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 ++#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 ++#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 ++#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 ++#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL ++#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L ++#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L ++#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L ++#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L ++#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L ++#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L ++#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L ++//GRBM_GFX_INDEX ++#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 ++#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 ++#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 ++#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d ++#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e ++#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f ++#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL ++#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L ++#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L ++#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L ++#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L ++#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L ++//VGT_GSVS_RING_SIZE ++#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 ++#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL ++//VGT_PRIMITIVE_TYPE ++#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 ++#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL ++//VGT_INDEX_TYPE ++#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 ++#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 ++#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L ++#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L ++//VGT_STRMOUT_BUFFER_FILLED_SIZE_0 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_BUFFER_FILLED_SIZE_1 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_BUFFER_FILLED_SIZE_2 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL ++//VGT_STRMOUT_BUFFER_FILLED_SIZE_3 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 ++#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL ++//VGT_MAX_VTX_INDX ++#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 ++#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL ++//VGT_MIN_VTX_INDX ++#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 ++#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL ++//VGT_INDX_OFFSET ++#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 ++#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL ++//VGT_MULTI_PRIM_IB_RESET_EN ++#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 ++#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 ++#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L ++#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L ++//VGT_NUM_INDICES ++#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 ++#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL ++//VGT_NUM_INSTANCES ++#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 ++#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL ++//VGT_TF_RING_SIZE ++#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 ++#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL ++//VGT_HS_OFFCHIP_PARAM ++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 ++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 ++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL ++#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L ++//VGT_TF_MEMORY_BASE ++#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 ++#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL ++//VGT_TF_MEMORY_BASE_HI ++#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 ++#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL ++//WD_POS_BUF_BASE ++#define WD_POS_BUF_BASE__BASE__SHIFT 0x0 ++#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL ++//WD_POS_BUF_BASE_HI ++#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 ++#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL ++//WD_CNTL_SB_BUF_BASE ++#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 ++#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL ++//WD_CNTL_SB_BUF_BASE_HI ++#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 ++#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL ++//WD_INDEX_BUF_BASE ++#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 ++#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL ++//WD_INDEX_BUF_BASE_HI ++#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 ++#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL ++//IA_MULTI_VGT_PARAM ++#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 ++#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 ++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 ++#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 ++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 ++#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 ++#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 ++#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 ++#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 ++#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL ++#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L ++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L ++#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L ++#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L ++#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L ++#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L ++#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L ++#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L ++//VGT_INSTANCE_BASE_ID ++#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 ++#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL ++//PA_SU_LINE_STIPPLE_VALUE ++#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 ++#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL ++//PA_SC_LINE_STIPPLE_STATE ++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 ++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 ++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL ++#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L ++//PA_SC_SCREEN_EXTENT_MIN_0 ++#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 ++#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 ++#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL ++#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L ++//PA_SC_SCREEN_EXTENT_MAX_0 ++#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 ++#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 ++#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL ++#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L ++//PA_SC_SCREEN_EXTENT_MIN_1 ++#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 ++#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 ++#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL ++#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L ++//PA_SC_SCREEN_EXTENT_MAX_1 ++#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 ++#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 ++#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL ++#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L ++//PA_SC_P3D_TRAP_SCREEN_HV_EN ++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 ++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 ++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L ++#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L ++//PA_SC_P3D_TRAP_SCREEN_H ++#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 ++#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL ++//PA_SC_P3D_TRAP_SCREEN_V ++#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 ++#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL ++//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE ++#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 ++#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL ++//PA_SC_P3D_TRAP_SCREEN_COUNT ++#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 ++#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL ++//PA_SC_HP3D_TRAP_SCREEN_HV_EN ++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 ++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 ++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L ++#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L ++//PA_SC_HP3D_TRAP_SCREEN_H ++#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 ++#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL ++//PA_SC_HP3D_TRAP_SCREEN_V ++#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 ++#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL ++//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE ++#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 ++#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL ++//PA_SC_HP3D_TRAP_SCREEN_COUNT ++#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 ++#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL ++//PA_SC_TRAP_SCREEN_HV_EN ++#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 ++#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 ++#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L ++#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L ++//PA_SC_TRAP_SCREEN_H ++#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 ++#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL ++//PA_SC_TRAP_SCREEN_V ++#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 ++#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL ++//PA_SC_TRAP_SCREEN_OCCURRENCE ++#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 ++#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL ++//PA_SC_TRAP_SCREEN_COUNT ++#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 ++#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL ++//PA_STATE_STEREO_X ++#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 ++#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_BASE ++#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 ++#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_SIZE ++#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 ++#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL ++//SQ_THREAD_TRACE_MASK ++#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 ++#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 ++#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 ++#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 ++#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc ++#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe ++#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf ++#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL ++#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L ++#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L ++#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L ++#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L ++#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L ++#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L ++//SQ_THREAD_TRACE_TOKEN_MASK ++#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 ++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 ++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 ++#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL ++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L ++#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L ++//SQ_THREAD_TRACE_PERF_MASK ++#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 ++#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 ++#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL ++#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L ++//SQ_THREAD_TRACE_CTRL ++#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f ++#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L ++//SQ_THREAD_TRACE_MODE ++#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 ++#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 ++#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 ++#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 ++#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc ++#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf ++#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 ++#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 ++#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 ++#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 ++#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a ++#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b ++#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d ++#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e ++#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f ++#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L ++#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L ++#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L ++#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L ++#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L ++#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L ++#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L ++#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L ++#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L ++#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L ++#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L ++#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L ++#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L ++#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L ++#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L ++//SQ_THREAD_TRACE_BASE2 ++#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 ++#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL ++//SQ_THREAD_TRACE_TOKEN_MASK2 ++#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 ++#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_WPTR ++#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 ++#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e ++#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL ++#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L ++//SQ_THREAD_TRACE_STATUS ++#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 ++#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 ++#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c ++#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d ++#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e ++#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f ++#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL ++#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L ++#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L ++#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L ++#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L ++#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L ++//SQ_THREAD_TRACE_HIWATER ++#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 ++#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L ++//SQ_THREAD_TRACE_CNTR ++#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 ++#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_USERDATA_0 ++#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 ++#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_USERDATA_1 ++#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 ++#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_USERDATA_2 ++#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 ++#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL ++//SQ_THREAD_TRACE_USERDATA_3 ++#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 ++#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL ++//SQC_CACHES ++#define SQC_CACHES__TARGET_INST__SHIFT 0x0 ++#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 ++#define SQC_CACHES__INVALIDATE__SHIFT 0x2 ++#define SQC_CACHES__WRITEBACK__SHIFT 0x3 ++#define SQC_CACHES__VOL__SHIFT 0x4 ++#define SQC_CACHES__COMPLETE__SHIFT 0x10 ++#define SQC_CACHES__TARGET_INST_MASK 0x00000001L ++#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L ++#define SQC_CACHES__INVALIDATE_MASK 0x00000004L ++#define SQC_CACHES__WRITEBACK_MASK 0x00000008L ++#define SQC_CACHES__VOL_MASK 0x00000010L ++#define SQC_CACHES__COMPLETE_MASK 0x00010000L ++//SQC_WRITEBACK ++#define SQC_WRITEBACK__DWB__SHIFT 0x0 ++#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 ++#define SQC_WRITEBACK__DWB_MASK 0x00000001L ++#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L ++//TA_CS_BC_BASE_ADDR ++#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 ++#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL ++//TA_CS_BC_BASE_ADDR_HI ++#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 ++#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL ++//DB_OCCLUSION_COUNT0_LOW ++#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL ++//DB_OCCLUSION_COUNT0_HI ++#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL ++//DB_OCCLUSION_COUNT1_LOW ++#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL ++//DB_OCCLUSION_COUNT1_HI ++#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL ++//DB_OCCLUSION_COUNT2_LOW ++#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL ++//DB_OCCLUSION_COUNT2_HI ++#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL ++//DB_OCCLUSION_COUNT3_LOW ++#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL ++//DB_OCCLUSION_COUNT3_HI ++#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 ++#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL ++//DB_ZPASS_COUNT_LOW ++#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 ++#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL ++//DB_ZPASS_COUNT_HI ++#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 ++#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL ++//GDS_RD_ADDR ++#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 ++#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL ++//GDS_RD_DATA ++#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 ++#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL ++//GDS_RD_BURST_ADDR ++#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 ++#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL ++//GDS_RD_BURST_COUNT ++#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 ++#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL ++//GDS_RD_BURST_DATA ++#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 ++#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL ++//GDS_WR_ADDR ++#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 ++#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL ++//GDS_WR_DATA ++#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 ++#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL ++//GDS_WR_BURST_ADDR ++#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 ++#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL ++//GDS_WR_BURST_DATA ++#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 ++#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL ++//GDS_WRITE_COMPLETE ++#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 ++#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL ++//GDS_ATOM_CNTL ++#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 ++#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 ++#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 ++#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa ++#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL ++#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L ++#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L ++#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L ++//GDS_ATOM_COMPLETE ++#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 ++#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 ++#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L ++#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL ++//GDS_ATOM_BASE ++#define GDS_ATOM_BASE__BASE__SHIFT 0x0 ++#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 ++#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL ++#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L ++//GDS_ATOM_SIZE ++#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 ++#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 ++#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL ++#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L ++//GDS_ATOM_OFFSET0 ++#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 ++#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 ++#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL ++#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L ++//GDS_ATOM_OFFSET1 ++#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 ++#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 ++#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL ++#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L ++//GDS_ATOM_DST ++#define GDS_ATOM_DST__DST__SHIFT 0x0 ++#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL ++//GDS_ATOM_OP ++#define GDS_ATOM_OP__OP__SHIFT 0x0 ++#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 ++#define GDS_ATOM_OP__OP_MASK 0x000000FFL ++#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L ++//GDS_ATOM_SRC0 ++#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 ++#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL ++//GDS_ATOM_SRC0_U ++#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 ++#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL ++//GDS_ATOM_SRC1 ++#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 ++#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL ++//GDS_ATOM_SRC1_U ++#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 ++#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL ++//GDS_ATOM_READ0 ++#define GDS_ATOM_READ0__DATA__SHIFT 0x0 ++#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL ++//GDS_ATOM_READ0_U ++#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 ++#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL ++//GDS_ATOM_READ1 ++#define GDS_ATOM_READ1__DATA__SHIFT 0x0 ++#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL ++//GDS_ATOM_READ1_U ++#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 ++#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL ++//GDS_GWS_RESOURCE_CNTL ++#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 ++#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 ++#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL ++#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L ++//GDS_GWS_RESOURCE ++#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 ++#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 ++#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd ++#define GDS_GWS_RESOURCE__DED__SHIFT 0xe ++#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf ++#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 ++#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c ++#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d ++#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e ++#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f ++#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L ++#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL ++#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L ++#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L ++#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L ++#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L ++#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L ++#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L ++#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L ++#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L ++//GDS_GWS_RESOURCE_CNT ++#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 ++#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 ++#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL ++#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L ++//GDS_OA_CNTL ++#define GDS_OA_CNTL__INDEX__SHIFT 0x0 ++#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 ++#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL ++#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L ++//GDS_OA_COUNTER ++#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 ++#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL ++//GDS_OA_ADDRESS ++#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 ++#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 ++#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 ++#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 ++#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e ++#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f ++#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL ++#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L ++#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L ++#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L ++#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L ++#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L ++//GDS_OA_INCDEC ++#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 ++#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f ++#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL ++#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L ++//GDS_OA_RING_SIZE ++#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 ++#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL ++//SPI_CONFIG_CNTL ++#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 ++#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 ++#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 ++#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 ++#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a ++#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b ++#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c ++#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d ++#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e ++#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL ++#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L ++#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L ++#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L ++#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L ++#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L ++#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L ++#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L ++#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L ++//SPI_CONFIG_CNTL_1 ++#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 ++#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 ++#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 ++#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 ++#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 ++#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 ++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 ++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa ++#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe ++#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf ++#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 ++#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL ++#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L ++#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L ++#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L ++#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L ++#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L ++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L ++#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L ++#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L ++#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L ++#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L ++//SPI_CONFIG_CNTL_2 ++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 ++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 ++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL ++#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L ++//SPI_WAVE_LIMIT_CNTL ++#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 ++#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2 ++#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 ++#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 ++#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L ++#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL ++#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L ++#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L ++ ++ ++// addressBlock: gc_perfddec ++//CPG_PERFCOUNTER1_LO ++#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CPG_PERFCOUNTER1_HI ++#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CPG_PERFCOUNTER0_LO ++#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CPG_PERFCOUNTER0_HI ++#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CPC_PERFCOUNTER1_LO ++#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CPC_PERFCOUNTER1_HI ++#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CPC_PERFCOUNTER0_LO ++#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CPC_PERFCOUNTER0_HI ++#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CPF_PERFCOUNTER1_LO ++#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CPF_PERFCOUNTER1_HI ++#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CPF_PERFCOUNTER0_LO ++#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CPF_PERFCOUNTER0_HI ++#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CPF_LATENCY_STATS_DATA ++#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 ++#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL ++//CPG_LATENCY_STATS_DATA ++#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 ++#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL ++//CPC_LATENCY_STATS_DATA ++#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 ++#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL ++//GRBM_PERFCOUNTER0_LO ++#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GRBM_PERFCOUNTER0_HI ++#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GRBM_PERFCOUNTER1_LO ++#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GRBM_PERFCOUNTER1_HI ++#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GRBM_SE0_PERFCOUNTER_LO ++#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GRBM_SE0_PERFCOUNTER_HI ++#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GRBM_SE1_PERFCOUNTER_LO ++#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GRBM_SE1_PERFCOUNTER_HI ++#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GRBM_SE2_PERFCOUNTER_LO ++#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GRBM_SE2_PERFCOUNTER_HI ++#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GRBM_SE3_PERFCOUNTER_LO ++#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GRBM_SE3_PERFCOUNTER_HI ++#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER0_LO ++#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER0_HI ++#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER1_LO ++#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER1_HI ++#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER2_LO ++#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER2_HI ++#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER3_LO ++#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//WD_PERFCOUNTER3_HI ++#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER0_LO ++#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER0_HI ++#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER1_LO ++#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER1_HI ++#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER2_LO ++#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER2_HI ++#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER3_LO ++#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//IA_PERFCOUNTER3_HI ++#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER0_LO ++#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER0_HI ++#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER1_LO ++#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER1_HI ++#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER2_LO ++#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER2_HI ++#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER3_LO ++#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//VGT_PERFCOUNTER3_HI ++#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SU_PERFCOUNTER0_LO ++#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SU_PERFCOUNTER0_HI ++#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL ++//PA_SU_PERFCOUNTER1_LO ++#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SU_PERFCOUNTER1_HI ++#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL ++//PA_SU_PERFCOUNTER2_LO ++#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SU_PERFCOUNTER2_HI ++#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL ++//PA_SU_PERFCOUNTER3_LO ++#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SU_PERFCOUNTER3_HI ++#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL ++//PA_SC_PERFCOUNTER0_LO ++#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER0_HI ++#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER1_LO ++#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER1_HI ++#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER2_LO ++#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER2_HI ++#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER3_LO ++#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER3_HI ++#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER4_LO ++#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER4_HI ++#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER5_LO ++#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER5_HI ++#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER6_LO ++#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER6_HI ++#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER7_LO ++#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//PA_SC_PERFCOUNTER7_HI ++#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER0_HI ++#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER0_LO ++#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER1_HI ++#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER1_LO ++#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER2_HI ++#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER2_LO ++#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER3_HI ++#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER3_LO ++#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER4_HI ++#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER4_LO ++#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER5_HI ++#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SPI_PERFCOUNTER5_LO ++#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER0_LO ++#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER0_HI ++#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER1_LO ++#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER1_HI ++#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER2_LO ++#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER2_HI ++#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER3_LO ++#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER3_HI ++#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER4_LO ++#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER4_HI ++#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER5_LO ++#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER5_HI ++#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER6_LO ++#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER6_HI ++#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER7_LO ++#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER7_HI ++#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER8_LO ++#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER8_HI ++#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER9_LO ++#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER9_HI ++#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER10_LO ++#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER10_HI ++#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER11_LO ++#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER11_HI ++#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER12_LO ++#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER12_HI ++#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER13_LO ++#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER13_HI ++#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER14_LO ++#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER14_HI ++#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER15_LO ++#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SQ_PERFCOUNTER15_HI ++#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER0_LO ++#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER0_HI ++#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER1_LO ++#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER1_HI ++#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER2_LO ++#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER2_HI ++#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER3_LO ++#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//SX_PERFCOUNTER3_HI ++#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER0_LO ++#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER0_HI ++#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER1_LO ++#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER1_HI ++#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER2_LO ++#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER2_HI ++#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER3_LO ++#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//GDS_PERFCOUNTER3_HI ++#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TA_PERFCOUNTER0_LO ++#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TA_PERFCOUNTER0_HI ++#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TA_PERFCOUNTER1_LO ++#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TA_PERFCOUNTER1_HI ++#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TD_PERFCOUNTER0_LO ++#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TD_PERFCOUNTER0_HI ++#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TD_PERFCOUNTER1_LO ++#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TD_PERFCOUNTER1_HI ++#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER0_LO ++#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER0_HI ++#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER1_LO ++#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER1_HI ++#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER2_LO ++#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER2_HI ++#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER3_LO ++#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCP_PERFCOUNTER3_HI ++#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER0_LO ++#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER0_HI ++#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER1_LO ++#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER1_HI ++#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER2_LO ++#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER2_HI ++#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER3_LO ++#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCC_PERFCOUNTER3_HI ++#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER0_LO ++#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER0_HI ++#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER1_LO ++#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER1_HI ++#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER2_LO ++#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER2_HI ++#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER3_LO ++#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//TCA_PERFCOUNTER3_HI ++#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER0_LO ++#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER0_HI ++#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER1_LO ++#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER1_HI ++#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER2_LO ++#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER2_HI ++#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER3_LO ++#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//CB_PERFCOUNTER3_HI ++#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER0_LO ++#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER0_HI ++#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER1_LO ++#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER1_HI ++#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER2_LO ++#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER2_HI ++#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER3_LO ++#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//DB_PERFCOUNTER3_HI ++#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//RLC_PERFCOUNTER0_LO ++#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//RLC_PERFCOUNTER0_HI ++#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//RLC_PERFCOUNTER1_LO ++#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//RLC_PERFCOUNTER1_HI ++#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER0_LO ++#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER0_HI ++#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER1_LO ++#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER1_HI ++#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER2_LO ++#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER2_HI ++#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER3_LO ++#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 ++#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL ++//RMI_PERFCOUNTER3_HI ++#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 ++#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gc_utcl2_atcl2pfcntrdec ++//ATC_L2_PERFCOUNTER_LO ++#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//ATC_L2_PERFCOUNTER_HI ++#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: gc_utcl2_vml2prdec ++//MC_VM_L2_PERFCOUNTER_LO ++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MC_VM_L2_PERFCOUNTER_HI ++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: gc_perfsdec ++//CPG_PERFCOUNTER1_SELECT ++#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 ++#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa ++#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 ++#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 ++#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c ++#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL ++#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L ++#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L ++#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L ++#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L ++//CPG_PERFCOUNTER0_SELECT1 ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L ++#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L ++//CPG_PERFCOUNTER0_SELECT ++#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 ++#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa ++#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 ++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 ++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c ++#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL ++#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L ++#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L ++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L ++#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L ++//CPC_PERFCOUNTER1_SELECT ++#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 ++#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa ++#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 ++#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 ++#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c ++#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL ++#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L ++#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L ++#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L ++#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L ++//CPC_PERFCOUNTER0_SELECT1 ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L ++#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L ++//CPF_PERFCOUNTER1_SELECT ++#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 ++#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa ++#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 ++#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 ++#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c ++#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL ++#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L ++#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L ++#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L ++#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L ++//CPF_PERFCOUNTER0_SELECT1 ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L ++#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L ++//CPF_PERFCOUNTER0_SELECT ++#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 ++#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa ++#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 ++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 ++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c ++#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL ++#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L ++#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L ++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L ++#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L ++//CP_PERFMON_CNTL ++#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 ++#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 ++#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 ++#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa ++#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL ++#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L ++#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L ++#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L ++//CPC_PERFCOUNTER0_SELECT ++#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 ++#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa ++#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 ++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 ++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c ++#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL ++#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L ++#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L ++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L ++#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L ++//CPF_TC_PERF_COUNTER_WINDOW_SELECT ++#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 ++#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e ++#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f ++#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L ++#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L ++#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L ++//CPG_TC_PERF_COUNTER_WINDOW_SELECT ++#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 ++#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e ++#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f ++#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL ++#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L ++#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L ++//CPF_LATENCY_STATS_SELECT ++#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 ++#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e ++#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f ++#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL ++#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L ++#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L ++//CPG_LATENCY_STATS_SELECT ++#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 ++#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e ++#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f ++#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL ++#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L ++#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L ++//CPC_LATENCY_STATS_SELECT ++#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 ++#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e ++#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f ++#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L ++#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L ++#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L ++//CP_DRAW_OBJECT ++#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 ++#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL ++//CP_DRAW_OBJECT_COUNTER ++#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 ++#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL ++//CP_DRAW_WINDOW_MASK_HI ++#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 ++#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL ++//CP_DRAW_WINDOW_HI ++#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 ++#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL ++//CP_DRAW_WINDOW_LO ++#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 ++#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 ++#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL ++#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L ++//CP_DRAW_WINDOW_CNTL ++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 ++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 ++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 ++#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 ++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L ++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L ++#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L ++#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L ++//GRBM_PERFCOUNTER0_SELECT ++#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa ++#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb ++#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc ++#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd ++#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe ++#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 ++#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 ++#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 ++#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 ++#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 ++#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 ++#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 ++#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 ++#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 ++#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 ++#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a ++#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b ++#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c ++#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d ++#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e ++#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f ++#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL ++#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L ++#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L ++#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L ++#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L ++#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L ++#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L ++#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L ++#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L ++#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L ++#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L ++#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L ++#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L ++#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L ++#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L ++#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L ++#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L ++#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L ++#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L ++#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L ++#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L ++#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L ++//GRBM_PERFCOUNTER1_SELECT ++#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa ++#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb ++#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc ++#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd ++#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe ++#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 ++#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 ++#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 ++#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 ++#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 ++#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 ++#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 ++#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 ++#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 ++#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 ++#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a ++#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b ++#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c ++#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d ++#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e ++#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f ++#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL ++#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L ++#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L ++#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L ++#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L ++#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L ++#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L ++#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L ++#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L ++#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L ++#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L ++#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L ++#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L ++#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L ++#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L ++#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L ++#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L ++#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L ++#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L ++#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L ++#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L ++#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L ++//GRBM_SE0_PERFCOUNTER_SELECT ++#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 ++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa ++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb ++#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc ++#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd ++#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf ++#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 ++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 ++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 ++#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 ++#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 ++#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 ++#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 ++#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL ++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L ++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L ++#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L ++#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L ++//GRBM_SE1_PERFCOUNTER_SELECT ++#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 ++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa ++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb ++#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc ++#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd ++#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf ++#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 ++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 ++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 ++#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 ++#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 ++#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 ++#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 ++#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL ++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L ++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L ++#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L ++#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L ++//GRBM_SE2_PERFCOUNTER_SELECT ++#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 ++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa ++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb ++#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc ++#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd ++#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf ++#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 ++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 ++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 ++#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 ++#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 ++#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 ++#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 ++#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL ++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L ++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L ++#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L ++#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L ++//GRBM_SE3_PERFCOUNTER_SELECT ++#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 ++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa ++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb ++#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc ++#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd ++#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf ++#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 ++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 ++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 ++#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 ++#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 ++#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 ++#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 ++#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL ++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L ++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L ++#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L ++#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L ++//WD_PERFCOUNTER0_SELECT ++#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL ++#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//WD_PERFCOUNTER1_SELECT ++#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL ++#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//WD_PERFCOUNTER2_SELECT ++#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL ++#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//WD_PERFCOUNTER3_SELECT ++#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL ++#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//IA_PERFCOUNTER0_SELECT ++#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//IA_PERFCOUNTER1_SELECT ++#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL ++#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//IA_PERFCOUNTER2_SELECT ++#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL ++#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//IA_PERFCOUNTER3_SELECT ++#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL ++#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//IA_PERFCOUNTER0_SELECT1 ++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//VGT_PERFCOUNTER0_SELECT ++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//VGT_PERFCOUNTER1_SELECT ++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//VGT_PERFCOUNTER2_SELECT ++#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL ++#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//VGT_PERFCOUNTER3_SELECT ++#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL ++#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//VGT_PERFCOUNTER0_SELECT1 ++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//VGT_PERFCOUNTER1_SELECT1 ++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//VGT_PERFCOUNTER_SEID_MASK ++#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 ++#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL ++//PA_SU_PERFCOUNTER0_SELECT ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//PA_SU_PERFCOUNTER0_SELECT1 ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//PA_SU_PERFCOUNTER1_SELECT ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//PA_SU_PERFCOUNTER1_SELECT1 ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//PA_SU_PERFCOUNTER2_SELECT ++#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//PA_SU_PERFCOUNTER3_SELECT ++#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//PA_SC_PERFCOUNTER0_SELECT ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//PA_SC_PERFCOUNTER0_SELECT1 ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//PA_SC_PERFCOUNTER1_SELECT ++#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++//PA_SC_PERFCOUNTER2_SELECT ++#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++//PA_SC_PERFCOUNTER3_SELECT ++#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++//PA_SC_PERFCOUNTER4_SELECT ++#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL ++//PA_SC_PERFCOUNTER5_SELECT ++#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL ++//PA_SC_PERFCOUNTER6_SELECT ++#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL ++//PA_SC_PERFCOUNTER7_SELECT ++#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 ++#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL ++//SPI_PERFCOUNTER0_SELECT ++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//SPI_PERFCOUNTER1_SELECT ++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//SPI_PERFCOUNTER2_SELECT ++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa ++#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 ++#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//SPI_PERFCOUNTER3_SELECT ++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa ++#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 ++#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//SPI_PERFCOUNTER0_SELECT1 ++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//SPI_PERFCOUNTER1_SELECT1 ++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//SPI_PERFCOUNTER2_SELECT1 ++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa ++#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//SPI_PERFCOUNTER3_SELECT1 ++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa ++#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//SPI_PERFCOUNTER4_SELECT ++#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 ++#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL ++//SPI_PERFCOUNTER5_SELECT ++#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 ++#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL ++//SPI_PERFCOUNTER_BINS ++#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 ++#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 ++#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 ++#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc ++#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 ++#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 ++#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 ++#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c ++#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL ++#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L ++#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L ++#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L ++#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L ++#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L ++#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L ++#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L ++//SQ_PERFCOUNTER0_SELECT ++#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER1_SELECT ++#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER2_SELECT ++#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER3_SELECT ++#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER4_SELECT ++#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER5_SELECT ++#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER6_SELECT ++#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER7_SELECT ++#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER8_SELECT ++#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER9_SELECT ++#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER10_SELECT ++#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER11_SELECT ++#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER12_SELECT ++#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER13_SELECT ++#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER14_SELECT ++#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER15_SELECT ++#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 ++#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc ++#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 ++#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 ++#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c ++#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL ++#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L ++#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L ++#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L ++#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L ++#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L ++//SQ_PERFCOUNTER_CTRL ++#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 ++#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 ++#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 ++#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 ++#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 ++#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 ++#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 ++#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 ++#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd ++#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L ++#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L ++#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L ++#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L ++#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L ++#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L ++#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L ++#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L ++#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L ++//SQ_PERFCOUNTER_MASK ++#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 ++#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 ++#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL ++#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L ++//SQ_PERFCOUNTER_CTRL2 ++#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 ++#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L ++//SX_PERFCOUNTER0_SELECT ++#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//SX_PERFCOUNTER1_SELECT ++#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//SX_PERFCOUNTER2_SELECT ++#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//SX_PERFCOUNTER3_SELECT ++#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//SX_PERFCOUNTER0_SELECT1 ++#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//SX_PERFCOUNTER1_SELECT1 ++#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//GDS_PERFCOUNTER0_SELECT ++#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//GDS_PERFCOUNTER1_SELECT ++#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//GDS_PERFCOUNTER2_SELECT ++#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa ++#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 ++#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//GDS_PERFCOUNTER3_SELECT ++#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa ++#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 ++#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//GDS_PERFCOUNTER0_SELECT1 ++#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//TA_PERFCOUNTER0_SELECT ++#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL ++#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L ++#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//TA_PERFCOUNTER0_SELECT1 ++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL ++#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L ++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//TA_PERFCOUNTER1_SELECT ++#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL ++#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//TD_PERFCOUNTER0_SELECT ++#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL ++#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L ++#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//TD_PERFCOUNTER0_SELECT1 ++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL ++#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L ++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//TD_PERFCOUNTER1_SELECT ++#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL ++#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCP_PERFCOUNTER0_SELECT ++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCP_PERFCOUNTER0_SELECT1 ++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//TCP_PERFCOUNTER1_SELECT ++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCP_PERFCOUNTER1_SELECT1 ++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//TCP_PERFCOUNTER2_SELECT ++#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCP_PERFCOUNTER3_SELECT ++#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCC_PERFCOUNTER0_SELECT ++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCC_PERFCOUNTER0_SELECT1 ++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 ++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c ++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L ++#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L ++//TCC_PERFCOUNTER1_SELECT ++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCC_PERFCOUNTER1_SELECT1 ++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 ++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c ++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L ++#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L ++//TCC_PERFCOUNTER2_SELECT ++#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCC_PERFCOUNTER3_SELECT ++#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCA_PERFCOUNTER0_SELECT ++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCA_PERFCOUNTER0_SELECT1 ++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 ++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c ++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L ++#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L ++//TCA_PERFCOUNTER1_SELECT ++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCA_PERFCOUNTER1_SELECT1 ++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 ++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c ++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L ++#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L ++//TCA_PERFCOUNTER2_SELECT ++#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//TCA_PERFCOUNTER3_SELECT ++#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//CB_PERFCOUNTER_FILTER ++#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 ++#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 ++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 ++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 ++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa ++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb ++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc ++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd ++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 ++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 ++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 ++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 ++#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L ++#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL ++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L ++#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L ++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L ++#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L ++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L ++#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L ++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L ++#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L ++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L ++#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L ++//CB_PERFCOUNTER0_SELECT ++#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL ++#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L ++#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//CB_PERFCOUNTER0_SELECT1 ++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL ++#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L ++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//CB_PERFCOUNTER1_SELECT ++#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL ++#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//CB_PERFCOUNTER2_SELECT ++#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL ++#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//CB_PERFCOUNTER3_SELECT ++#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL ++#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//DB_PERFCOUNTER0_SELECT ++#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL ++#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//DB_PERFCOUNTER0_SELECT1 ++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//DB_PERFCOUNTER1_SELECT ++#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa ++#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 ++#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 ++#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL ++#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//DB_PERFCOUNTER1_SELECT1 ++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa ++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL ++#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L ++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//DB_PERFCOUNTER2_SELECT ++#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa ++#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 ++#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL ++#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//DB_PERFCOUNTER3_SELECT ++#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa ++#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 ++#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 ++#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL ++#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L ++#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//RLC_SPM_PERFMON_CNTL ++#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 ++#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc ++#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe ++#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 ++#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL ++#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L ++#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L ++#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L ++//RLC_SPM_PERFMON_RING_BASE_LO ++#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 ++#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL ++//RLC_SPM_PERFMON_RING_BASE_HI ++#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 ++#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 ++#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL ++#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L ++//RLC_SPM_PERFMON_RING_SIZE ++#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 ++#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL ++//RLC_SPM_PERFMON_SEGMENT_SIZE ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L ++#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L ++//RLC_SPM_SE_MUXSEL_ADDR ++#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 ++#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL ++//RLC_SPM_SE_MUXSEL_DATA ++#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 ++#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL ++//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_CB_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_DB_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_PA_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_IA_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_SC_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_TA_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_TD_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_SX_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_GLOBAL_MUXSEL_ADDR ++#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 ++#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL ++//RLC_SPM_GLOBAL_MUXSEL_DATA ++#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 ++#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL ++//RLC_SPM_RING_RDPTR ++#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 ++#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL ++//RLC_SPM_SEGMENT_THRESHOLD ++#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 ++#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL ++//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY ++#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 ++#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L ++//RLC_SPM_PERFMON_SAMPLE_DELAY_MAX ++#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT 0x0 ++#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT 0x8 ++#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK 0x000000FFL ++#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK 0xFFFFFF00L ++//RLC_PERFMON_CLK_CNTL_UCODE ++#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 ++#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L ++//RLC_PERFMON_CLK_CNTL ++#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 ++#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L ++//RLC_PERFMON_CNTL ++#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 ++#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa ++#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L ++#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L ++//RLC_PERFCOUNTER0_SELECT ++#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 ++#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL ++//RLC_PERFCOUNTER1_SELECT ++#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 ++#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL ++//RLC_GPU_IOV_PERF_CNT_CNTL ++#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 ++#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 ++#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 ++#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 ++#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L ++#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L ++#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L ++#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L ++//RLC_GPU_IOV_PERF_CNT_WR_ADDR ++#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 ++#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 ++#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 ++#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL ++#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L ++#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L ++//RLC_GPU_IOV_PERF_CNT_WR_DATA ++#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 ++#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL ++//RLC_GPU_IOV_PERF_CNT_RD_ADDR ++#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 ++#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 ++#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 ++#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL ++#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L ++#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L ++//RLC_GPU_IOV_PERF_CNT_RD_DATA ++#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 ++#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL ++//RMI_PERFCOUNTER0_SELECT ++#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa ++#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 ++#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 ++#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c ++#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL ++#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L ++#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L ++//RMI_PERFCOUNTER0_SELECT1 ++#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa ++#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL ++#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L ++#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//RMI_PERFCOUNTER1_SELECT ++#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c ++#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL ++#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L ++//RMI_PERFCOUNTER2_SELECT ++#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 ++#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa ++#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 ++#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 ++#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c ++#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL ++#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L ++#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L ++#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L ++#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L ++//RMI_PERFCOUNTER2_SELECT1 ++#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 ++#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa ++#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 ++#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c ++#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL ++#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L ++#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L ++#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L ++//RMI_PERFCOUNTER3_SELECT ++#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 ++#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c ++#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL ++#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L ++//RMI_PERF_COUNTER_CNTL ++#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 ++#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 ++#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 ++#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 ++#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 ++#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa ++#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe ++#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 ++#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 ++#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a ++#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L ++#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL ++#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L ++#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L ++#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L ++#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L ++#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L ++#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L ++#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L ++#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L ++ ++ ++// addressBlock: gc_utcl2_atcl2pfcntldec ++//ATC_L2_PERFCOUNTER0_CFG ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//ATC_L2_PERFCOUNTER1_CFG ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//ATC_L2_PERFCOUNTER_RSLT_CNTL ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++ ++// addressBlock: gc_utcl2_vml2pldec ++//MC_VM_L2_PERFCOUNTER0_CFG ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER1_CFG ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER2_CFG ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER3_CFG ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER4_CFG ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER5_CFG ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER6_CFG ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER7_CFG ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER_RSLT_CNTL ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++ ++// addressBlock: gc_rlcpdec ++//RLC_CNTL ++#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 ++#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 ++#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 ++#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 ++#define RLC_CNTL__RESERVED__SHIFT 0x4 ++#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L ++#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L ++#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L ++#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L ++#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L ++//RLC_STAT ++#define RLC_STAT__RLC_BUSY__SHIFT 0x0 ++#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 ++#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 ++#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 ++#define RLC_STAT__MC_BUSY__SHIFT 0x4 ++#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 ++#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 ++#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 ++#define RLC_STAT__RESERVED__SHIFT 0x8 ++#define RLC_STAT__RLC_BUSY_MASK 0x00000001L ++#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L ++#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L ++#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L ++#define RLC_STAT__MC_BUSY_MASK 0x00000010L ++#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L ++#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L ++#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L ++#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L ++//RLC_SAFE_MODE ++#define RLC_SAFE_MODE__CMD__SHIFT 0x0 ++#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 ++#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 ++#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 ++#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc ++#define RLC_SAFE_MODE__CMD_MASK 0x00000001L ++#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL ++#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L ++#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L ++#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L ++//RLC_MEM_SLP_CNTL ++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 ++#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 ++#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 ++#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 ++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 ++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 ++#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 ++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L ++#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L ++#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL ++#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L ++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L ++#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L ++#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L ++//SMU_RLC_RESPONSE ++#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 ++#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL ++//RLC_RLCV_SAFE_MODE ++#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 ++#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 ++#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 ++#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 ++#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc ++#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L ++#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL ++#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L ++#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L ++#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L ++//RLC_SMU_SAFE_MODE ++#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 ++#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 ++#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 ++#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 ++#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc ++#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L ++#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL ++#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L ++#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L ++#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L ++//RLC_RLCV_COMMAND ++#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 ++#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 ++#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL ++#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L ++//RLC_REFCLOCK_TIMESTAMP_LSB ++#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 ++#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL ++//RLC_REFCLOCK_TIMESTAMP_MSB ++#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 ++#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL ++//RLC_GPM_TIMER_INT_0 ++#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 ++#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL ++//RLC_GPM_TIMER_INT_1 ++#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 ++#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL ++//RLC_GPM_TIMER_INT_2 ++#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 ++#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL ++//RLC_GPM_TIMER_CTRL ++#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 ++#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 ++#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 ++#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 ++#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 ++#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L ++#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L ++#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L ++#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L ++#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L ++//RLC_LB_CNTR_MAX ++#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 ++#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL ++//RLC_GPM_TIMER_STAT ++#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 ++#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 ++#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 ++#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 ++#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 ++#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 ++#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa ++#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb ++#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0xc ++#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L ++#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L ++#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L ++#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L ++#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L ++#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L ++#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L ++#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L ++#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFF000L ++//RLC_GPM_TIMER_INT_3 ++#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 ++#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL ++//RLC_SERDES_WR_NONCU_MASTER_MASK_1 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L ++//RLC_SERDES_NONCU_MASTER_BUSY_1 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L ++#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L ++//RLC_INT_STAT ++#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 ++#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 ++#define RLC_INT_STAT__RESERVED__SHIFT 0x9 ++#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL ++#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L ++#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L ++//RLC_LB_CNTL ++#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 ++#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 ++#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 ++#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 ++#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 ++#define RLC_LB_CNTL__RESERVED__SHIFT 0xc ++#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L ++#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L ++#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L ++#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L ++#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L ++#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L ++//RLC_MGCG_CTRL ++#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 ++#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 ++#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 ++#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 ++#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 ++#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf ++#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 ++#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 ++#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L ++#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L ++#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L ++#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L ++#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L ++#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L ++#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L ++#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L ++//RLC_LB_CNTR_INIT ++#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 ++#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL ++//RLC_LOAD_BALANCE_CNTR ++#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 ++#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL ++//RLC_JUMP_TABLE_RESTORE ++#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 ++#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL ++//RLC_PG_DELAY_2 ++#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 ++#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 ++#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 ++#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL ++#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L ++#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L ++//RLC_GPU_CLOCK_COUNT_LSB ++#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 ++#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL ++//RLC_GPU_CLOCK_COUNT_MSB ++#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 ++#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL ++//RLC_CAPTURE_GPU_CLOCK_COUNT ++#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L ++#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL ++//RLC_UCODE_CNTL ++#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 ++#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL ++//RLC_GPM_THREAD_RESET ++#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 ++#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 ++#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 ++#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 ++#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 ++#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L ++#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L ++#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L ++#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L ++#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L ++//RLC_GPM_CP_DMA_COMPLETE_T0 ++#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 ++#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 ++#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L ++#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL ++//RLC_GPM_CP_DMA_COMPLETE_T1 ++#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 ++#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 ++#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L ++#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL ++//RLC_FIREWALL_VIOLATION ++#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0 ++#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL ++//RLC_CLK_COUNT_GFXCLK_LSB ++#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 ++#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL ++//RLC_CLK_COUNT_GFXCLK_MSB ++#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 ++#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL ++//RLC_CLK_COUNT_REFCLK_LSB ++#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 ++#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL ++//RLC_CLK_COUNT_REFCLK_MSB ++#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 ++#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL ++//RLC_CLK_COUNT_CTRL ++#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 ++#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 ++#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 ++#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 ++#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 ++#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 ++#define RLC_CLK_COUNT_CTRL__RESERVED__SHIFT 0x6 ++#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L ++#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L ++#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L ++#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L ++#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L ++#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L ++#define RLC_CLK_COUNT_CTRL__RESERVED_MASK 0xFFFFFFC0L ++//RLC_CLK_COUNT_STAT ++#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 ++#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 ++#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 ++#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 ++#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 ++#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 ++#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L ++#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L ++#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L ++#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L ++#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L ++#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L ++//RLC_GPM_STAT ++#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 ++#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 ++#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 ++#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 ++#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 ++#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 ++#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 ++#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 ++#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 ++#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 ++#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa ++#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb ++#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc ++#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd ++#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe ++#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf ++#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 ++#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 ++#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 ++#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 ++#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 ++#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 ++#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 ++#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 ++#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 ++#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L ++#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L ++#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L ++#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L ++#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L ++#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L ++#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L ++#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L ++#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L ++#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L ++#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L ++#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L ++#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L ++#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L ++#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L ++#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L ++#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L ++#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L ++#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L ++#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L ++#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L ++#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L ++#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L ++#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L ++#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L ++//RLC_GPU_CLOCK_32_RES_SEL ++#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 ++#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 ++#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL ++#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L ++//RLC_GPU_CLOCK_32 ++#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 ++#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL ++//RLC_PG_CNTL ++#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 ++#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 ++#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 ++#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 ++#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 ++#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 ++#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe ++#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf ++#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 ++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 ++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 ++#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 ++#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 ++#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 ++#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 ++#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L ++#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L ++#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L ++#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L ++#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L ++#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L ++#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L ++#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L ++#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L ++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L ++#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L ++#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L ++#define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L ++#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L ++#define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L ++//RLC_GPM_THREAD_PRIORITY ++#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 ++#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 ++#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 ++#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 ++#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL ++#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L ++#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L ++#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L ++//RLC_GPM_THREAD_ENABLE ++#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 ++#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 ++#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 ++#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 ++#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 ++#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L ++#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L ++#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L ++#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L ++#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L ++//RLC_CGTT_MGCG_OVERRIDE ++#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0 ++#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 ++#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 ++#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9__SHIFT 0x9 ++#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10 ++#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11 ++#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L ++#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L ++#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L ++#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L ++#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9_MASK 0x0000FE00L ++#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L ++#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L ++//RLC_CGCG_CGLS_CTRL ++#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 ++#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 ++#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 ++#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 ++#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b ++#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c ++#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d ++#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f ++#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L ++#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L ++#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL ++#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L ++#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L ++#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L ++#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L ++#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L ++//RLC_CGCG_RAMP_CTRL ++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 ++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 ++#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 ++#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc ++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 ++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c ++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL ++#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L ++#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L ++#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L ++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L ++#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L ++//RLC_DYN_PG_STATUS ++#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 ++#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL ++//RLC_DYN_PG_REQUEST ++#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 ++#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL ++//RLC_PG_DELAY ++#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 ++#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 ++#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 ++#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 ++#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL ++#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L ++#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L ++#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L ++//RLC_CU_STATUS ++#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 ++#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL ++//RLC_LB_INIT_CU_MASK ++#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 ++#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL ++//RLC_LB_ALWAYS_ACTIVE_CU_MASK ++#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 ++#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL ++//RLC_LB_PARAMS ++#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 ++#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 ++#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 ++#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 ++#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L ++#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL ++#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L ++#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L ++//RLC_THREAD1_DELAY ++#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 ++#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 ++#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 ++#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 ++#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL ++#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L ++#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L ++#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L ++//RLC_PG_ALWAYS_ON_CU_MASK ++#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 ++#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL ++//RLC_MAX_PG_CU ++#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 ++#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 ++#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL ++#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L ++//RLC_AUTO_PG_CTRL ++#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 ++#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 ++#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 ++#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 ++#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 ++#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L ++#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L ++#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L ++#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L ++#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L ++//RLC_SMU_GRBM_REG_SAVE_CTRL ++#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 ++#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 ++#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L ++#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL ++//RLC_SERDES_RD_PENDING ++#define RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT 0x0 ++#define RLC_SERDES_RD_PENDING__RD_PENDING_MASK 0x00000001L ++//RLC_SERDES_RD_MASTER_INDEX ++#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 ++#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 ++#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 ++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 ++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc ++#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd ++#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 ++#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 ++#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL ++#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L ++#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L ++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L ++#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L ++#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L ++#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L ++#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L ++//RLC_SERDES_RD_DATA_0 ++#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 ++#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL ++//RLC_SERDES_RD_DATA_1 ++#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 ++#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL ++//RLC_SERDES_RD_DATA_2 ++#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 ++#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL ++//RLC_SERDES_WR_CU_MASTER_MASK ++#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 ++#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL ++//RLC_SERDES_WR_NONCU_MASTER_MASK ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L ++#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L ++//RLC_SERDES_WR_CTRL ++#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 ++#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 ++#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 ++#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa ++#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb ++#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc ++#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd ++#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe ++#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf ++#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 ++#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a ++#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b ++#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c ++#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL ++#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L ++#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L ++#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L ++#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L ++#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L ++#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L ++#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L ++#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L ++#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L ++#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L ++#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L ++#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L ++//RLC_SERDES_WR_DATA ++#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 ++#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL ++//RLC_SERDES_CU_MASTER_BUSY ++#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 ++#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL ++//RLC_SERDES_NONCU_MASTER_BUSY ++#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 ++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 ++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 ++#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 ++#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 ++#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 ++#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 ++#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a ++#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL ++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L ++#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L ++//RLC_GPM_GENERAL_0 ++#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_1 ++#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_2 ++#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_3 ++#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_4 ++#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_5 ++#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_6 ++#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_7 ++#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_SCRATCH_ADDR ++#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 ++#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 ++#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL ++#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L ++//RLC_GPM_SCRATCH_DATA ++#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 ++#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL ++//RLC_STATIC_PG_STATUS ++#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 ++#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL ++//RLC_SPM_MC_CNTL ++#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 ++#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 ++#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 ++#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 ++#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 ++#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 ++#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa ++#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL ++#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L ++#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L ++#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L ++#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L ++#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L ++#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L ++//RLC_SPM_INT_CNTL ++#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 ++#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 ++#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L ++#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL ++//RLC_SPM_INT_STATUS ++#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 ++#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 ++#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L ++#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL ++//RLC_SMU_MESSAGE ++#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 ++#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL ++//RLC_GPM_LOG_SIZE ++#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 ++#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL ++//RLC_PG_DELAY_3 ++#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 ++#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 ++#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL ++#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L ++//RLC_GPR_REG1 ++#define RLC_GPR_REG1__DATA__SHIFT 0x0 ++#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL ++//RLC_GPR_REG2 ++#define RLC_GPR_REG2__DATA__SHIFT 0x0 ++#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_LOG_CONT ++#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 ++#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL ++//RLC_GPM_INT_DISABLE_TH0 ++#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 ++#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL ++//RLC_GPM_INT_FORCE_TH0 ++#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 ++#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL ++//RLC_GPM_INT_FORCE_TH1 ++#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 ++#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL ++//RLC_SRM_CNTL ++#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 ++#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 ++#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 ++#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L ++#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L ++#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL ++//RLC_SRM_ARAM_ADDR ++#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 ++#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc ++#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL ++#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L ++//RLC_SRM_ARAM_DATA ++#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 ++#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_DRAM_ADDR ++#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 ++#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc ++#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL ++#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L ++//RLC_SRM_DRAM_DATA ++#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 ++#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_GPM_COMMAND ++#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 ++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 ++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 ++#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 ++#define RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT 0x10 ++#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 ++#define RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT 0x1d ++#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f ++#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L ++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L ++#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL ++#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0000FFE0L ++#define RLC_SRM_GPM_COMMAND__RESERVED_16_MASK 0x00010000L ++#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L ++#define RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK 0x60000000L ++#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L ++//RLC_SRM_GPM_COMMAND_STATUS ++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 ++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 ++#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 ++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L ++#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L ++#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL ++//RLC_SRM_RLCV_COMMAND ++#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 ++#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 ++#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 ++#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 ++#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c ++#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f ++#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L ++#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL ++#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L ++#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L ++#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L ++#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L ++//RLC_SRM_RLCV_COMMAND_STATUS ++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 ++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 ++#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 ++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L ++#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L ++#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL ++//RLC_SRM_INDEX_CNTL_ADDR_0 ++#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_ADDR_1 ++#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_ADDR_2 ++#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_ADDR_3 ++#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_ADDR_4 ++#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_ADDR_5 ++#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_ADDR_6 ++#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_ADDR_7 ++#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 ++#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL ++#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L ++//RLC_SRM_INDEX_CNTL_DATA_0 ++#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_INDEX_CNTL_DATA_1 ++#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_INDEX_CNTL_DATA_2 ++#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_INDEX_CNTL_DATA_3 ++#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_INDEX_CNTL_DATA_4 ++#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_INDEX_CNTL_DATA_5 ++#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_INDEX_CNTL_DATA_6 ++#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_INDEX_CNTL_DATA_7 ++#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 ++#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL ++//RLC_SRM_STAT ++#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 ++#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 ++#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 ++#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L ++#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L ++#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL ++//RLC_SRM_GPM_ABORT ++#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 ++#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 ++#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L ++#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL ++//RLC_CSIB_ADDR_LO ++#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 ++#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL ++//RLC_CSIB_ADDR_HI ++#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 ++#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL ++//RLC_CSIB_LENGTH ++#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 ++#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL ++//RLC_SMU_COMMAND ++#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 ++#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL ++//RLC_CP_SCHEDULERS ++#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 ++#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 ++#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 ++#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 ++#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL ++#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L ++#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L ++#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L ++//RLC_SMU_ARGUMENT_1 ++#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 ++#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL ++//RLC_SMU_ARGUMENT_2 ++#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 ++#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_8 ++#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_9 ++#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_10 ++#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_11 ++#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_12 ++#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_UTCL1_CNTL_0 ++#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 ++#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 ++#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a ++#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c ++#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e ++#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L ++#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L ++#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L ++#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L ++#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L ++//RLC_GPM_UTCL1_CNTL_1 ++#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 ++#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 ++#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a ++#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c ++#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e ++#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L ++#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L ++#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L ++#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L ++#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L ++//RLC_GPM_UTCL1_CNTL_2 ++#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 ++#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 ++#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a ++#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c ++#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e ++#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L ++#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L ++#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L ++#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L ++#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L ++//RLC_SPM_UTCL1_CNTL ++#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 ++#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 ++#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a ++#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c ++#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e ++#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L ++#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L ++#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L ++#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L ++#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L ++//RLC_UTCL1_STATUS_2 ++#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 ++#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 ++#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 ++#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 ++#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 ++#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 ++#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 ++#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 ++#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 ++#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 ++#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa ++#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L ++#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L ++#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L ++#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L ++#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L ++#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L ++#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L ++#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L ++#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L ++#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L ++#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L ++//RLC_LB_THR_CONFIG_2 ++#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 ++#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL ++//RLC_LB_THR_CONFIG_3 ++#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 ++#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL ++//RLC_LB_THR_CONFIG_4 ++#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 ++#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL ++//RLC_SPM_UTCL1_ERROR_1 ++#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 ++#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 ++#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 ++#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L ++#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL ++#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L ++//RLC_SPM_UTCL1_ERROR_2 ++#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 ++#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL ++//RLC_GPM_UTCL1_TH0_ERROR_1 ++#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 ++#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 ++#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 ++#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L ++#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL ++#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L ++//RLC_LB_THR_CONFIG_1 ++#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 ++#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_UTCL1_TH0_ERROR_2 ++#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 ++#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL ++//RLC_GPM_UTCL1_TH1_ERROR_1 ++#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 ++#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 ++#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 ++#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L ++#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL ++#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L ++//RLC_GPM_UTCL1_TH1_ERROR_2 ++#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 ++#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL ++//RLC_GPM_UTCL1_TH2_ERROR_1 ++#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 ++#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 ++#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 ++#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L ++#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL ++#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L ++//RLC_GPM_UTCL1_TH2_ERROR_2 ++#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 ++#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL ++//RLC_CGCG_CGLS_CTRL_3D ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 ++#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 ++#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c ++#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d ++#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L ++#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L ++#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L ++#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L ++#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L ++#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L ++//RLC_CGCG_RAMP_CTRL_3D ++#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 ++#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 ++#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 ++#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc ++#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 ++#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c ++#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL ++#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L ++#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L ++#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L ++#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L ++#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L ++//RLC_SEMAPHORE_0 ++#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 ++#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 ++#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL ++#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L ++//RLC_SEMAPHORE_1 ++#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 ++#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 ++#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL ++#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L ++//RLC_CP_EOF_INT ++#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 ++#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 ++#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L ++#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL ++//RLC_CP_EOF_INT_CNT ++#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 ++#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL ++//RLC_SPARE_INT ++#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 ++#define RLC_SPARE_INT__RESERVED__SHIFT 0x1 ++#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L ++#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL ++//RLC_PREWALKER_UTCL1_CNTL ++#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 ++#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 ++#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 ++#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a ++#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b ++#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c ++#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d ++#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e ++#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL ++#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L ++#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L ++#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L ++#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L ++#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L ++#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L ++#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L ++//RLC_PREWALKER_UTCL1_TRIG ++#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 ++#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 ++#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 ++#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 ++#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 ++#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 ++#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 ++#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f ++#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L ++#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL ++#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L ++#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L ++#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L ++#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L ++#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L ++#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L ++//RLC_PREWALKER_UTCL1_ADDR_LSB ++#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 ++#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL ++//RLC_PREWALKER_UTCL1_ADDR_MSB ++#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 ++#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL ++//RLC_PREWALKER_UTCL1_SIZE_LSB ++#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 ++#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL ++//RLC_PREWALKER_UTCL1_SIZE_MSB ++#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 ++#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L ++//RLC_DSM_TRIG ++#define RLC_DSM_TRIG__START__SHIFT 0x0 ++#define RLC_DSM_TRIG__START_MASK 0x00000001L ++//RLC_UTCL1_STATUS ++#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 ++#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 ++#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 ++#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 ++#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 ++#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe ++#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 ++#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 ++#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 ++#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e ++#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L ++#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L ++#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L ++#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L ++#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L ++#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L ++#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L ++#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L ++#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L ++#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L ++//RLC_R2I_CNTL_0 ++#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 ++#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL ++//RLC_R2I_CNTL_1 ++#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 ++#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL ++//RLC_R2I_CNTL_2 ++#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 ++#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL ++//RLC_R2I_CNTL_3 ++#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 ++#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL ++//RLC_UTCL2_CNTL ++#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 ++#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1 ++#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L ++#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL ++//RLC_LBPW_CU_STAT ++#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 ++#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 ++#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL ++#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L ++//RLC_DS_CNTL ++#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 ++#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 ++#define RLC_DS_CNTL__RESRVED__SHIFT 0x2 ++#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 ++#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 ++#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 ++#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L ++#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L ++#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL ++#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L ++#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L ++#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L ++//RLC_GPM_INT_STAT_TH0 ++#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 ++#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_13 ++#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_14 ++#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL ++//RLC_GPM_GENERAL_15 ++#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 ++#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL ++//RLC_SPARE_INT_1 ++#define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0 ++#define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1 ++#define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L ++#define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL ++//RLC_RLCV_SPARE_INT_1 ++#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 ++#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 ++#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L ++#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL ++//RLC_SEMAPHORE_2 ++#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 ++#define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 ++#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL ++#define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L ++//RLC_SEMAPHORE_3 ++#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 ++#define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 ++#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL ++#define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L ++//RLC_SMU_ARGUMENT_3 ++#define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 ++#define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL ++//RLC_SMU_ARGUMENT_4 ++#define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 ++#define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL ++//RLC_GPU_CLOCK_COUNT_LSB_1 ++#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 ++#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL ++//RLC_GPU_CLOCK_COUNT_MSB_1 ++#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 ++#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL ++//RLC_CAPTURE_GPU_CLOCK_COUNT_1 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL ++//RLC_GPU_CLOCK_COUNT_LSB_2 ++#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 ++#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL ++//RLC_GPU_CLOCK_COUNT_MSB_2 ++#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 ++#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL ++//RLC_CAPTURE_GPU_CLOCK_COUNT_2 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L ++#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL ++//RLC_CPG_STAT_INVAL ++#define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0 ++#define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L ++//RLC_RLCV_SPARE_INT ++#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 ++#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 ++#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L ++#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL ++//RLC_SMU_CLK_REQ ++#define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 ++#define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L ++ ++ ++// addressBlock: gc_pwrdec ++//CGTS_SM_CTRL_REG ++#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 ++#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 ++#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc ++#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 ++#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 ++#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 ++#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 ++#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 ++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 ++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 ++#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL ++#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L ++#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L ++#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L ++#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L ++#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L ++#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L ++#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L ++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L ++#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L ++//CGTS_RD_CTRL_REG ++#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 ++#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 ++#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL ++#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L ++//CGTS_RD_REG ++#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 ++#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL ++//CGTS_TCC_DISABLE ++#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 ++#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L ++//CGTS_USER_TCC_DISABLE ++#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 ++#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L ++//CGTS_CU0_SP0_CTRL_REG ++#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU0_LDS_SQ_CTRL_REG ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU0_TA_SQC_CTRL_REG ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU0_SP1_CTRL_REG ++#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU0_TD_TCP_CTRL_REG ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU1_SP0_CTRL_REG ++#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU1_LDS_SQ_CTRL_REG ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU1_TA_SQC_CTRL_REG ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU1_SP1_CTRL_REG ++#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU1_TD_TCP_CTRL_REG ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU2_SP0_CTRL_REG ++#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU2_LDS_SQ_CTRL_REG ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU2_TA_SQC_CTRL_REG ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU2_SP1_CTRL_REG ++#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU2_TD_TCP_CTRL_REG ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU3_SP0_CTRL_REG ++#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU3_LDS_SQ_CTRL_REG ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU3_TA_SQC_CTRL_REG ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU3_SP1_CTRL_REG ++#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU3_TD_TCP_CTRL_REG ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU4_SP0_CTRL_REG ++#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU4_LDS_SQ_CTRL_REG ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU4_TA_SQC_CTRL_REG ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU4_SP1_CTRL_REG ++#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU4_TD_TCP_CTRL_REG ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU5_SP0_CTRL_REG ++#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU5_LDS_SQ_CTRL_REG ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU5_TA_SQC_CTRL_REG ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU5_SP1_CTRL_REG ++#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU5_TD_TCP_CTRL_REG ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU6_SP0_CTRL_REG ++#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU6_LDS_SQ_CTRL_REG ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU6_TA_SQC_CTRL_REG ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU6_SP1_CTRL_REG ++#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU6_TD_TCP_CTRL_REG ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU7_SP0_CTRL_REG ++#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU7_LDS_SQ_CTRL_REG ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU7_TA_SQC_CTRL_REG ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU7_SP1_CTRL_REG ++#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU7_TD_TCP_CTRL_REG ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU8_SP0_CTRL_REG ++#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU8_LDS_SQ_CTRL_REG ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU8_TA_SQC_CTRL_REG ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU8_SP1_CTRL_REG ++#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU8_TD_TCP_CTRL_REG ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU9_SP0_CTRL_REG ++#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU9_LDS_SQ_CTRL_REG ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU9_TA_SQC_CTRL_REG ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU9_SP1_CTRL_REG ++#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU9_TD_TCP_CTRL_REG ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU10_SP0_CTRL_REG ++#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU10_LDS_SQ_CTRL_REG ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU10_TA_SQC_CTRL_REG ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU10_SP1_CTRL_REG ++#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU10_TD_TCP_CTRL_REG ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU11_SP0_CTRL_REG ++#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU11_LDS_SQ_CTRL_REG ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU11_TA_SQC_CTRL_REG ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU11_SP1_CTRL_REG ++#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU11_TD_TCP_CTRL_REG ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU12_SP0_CTRL_REG ++#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU12_LDS_SQ_CTRL_REG ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU12_TA_SQC_CTRL_REG ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU12_SP1_CTRL_REG ++#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU12_TD_TCP_CTRL_REG ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU13_SP0_CTRL_REG ++#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU13_LDS_SQ_CTRL_REG ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU13_TA_SQC_CTRL_REG ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU13_SP1_CTRL_REG ++#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU13_TD_TCP_CTRL_REG ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU14_SP0_CTRL_REG ++#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU14_LDS_SQ_CTRL_REG ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU14_TA_SQC_CTRL_REG ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++//CGTS_CU14_SP1_CTRL_REG ++#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU14_TD_TCP_CTRL_REG ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU15_SP0_CTRL_REG ++#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 ++#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 ++#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL ++#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L ++#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU15_LDS_SQ_CTRL_REG ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU15_TA_SQC_CTRL_REG ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU15_SP1_CTRL_REG ++#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 ++#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 ++#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL ++#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L ++#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU15_TD_TCP_CTRL_REG ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L ++#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L ++//CGTS_CU0_TCPI_CTRL_REG ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU1_TCPI_CTRL_REG ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU2_TCPI_CTRL_REG ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU3_TCPI_CTRL_REG ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU4_TCPI_CTRL_REG ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU5_TCPI_CTRL_REG ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU6_TCPI_CTRL_REG ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU7_TCPI_CTRL_REG ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU8_TCPI_CTRL_REG ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU9_TCPI_CTRL_REG ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU10_TCPI_CTRL_REG ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU11_TCPI_CTRL_REG ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU12_TCPI_CTRL_REG ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU13_TCPI_CTRL_REG ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU14_TCPI_CTRL_REG ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTS_CU15_TCPI_CTRL_REG ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb ++#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L ++#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L ++#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L ++//CGTT_SPI_PS_CLK_CTRL ++#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 ++#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 ++#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 ++#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a ++#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b ++#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c ++#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d ++#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e ++#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L ++#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L ++#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L ++#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L ++#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L ++#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L ++#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L ++#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L ++#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L ++#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_SPIS_CLK_CTRL ++#define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 ++#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 ++#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 ++#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a ++#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b ++#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c ++#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d ++#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e ++#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L ++#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L ++#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L ++#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L ++#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L ++#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L ++#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L ++#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L ++#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L ++#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTX_SPI_DEBUG_CLK_CTRL ++#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x0 ++#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x6 ++#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x7 ++#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL__SHIFT 0x8 ++#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x0000003FL ++#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x00000040L ++#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x00000080L ++#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL_MASK 0x00000100L ++//CGTT_SPI_CLK_CTRL ++#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 ++#define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 ++#define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 ++#define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a ++#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b ++#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c ++#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d ++#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e ++#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L ++#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L ++#define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L ++#define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L ++#define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L ++#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L ++#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L ++#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L ++#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L ++#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_PC_CLK_CTRL ++#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11 ++#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 ++#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 ++#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 ++#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a ++#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b ++#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c ++#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d ++#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e ++#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L ++#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L ++#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L ++#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L ++#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L ++#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L ++#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L ++#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L ++#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L ++#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_BCI_CLK_CTRL ++#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 ++#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 ++#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a ++#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b ++#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c ++#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d ++#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e ++#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L ++#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L ++#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L ++#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L ++#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L ++#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L ++#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L ++#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_VGT_CLK_CTRL ++#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18 ++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 ++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a ++#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b ++#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c ++#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d ++#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e ++#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L ++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L ++#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L ++#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L ++#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L ++#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L ++#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L ++#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_IA_CLK_CTRL ++#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e ++#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L ++#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_WD_CLK_CTRL ++#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 ++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a ++#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b ++#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c ++#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d ++#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e ++#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L ++#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L ++#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L ++#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L ++#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L ++#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L ++#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_PA_CLK_CTRL ++#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d ++#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e ++#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f ++#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L ++#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L ++#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L ++//CGTT_SC_CLK_CTRL0 ++#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 ++#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 ++#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 ++#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e ++#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f ++#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L ++#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L ++#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L ++#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L ++#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L ++#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L ++//CGTT_SC_CLK_CTRL1 ++#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 ++#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 ++#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 ++#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 ++#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 ++#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 ++#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 ++#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 ++#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a ++#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b ++#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c ++#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d ++#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e ++#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L ++#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L ++#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L ++#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L ++#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L ++#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L ++#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L ++#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L ++#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L ++#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L ++#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L ++#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L ++//CGTT_SC_CLK_CTRL2 ++#define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 ++#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b ++#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c ++#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d ++#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e ++#define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L ++#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L ++#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L ++#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L ++//CGTT_SQ_CLK_CTRL ++#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d ++#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e ++#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L ++#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L ++#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//CGTT_SQG_CLK_CTRL ++#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c ++#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d ++#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e ++#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f ++#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L ++#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L ++#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L ++#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L ++//SQ_ALU_CLK_CTRL ++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 ++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 ++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL ++#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L ++//SQ_TEX_CLK_CTRL ++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 ++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 ++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL ++#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L ++//SQ_LDS_CLK_CTRL ++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 ++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 ++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL ++#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L ++//SQ_POWER_THROTTLE ++#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 ++#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 ++#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e ++#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL ++#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L ++#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L ++//SQ_POWER_THROTTLE2 ++#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 ++#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 ++#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b ++#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f ++#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL ++#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L ++#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L ++#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L ++//CGTT_SX_CLK_CTRL0 ++#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 ++#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_SX_CLK_CTRL1 ++#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 ++#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_SX_CLK_CTRL2 ++#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 ++#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_SX_CLK_CTRL3 ++#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 ++#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_SX_CLK_CTRL4 ++#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 ++#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL ++#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L ++//TD_CGTT_CTRL ++#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 ++#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL ++#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//TA_CGTT_CTRL ++#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 ++#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL ++#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_TCPI_CLK_CTRL ++#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_TCI_CLK_CTRL ++#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_GDS_CLK_CTRL ++#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//DB_CGTT_CLK_CTRL_0 ++#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 ++#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 ++#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f ++#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL ++#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L ++#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L ++//CB_CGTT_SCLK_CTRL ++#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//TCC_CGTT_SCLK_CTRL ++#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//TCA_CGTT_SCLK_CTRL ++#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_CP_CLK_CTRL ++#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d ++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e ++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f ++#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L ++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L ++#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L ++//CGTT_CPF_CLK_CTRL ++#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d ++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e ++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f ++#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L ++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L ++#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L ++//CGTT_CPC_CLK_CTRL ++#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d ++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e ++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f ++#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L ++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L ++#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L ++//CGTT_RLC_CLK_CTRL ++#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e ++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f ++#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L ++#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L ++//RLC_GFX_RM_CNTL ++#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 ++#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 ++#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L ++#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL ++//RMI_CGTT_SCLK_CTRL ++#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//CGTT_TCPF_CLK_CTRL ++#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//SE_CAC_CGTT_CLK_CTRL ++#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e ++#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f ++#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L ++#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L ++//GC_CAC_CGTT_CLK_CTRL ++#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e ++#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f ++#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L ++#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L ++//GRBM_CGTT_CLK_CNTL ++#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 ++#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 ++#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e ++#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL ++#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L ++#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L ++ ++ ++// addressBlock: gc_ea_pwrdec ++//GCEA_CGTT_CLK_CTRL ++#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 ++#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e ++#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f ++#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L ++#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L ++#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L ++ ++ ++// addressBlock: gc_utcl2_vmsharedhvdec ++//MC_VM_FB_SIZE_OFFSET_VF0 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF1 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF2 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF3 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF4 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF5 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF6 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF7 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF8 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF9 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF10 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF11 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF12 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF13 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF14 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF15 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L ++//VM_IOMMU_MMIO_CNTRL_1 ++#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 ++#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L ++//MC_VM_MARC_BASE_LO_0 ++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_LO_1 ++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_LO_2 ++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_LO_3 ++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_HI_0 ++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL ++//MC_VM_MARC_BASE_HI_1 ++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL ++//MC_VM_MARC_BASE_HI_2 ++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL ++//MC_VM_MARC_BASE_HI_3 ++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_LO_0 ++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_LO_1 ++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_LO_2 ++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_LO_3 ++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_HI_0 ++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_HI_1 ++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_HI_2 ++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_HI_3 ++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_LO_0 ++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_LO_1 ++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_LO_2 ++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_LO_3 ++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_HI_0 ++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_HI_1 ++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_HI_2 ++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_HI_3 ++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL ++//VM_IOMMU_CONTROL_REGISTER ++#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 ++#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L ++//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER ++#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd ++#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L ++//VM_PCIE_ATS_CNTL ++#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 ++#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L ++#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_0 ++#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_1 ++#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_2 ++#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_3 ++#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_4 ++#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_5 ++#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_6 ++#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_7 ++#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_8 ++#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_9 ++#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_10 ++#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_11 ++#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_12 ++#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_13 ++#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_14 ++#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_15 ++#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L ++//UTCL2_CGTT_CLK_CTRL ++#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc ++#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L ++#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++//MC_SHARED_ACTIVE_FCN_ID ++#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//MC_VM_XGMI_GPUIOV_ENABLE ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L ++ ++ ++// addressBlock: gc_hypdec ++//CP_HYP_PFP_UCODE_ADDR ++#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL ++//CP_PFP_UCODE_ADDR ++#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL ++//CP_HYP_PFP_UCODE_DATA ++#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_PFP_UCODE_DATA ++#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_HYP_ME_UCODE_ADDR ++#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL ++//CP_ME_RAM_RADDR ++#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 ++#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL ++//CP_ME_RAM_WADDR ++#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 ++#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL ++//CP_HYP_ME_UCODE_DATA ++#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_ME_RAM_DATA ++#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 ++#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL ++//CP_CE_UCODE_ADDR ++#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL ++//CP_HYP_CE_UCODE_ADDR ++#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL ++//CP_CE_UCODE_DATA ++#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_HYP_CE_UCODE_DATA ++#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_HYP_MEC1_UCODE_ADDR ++#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL ++//CP_MEC_ME1_UCODE_ADDR ++#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL ++//CP_HYP_MEC1_UCODE_DATA ++#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_MEC_ME1_UCODE_DATA ++#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_HYP_MEC2_UCODE_ADDR ++#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL ++//CP_MEC_ME2_UCODE_ADDR ++#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL ++//CP_HYP_MEC2_UCODE_DATA ++#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_MEC_ME2_UCODE_DATA ++#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//CP_HYP_PFP_UCODE_CHKSUM ++#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 ++#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL ++//CP_HYP_CE_UCODE_CHKSUM ++#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 ++#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL ++//CP_HYP_ME_UCODE_CHKSUM ++#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 ++#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL ++//CP_HYP_MEC_ME1_UCODE_CHKSUM ++#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 ++#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL ++//CP_HYP_MEC_ME2_UCODE_CHKSUM ++#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 ++#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL ++//RLC_GPM_UCODE_ADDR ++#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe ++#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL ++#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L ++//RLC_GPM_UCODE_DATA ++#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//GRBM_GFX_INDEX_SR_SELECT ++#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 ++#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L ++//GRBM_GFX_INDEX_SR_DATA ++#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 ++#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 ++#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 ++#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d ++#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e ++#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f ++#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL ++#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L ++#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L ++#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L ++#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L ++#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L ++//GRBM_GFX_CNTL_SR_SELECT ++#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 ++#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L ++//GRBM_GFX_CNTL_SR_DATA ++#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 ++#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 ++#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 ++#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 ++#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L ++#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL ++#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L ++#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L ++//GRBM_CAM_INDEX ++#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 ++#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L ++//GRBM_HYP_CAM_INDEX ++#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 ++#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L ++//GRBM_CAM_DATA ++#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 ++#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 ++#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL ++#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L ++//GRBM_HYP_CAM_DATA ++#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 ++#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 ++#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL ++#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L ++//RLC_GPU_IOV_VF_ENABLE ++#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 ++#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 ++#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 ++#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L ++#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL ++#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L ++//RLC_GPU_IOV_CFG_REG6 ++#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 ++#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 ++#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 ++#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa ++#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL ++#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L ++#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L ++#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L ++//RLC_GPU_IOV_CFG_REG8 ++#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 ++#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL ++//RLC_RLCV_TIMER_INT_0 ++#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 ++#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL ++//RLC_RLCV_TIMER_CTRL ++#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 ++#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 ++#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x2 ++#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L ++#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L ++#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFCL ++//RLC_RLCV_TIMER_STAT ++#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 ++#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 ++#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 ++#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 ++#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 ++#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L ++#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L ++#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL ++#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L ++#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L ++//RLC_GPU_IOV_VF_DOORBELL_STATUS ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L ++//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L ++//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L ++#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L ++//RLC_GPU_IOV_VF_MASK ++#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 ++#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 ++#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL ++#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L ++//RLC_HYP_SEMAPHORE_0 ++#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 ++#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 ++#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL ++#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L ++//RLC_HYP_SEMAPHORE_1 ++#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 ++#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 ++#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL ++#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L ++//RLC_CLK_CNTL ++#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 ++#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2 ++#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4 ++#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5 ++#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6 ++#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0x7 ++#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 ++#define RLC_CLK_CNTL__RESERVED__SHIFT 0x9 ++#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L ++#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL ++#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L ++#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L ++#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L ++#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000080L ++#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L ++#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFE00L ++//RLC_GPU_IOV_SCH_BLOCK ++#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 ++#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 ++#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 ++#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 ++#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL ++#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L ++#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L ++#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L ++//RLC_GPU_IOV_CFG_REG1 ++#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 ++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 ++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 ++#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 ++#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 ++#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 ++#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 ++#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL ++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L ++#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L ++#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L ++#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L ++#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L ++#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L ++//RLC_GPU_IOV_CFG_REG2 ++#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 ++#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 ++#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL ++#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L ++//RLC_GPU_IOV_VM_BUSY_STATUS ++#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 ++#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_SCH_0 ++#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 ++#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_ACTIVE_FCN_ID ++#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 ++#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 ++#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f ++#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL ++#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L ++#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L ++//RLC_GPU_IOV_SCH_3 ++#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 ++#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_SCH_1 ++#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 ++#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_SCH_2 ++#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 ++#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_INT_STAT ++#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 ++#define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL ++//RLC_RLCV_TIMER_INT_1 ++#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 ++#define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_UCODE_ADDR ++#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 ++#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc ++#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL ++#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L ++//RLC_GPU_IOV_UCODE_DATA ++#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 ++#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_SCRATCH_ADDR ++#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 ++#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 ++#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL ++#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L ++//RLC_GPU_IOV_SCRATCH_DATA ++#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 ++#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_F32_CNTL ++#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 ++#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 ++#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L ++#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL ++//RLC_GPU_IOV_F32_RESET ++#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 ++#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 ++#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L ++#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL ++//RLC_GPU_IOV_SDMA0_STATUS ++#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 ++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 ++#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 ++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 ++#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc ++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd ++#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L ++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL ++#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L ++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L ++#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L ++#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L ++//RLC_GPU_IOV_SDMA1_STATUS ++#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 ++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 ++#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 ++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 ++#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc ++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd ++#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L ++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL ++#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L ++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L ++#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L ++#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L ++//RLC_GPU_IOV_SMU_RESPONSE ++#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 ++#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_VIRT_RESET_REQ ++#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 ++#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 ++#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f ++#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL ++#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L ++#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L ++//RLC_GPU_IOV_RLC_RESPONSE ++#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 ++#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_INT_DISABLE ++#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 ++#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_INT_FORCE ++#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 ++#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_SDMA0_BUSY_STATUS ++#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 ++#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL ++//RLC_GPU_IOV_SDMA1_BUSY_STATUS ++#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 ++#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL ++//RLC_HYP_SEMAPHORE_2 ++#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 ++#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 ++#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL ++#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L ++//RLC_HYP_SEMAPHORE_3 ++#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 ++#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 ++#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL ++#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L ++ ++ ++// addressBlock: gccacind ++//GC_CAC_CNTL ++#define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 ++#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 ++#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 ++#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 ++#define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L ++#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL ++#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L ++#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L ++//GC_CAC_OVR_SEL ++#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 ++#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL ++//GC_CAC_OVR_VAL ++#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 ++#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL ++//GC_CAC_WEIGHT_BCI_0 ++#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_CB_0 ++#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_CB_1 ++#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_CP_0 ++#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_CP_1 ++#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_DB_0 ++#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_DB_1 ++#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_GDS_0 ++#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_GDS_1 ++#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_IA_0 ++#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_LDS_0 ++#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_LDS_1 ++#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_PA_0 ++#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_PC_0 ++#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_SC_0 ++#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_SPI_0 ++#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_SPI_1 ++#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_SPI_2 ++#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 ++#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_SQ_0 ++#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_SQ_1 ++#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_SQ_2 ++#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 ++#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_SQ_3 ++#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 ++#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_SQ_4 ++#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_SX_0 ++#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_SXRB_0 ++#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_TA_0 ++#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_TCC_0 ++#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_TCC_1 ++#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_TCC_2 ++#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_TCP_0 ++#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_TCP_1 ++#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_TCP_2 ++#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_TD_0 ++#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_TD_1 ++#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_TD_2 ++#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 ++#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_VGT_0 ++#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_VGT_1 ++#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_WD_0 ++#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_CU_0 ++#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL ++//GC_CAC_ACC_BCI0 ++#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CB0 ++#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CB1 ++#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CB2 ++#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CB3 ++#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CP0 ++#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CP1 ++#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CP2 ++#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_DB0 ++#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_DB1 ++#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_DB2 ++#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_DB3 ++#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_GDS0 ++#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_GDS1 ++#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_GDS2 ++#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_GDS3 ++#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_IA0 ++#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_LDS0 ++#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_LDS1 ++#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_LDS2 ++#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_LDS3 ++#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_PA0 ++#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_PA1 ++#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_PC0 ++#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SC0 ++#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SPI0 ++#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SPI1 ++#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SPI2 ++#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SPI3 ++#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SPI4 ++#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SPI5 ++#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_WEIGHT_UTCL2_ATCL2_0 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L ++//GC_CAC_ACC_EA0 ++#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_EA1 ++#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_EA2 ++#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_EA3 ++#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ATCL20 ++#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_OVRD_EA ++#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 ++#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL ++#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L ++//GC_CAC_OVRD_UTCL2_ATCL2 ++#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 ++#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL ++#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L ++//GC_CAC_WEIGHT_EA_0 ++#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_EA_1 ++#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_RMI_0 ++#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL ++//GC_CAC_ACC_RMI0 ++#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_OVRD_RMI ++#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_WEIGHT_UTCL2_ATCL2_1 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L ++//GC_CAC_ACC_UTCL2_ATCL21 ++#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ATCL22 ++#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ATCL23 ++#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_EA4 ++#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_EA5 ++#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_WEIGHT_EA_2 ++#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 ++#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L ++//GC_CAC_ACC_SQ0_LOWER ++#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ0_UPPER ++#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ1_LOWER ++#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ1_UPPER ++#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ2_LOWER ++#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ2_UPPER ++#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ3_LOWER ++#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ3_UPPER ++#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ4_LOWER ++#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ4_UPPER ++#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ5_LOWER ++#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ5_UPPER ++#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ6_LOWER ++#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ6_UPPER ++#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ7_LOWER ++#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ7_UPPER ++#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SQ8_LOWER ++#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SQ8_UPPER ++#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 ++#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL ++//GC_CAC_ACC_SX0 ++#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SXRB0 ++#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_SXRB1 ++#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TA0 ++#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCC0 ++#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCC1 ++#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCC2 ++#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCC3 ++#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCC4 ++#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCP0 ++#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCP1 ++#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCP2 ++#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCP3 ++#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TCP4 ++#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TD0 ++#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TD1 ++#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TD2 ++#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TD3 ++#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TD4 ++#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_TD5 ++#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_VGT0 ++#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_VGT1 ++#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_VGT2 ++#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_WD0 ++#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CU0 ++#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CU1 ++#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CU2 ++#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CU3 ++#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_CU4 ++#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_OVRD_BCI ++#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 ++#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L ++#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL ++//GC_CAC_OVRD_CB ++#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 ++#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL ++#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L ++//GC_CAC_OVRD_CP ++#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 ++#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L ++#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L ++//GC_CAC_OVRD_DB ++#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 ++#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL ++#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L ++//GC_CAC_OVRD_GDS ++#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 ++#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL ++#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L ++//GC_CAC_OVRD_IA ++#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_OVRD_LDS ++#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 ++#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL ++#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L ++//GC_CAC_OVRD_PA ++#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 ++#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L ++#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL ++//GC_CAC_OVRD_PC ++#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_OVRD_SC ++#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_OVRD_SPI ++#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 ++#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL ++#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L ++//GC_CAC_OVRD_CU ++#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_OVRD_SQ ++#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9 ++#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL ++#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L ++//GC_CAC_OVRD_SX ++#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_OVRD_SXRB ++#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_OVRD_TA ++#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_OVRD_TCC ++#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5 ++#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL ++#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L ++//GC_CAC_OVRD_TCP ++#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 ++#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL ++#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L ++//GC_CAC_OVRD_TD ++#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6 ++#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL ++#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L ++//GC_CAC_OVRD_VGT ++#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3 ++#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L ++#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L ++//GC_CAC_OVRD_WD ++#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1 ++#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L ++#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L ++//GC_CAC_ACC_BCI1 ++#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_WEIGHT_UTCL2_ATCL2_2 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL ++//GC_CAC_WEIGHT_UTCL2_ROUTER_0 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_ROUTER_1 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_ROUTER_2 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_ROUTER_3 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_ROUTER_4 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_VML2_0 ++#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_VML2_1 ++#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_VML2_2 ++#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL ++//GC_CAC_ACC_UTCL2_ATCL24 ++#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER0 ++#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER1 ++#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER2 ++#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER3 ++#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER4 ++#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER5 ++#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER6 ++#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER7 ++#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER8 ++#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_ROUTER9 ++#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_VML20 ++#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_VML21 ++#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_VML22 ++#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_VML23 ++#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_VML24 ++#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_OVRD_UTCL2_ROUTER ++#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa ++#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL ++#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L ++//GC_CAC_OVRD_UTCL2_VML2 ++#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 ++#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL ++#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L ++//GC_CAC_WEIGHT_UTCL2_WALKER_0 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_WALKER_1 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL ++#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L ++//GC_CAC_WEIGHT_UTCL2_WALKER_2 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 ++#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL ++//GC_CAC_ACC_UTCL2_WALKER0 ++#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_WALKER1 ++#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_WALKER2 ++#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_WALKER3 ++#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_ACC_UTCL2_WALKER4 ++#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 ++#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL ++//GC_CAC_OVRD_UTCL2_WALKER ++#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 ++#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 ++#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL ++#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L ++//PCC_STALL_PATTERN_1_2 ++#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 ++#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 ++#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL ++#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L ++//PCC_STALL_PATTERN_3_4 ++#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 ++#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 ++#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL ++#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L ++//PCC_STALL_PATTERN_5_6 ++#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 ++#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 ++#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL ++#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L ++//PCC_STALL_PATTERN_7 ++#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 ++#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL ++//PCC_THROT_REINCR_FIRST_PATN_1_8 ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1__SHIFT 0x0 ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2__SHIFT 0x4 ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3__SHIFT 0x8 ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4__SHIFT 0xc ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5__SHIFT 0x10 ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6__SHIFT 0x14 ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7__SHIFT 0x18 ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8__SHIFT 0x1c ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1_MASK 0x00000007L ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2_MASK 0x00000070L ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3_MASK 0x00000700L ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4_MASK 0x00007000L ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5_MASK 0x00070000L ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6_MASK 0x00700000L ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7_MASK 0x07000000L ++#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8_MASK 0x70000000L ++//PCC_THROT_REINCR_FIRST_PATN_9_16 ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9__SHIFT 0x0 ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10__SHIFT 0x4 ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11__SHIFT 0x8 ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12__SHIFT 0xc ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13__SHIFT 0x10 ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14__SHIFT 0x14 ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15__SHIFT 0x18 ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16__SHIFT 0x1c ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9_MASK 0x00000007L ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10_MASK 0x00000070L ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11_MASK 0x00000700L ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12_MASK 0x00007000L ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13_MASK 0x00070000L ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14_MASK 0x00700000L ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15_MASK 0x07000000L ++#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16_MASK 0x70000000L ++//PCC_THROT_REINCR_FIRST_PATN_17_20 ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17__SHIFT 0x0 ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18__SHIFT 0x4 ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19__SHIFT 0x8 ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20__SHIFT 0xc ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17_MASK 0x00000007L ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18_MASK 0x00000070L ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19_MASK 0x00000700L ++#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20_MASK 0x00007000L ++//PCC_THROT_DECR_FIRST_PATN_1_4 ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1__SHIFT 0x0 ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2__SHIFT 0x8 ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3__SHIFT 0x10 ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4__SHIFT 0x18 ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1_MASK 0x0000001FL ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2_MASK 0x00001F00L ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3_MASK 0x001F0000L ++#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4_MASK 0x1F000000L ++//PCC_THROT_DECR_FIRST_PATN_5_7 ++#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5__SHIFT 0x0 ++#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6__SHIFT 0x8 ++#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7__SHIFT 0x10 ++#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5_MASK 0x0000001FL ++#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6_MASK 0x00001F00L ++#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7_MASK 0x001F0000L ++ ++ ++// addressBlock: secacind ++//SE_CAC_CNTL ++#define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 ++#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 ++#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 ++#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 ++#define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L ++#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL ++#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L ++#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L ++//SE_CAC_OVR_SEL ++#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 ++#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL ++//SE_CAC_OVR_VAL ++#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 ++#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: sqind ++//SQ_WAVE_MODE ++#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 ++#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 ++#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 ++#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 ++#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa ++#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb ++#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc ++#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 ++#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 ++#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 ++#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a ++#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b ++#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c ++#define SQ_WAVE_MODE__CSP__SHIFT 0x1d ++#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL ++#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L ++#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L ++#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L ++#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L ++#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L ++#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L ++#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L ++#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L ++#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L ++#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L ++#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L ++#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L ++#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L ++//SQ_WAVE_STATUS ++#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 ++#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 ++#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 ++#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 ++#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 ++#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 ++#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 ++#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 ++#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa ++#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb ++#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc ++#define SQ_WAVE_STATUS__HALT__SHIFT 0xd ++#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe ++#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf ++#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 ++#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 ++#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 ++#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 ++#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 ++#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 ++#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 ++#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 ++#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b ++#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L ++#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L ++#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L ++#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L ++#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L ++#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L ++#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L ++#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L ++#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L ++#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L ++#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L ++#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L ++#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L ++#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L ++#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L ++#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L ++#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L ++#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L ++#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L ++#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L ++#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L ++#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L ++#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L ++//SQ_WAVE_TRAPSTS ++#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 ++#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa ++#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb ++#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc ++#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 ++#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c ++#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d ++#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL ++#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L ++#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L ++#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L ++#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L ++#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L ++#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L ++//SQ_WAVE_HW_ID ++#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 ++#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 ++#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 ++#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 ++#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc ++#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd ++#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 ++#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 ++#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 ++#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b ++#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e ++#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL ++#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L ++#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L ++#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L ++#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L ++#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L ++#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L ++#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L ++#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L ++#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L ++#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L ++//SQ_WAVE_GPR_ALLOC ++#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 ++#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 ++#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 ++#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 ++#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL ++#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L ++#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L ++#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L ++//SQ_WAVE_LDS_ALLOC ++#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 ++#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc ++#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL ++#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L ++//SQ_WAVE_IB_STS ++#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 ++#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 ++#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 ++#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc ++#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf ++#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 ++#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 ++#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL ++#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L ++#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L ++#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L ++#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L ++#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L ++#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L ++//SQ_WAVE_PC_LO ++#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 ++#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL ++//SQ_WAVE_PC_HI ++#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 ++#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL ++//SQ_WAVE_INST_DW0 ++#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 ++#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL ++//SQ_WAVE_INST_DW1 ++#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 ++#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL ++//SQ_WAVE_IB_DBG0 ++#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 ++#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 ++#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 ++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 ++#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 ++#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa ++#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 ++#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 ++#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a ++#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b ++#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d ++#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e ++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f ++#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L ++#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L ++#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L ++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L ++#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L ++#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L ++#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L ++#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L ++#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L ++#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L ++#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L ++#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L ++#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L ++//SQ_WAVE_IB_DBG1 ++#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 ++#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 ++#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 ++#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 ++#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb ++#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 ++#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 ++#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L ++#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L ++#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L ++#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L ++#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L ++#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L ++#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L ++//SQ_WAVE_FLUSH_IB ++#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 ++#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP0 ++#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP1 ++#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP2 ++#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP3 ++#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP4 ++#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP5 ++#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP6 ++#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP7 ++#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP8 ++#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP9 ++#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP10 ++#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP11 ++#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP12 ++#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP13 ++#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP14 ++#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_TTMP15 ++#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 ++#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL ++//SQ_WAVE_M0 ++#define SQ_WAVE_M0__M0__SHIFT 0x0 ++#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL ++//SQ_WAVE_EXEC_LO ++#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 ++#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL ++//SQ_WAVE_EXEC_HI ++#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 ++#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL ++//SQ_INTERRUPT_WORD_AUTO_CTXID ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L ++#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L ++//SQ_INTERRUPT_WORD_AUTO_HI ++#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 ++#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa ++#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L ++#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L ++//SQ_INTERRUPT_WORD_AUTO_LO ++#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 ++#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 ++#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 ++#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 ++#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 ++#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 ++#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 ++#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 ++#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 ++#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L ++#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L ++#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L ++#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L ++#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L ++#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L ++#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L ++#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L ++#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L ++//SQ_INTERRUPT_WORD_CMN_CTXID ++#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 ++#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a ++#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L ++#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L ++//SQ_INTERRUPT_WORD_CMN_HI ++#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 ++#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa ++#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L ++#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L ++//SQ_INTERRUPT_WORD_WAVE_CTXID ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L ++#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L ++//SQ_INTERRUPT_WORD_WAVE_HI ++#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 ++#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 ++#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 ++#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa ++#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL ++#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L ++#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L ++#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L ++//SQ_INTERRUPT_WORD_WAVE_LO ++#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 ++#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 ++#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 ++#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a ++#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e ++#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL ++#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L ++#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L ++#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L ++#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L ++ ++ ++// addressBlock: didtind ++//DIDT_SQ_CTRL0 ++#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 ++#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 ++#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 ++#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 ++#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 ++#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 ++#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 ++#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 ++#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 ++#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 ++#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a ++#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b ++#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c ++#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L ++#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L ++#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L ++#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L ++#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L ++#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L ++#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L ++#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L ++#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L ++#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L ++#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L ++#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L ++#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L ++//DIDT_SQ_CTRL2 ++#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 ++#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 ++#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b ++#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL ++#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L ++#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L ++//DIDT_SQ_STALL_CTRL ++#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 ++#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 ++#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc ++#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 ++#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL ++#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L ++#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L ++#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L ++//DIDT_SQ_TUNING_CTRL ++#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 ++#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe ++#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL ++#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L ++//DIDT_SQ_STALL_AUTO_RELEASE_CTRL ++#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 ++#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL ++//DIDT_SQ_CTRL3 ++#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 ++#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 ++#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 ++#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 ++#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe ++#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 ++#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 ++#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 ++#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b ++#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c ++#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L ++#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L ++#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL ++#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L ++#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L ++#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L ++#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L ++#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L ++#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L ++#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L ++//DIDT_SQ_STALL_PATTERN_1_2 ++#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_SQ_STALL_PATTERN_3_4 ++#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_SQ_STALL_PATTERN_5_6 ++#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_SQ_STALL_PATTERN_7 ++#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_SQ_MPD_SCALE_FACTOR ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L ++#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L ++//DIDT_SQ_THROTTLE_CNTL0 ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL ++#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L ++//DIDT_SQ_THROTTLE_CNTL1 ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L ++#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L ++//DIDT_SQ_THROTTLE_CNTL_STATUS ++#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 ++#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L ++//DIDT_SQ_WEIGHT0_3 ++#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 ++#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 ++#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 ++#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 ++#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL ++#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L ++#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L ++#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L ++//DIDT_SQ_WEIGHT4_7 ++#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 ++#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 ++#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 ++#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 ++#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL ++#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L ++#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L ++#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L ++//DIDT_SQ_WEIGHT8_11 ++#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 ++#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 ++#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 ++#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 ++#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL ++#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L ++#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L ++#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L ++//DIDT_SQ_EDC_CTRL ++#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 ++#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 ++#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 ++#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 ++#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 ++#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 ++#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 ++#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 ++#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 ++#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 ++#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L ++#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L ++#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L ++#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L ++#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L ++#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L ++#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L ++#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L ++#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L ++#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L ++//DIDT_SQ_THROTTLE_CTRL ++#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 ++#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L ++//DIDT_SQ_EDC_STALL_PATTERN_1_2 ++#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_SQ_EDC_STALL_PATTERN_3_4 ++#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_SQ_EDC_STALL_PATTERN_5_6 ++#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_SQ_EDC_STALL_PATTERN_7 ++#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_SQ_EDC_STALL_DELAY_1 ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x7 ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xe ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x15 ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000007FL ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00003F80L ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x001FC000L ++#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x0FE00000L ++//DIDT_SQ_EDC_STALL_DELAY_2 ++#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 ++#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000007FL ++//DIDT_DB_CTRL0 ++#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 ++#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 ++#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 ++#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 ++#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 ++#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 ++#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 ++#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 ++#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 ++#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 ++#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a ++#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b ++#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c ++#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L ++#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L ++#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L ++#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L ++#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L ++#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L ++#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L ++#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L ++#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L ++#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L ++#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L ++#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L ++#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L ++//DIDT_DB_CTRL2 ++#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 ++#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 ++#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b ++#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL ++#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L ++#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L ++//DIDT_DB_STALL_CTRL ++#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 ++#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 ++#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc ++#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 ++#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL ++#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L ++#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L ++#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L ++//DIDT_DB_TUNING_CTRL ++#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 ++#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe ++#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL ++#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L ++//DIDT_DB_STALL_AUTO_RELEASE_CTRL ++#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 ++#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL ++//DIDT_DB_CTRL3 ++#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 ++#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 ++#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 ++#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 ++#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe ++#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 ++#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 ++#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 ++#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b ++#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c ++#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L ++#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L ++#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL ++#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L ++#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L ++#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L ++#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L ++#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L ++#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L ++#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L ++//DIDT_DB_STALL_PATTERN_1_2 ++#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_DB_STALL_PATTERN_3_4 ++#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_DB_STALL_PATTERN_5_6 ++#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_DB_STALL_PATTERN_7 ++#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_DB_MPD_SCALE_FACTOR ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L ++#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L ++//DIDT_DB_THROTTLE_CNTL0 ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL ++#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L ++//DIDT_DB_THROTTLE_CNTL1 ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L ++#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L ++//DIDT_DB_THROTTLE_CNTL_STATUS ++#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 ++#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L ++//DIDT_DB_WEIGHT0_3 ++#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 ++#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 ++#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 ++#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 ++#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL ++#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L ++#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L ++#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L ++//DIDT_DB_WEIGHT4_7 ++#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 ++#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 ++#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 ++#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 ++#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL ++#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L ++#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L ++#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L ++//DIDT_DB_WEIGHT8_11 ++#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 ++#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 ++#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 ++#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 ++#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL ++#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L ++#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L ++#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L ++//DIDT_DB_EDC_CTRL ++#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 ++#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 ++#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 ++#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 ++#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 ++#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 ++#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 ++#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 ++#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 ++#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 ++#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L ++#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L ++#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L ++#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L ++#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L ++#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L ++#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L ++#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L ++#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L ++#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L ++//DIDT_DB_THROTTLE_CTRL ++#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 ++#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L ++//DIDT_DB_EDC_STALL_PATTERN_1_2 ++#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_DB_EDC_STALL_PATTERN_3_4 ++#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_DB_EDC_STALL_PATTERN_5_6 ++#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_DB_EDC_STALL_PATTERN_7 ++#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_DB_EDC_STALL_DELAY_1 ++#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 ++#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x5 ++#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000001FL ++#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x000003E0L ++//DIDT_TD_CTRL0 ++#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 ++#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 ++#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 ++#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 ++#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 ++#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 ++#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 ++#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 ++#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 ++#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 ++#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a ++#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b ++#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c ++#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L ++#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L ++#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L ++#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L ++#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L ++#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L ++#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L ++#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L ++#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L ++#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L ++#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L ++#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L ++#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L ++//DIDT_TD_CTRL2 ++#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 ++#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 ++#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b ++#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL ++#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L ++#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L ++//DIDT_TD_STALL_CTRL ++#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 ++#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 ++#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc ++#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 ++#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL ++#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L ++#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L ++#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L ++//DIDT_TD_TUNING_CTRL ++#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 ++#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe ++#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL ++#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L ++//DIDT_TD_STALL_AUTO_RELEASE_CTRL ++#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 ++#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL ++//DIDT_TD_CTRL3 ++#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 ++#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 ++#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 ++#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 ++#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe ++#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 ++#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 ++#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 ++#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b ++#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c ++#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L ++#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L ++#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL ++#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L ++#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L ++#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L ++#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L ++#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L ++#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L ++#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L ++//DIDT_TD_STALL_PATTERN_1_2 ++#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_TD_STALL_PATTERN_3_4 ++#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_TD_STALL_PATTERN_5_6 ++#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_TD_STALL_PATTERN_7 ++#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_TD_MPD_SCALE_FACTOR ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L ++#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L ++//DIDT_TD_THROTTLE_CNTL0 ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL ++#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L ++//DIDT_TD_THROTTLE_CNTL1 ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L ++#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L ++//DIDT_TD_THROTTLE_CNTL_STATUS ++#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 ++#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L ++//DIDT_TD_WEIGHT0_3 ++#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 ++#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 ++#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 ++#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 ++#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL ++#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L ++#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L ++#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L ++//DIDT_TD_WEIGHT4_7 ++#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 ++#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 ++#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 ++#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 ++#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL ++#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L ++#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L ++#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L ++//DIDT_TD_WEIGHT8_11 ++#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 ++#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 ++#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 ++#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 ++#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL ++#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L ++#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L ++#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L ++//DIDT_TD_EDC_CTRL ++#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 ++#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 ++#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 ++#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 ++#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 ++#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 ++#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 ++#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 ++#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 ++#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 ++#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L ++#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L ++#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L ++#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L ++#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L ++#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L ++#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L ++#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L ++#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L ++#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L ++//DIDT_TD_THROTTLE_CTRL ++#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 ++#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L ++//DIDT_TD_EDC_STALL_PATTERN_1_2 ++#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_TD_EDC_STALL_PATTERN_3_4 ++#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_TD_EDC_STALL_PATTERN_5_6 ++#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_TD_EDC_STALL_PATTERN_7 ++#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_TD_EDC_STALL_DELAY_1 ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x7 ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xe ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x15 ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000007FL ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00003F80L ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x001FC000L ++#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x0FE00000L ++//DIDT_TD_EDC_STALL_DELAY_2 ++#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 ++#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000007FL ++//DIDT_TCP_CTRL0 ++#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 ++#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 ++#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 ++#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 ++#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 ++#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 ++#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 ++#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 ++#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 ++#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 ++#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a ++#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b ++#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c ++#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L ++#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L ++#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L ++#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L ++#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L ++#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L ++#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L ++#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L ++#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L ++#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L ++#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L ++#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L ++#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L ++//DIDT_TCP_CTRL2 ++#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 ++#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 ++#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b ++#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL ++#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L ++#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L ++//DIDT_TCP_STALL_CTRL ++#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 ++#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 ++#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc ++#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 ++#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL ++#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L ++#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L ++#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L ++//DIDT_TCP_TUNING_CTRL ++#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 ++#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe ++#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL ++#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L ++//DIDT_TCP_STALL_AUTO_RELEASE_CTRL ++#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 ++#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL ++//DIDT_TCP_CTRL3 ++#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 ++#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 ++#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 ++#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 ++#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe ++#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 ++#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 ++#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 ++#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b ++#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c ++#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L ++#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L ++#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL ++#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L ++#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L ++#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L ++#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L ++#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L ++#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L ++#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L ++//DIDT_TCP_STALL_PATTERN_1_2 ++#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_TCP_STALL_PATTERN_3_4 ++#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_TCP_STALL_PATTERN_5_6 ++#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_TCP_STALL_PATTERN_7 ++#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_TCP_MPD_SCALE_FACTOR ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L ++#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L ++//DIDT_TCP_THROTTLE_CNTL0 ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL ++#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L ++//DIDT_TCP_THROTTLE_CNTL1 ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L ++#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L ++//DIDT_TCP_THROTTLE_CNTL_STATUS ++#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 ++#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L ++//DIDT_TCP_WEIGHT0_3 ++#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 ++#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 ++#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 ++#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 ++#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL ++#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L ++#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L ++#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L ++//DIDT_TCP_WEIGHT4_7 ++#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 ++#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 ++#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 ++#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 ++#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL ++#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L ++#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L ++#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L ++//DIDT_TCP_WEIGHT8_11 ++#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 ++#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 ++#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 ++#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 ++#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL ++#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L ++#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L ++#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L ++//DIDT_TCP_EDC_CTRL ++#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 ++#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 ++#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 ++#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 ++#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 ++#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 ++#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 ++#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 ++#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 ++#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 ++#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 ++#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 ++#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L ++#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L ++#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L ++#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L ++#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L ++#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L ++#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L ++#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L ++#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L ++#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L ++#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L ++#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L ++//DIDT_TCP_THROTTLE_CTRL ++#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 ++#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L ++//DIDT_TCP_EDC_STALL_PATTERN_1_2 ++#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 ++#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 ++#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL ++#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L ++//DIDT_TCP_EDC_STALL_PATTERN_3_4 ++#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 ++#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 ++#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL ++#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L ++//DIDT_TCP_EDC_STALL_PATTERN_5_6 ++#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 ++#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 ++#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL ++#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L ++//DIDT_TCP_EDC_STALL_PATTERN_7 ++#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 ++#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL ++//DIDT_TCP_EDC_STALL_DELAY_1 ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x7 ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xe ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x15 ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000007FL ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00003F80L ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x001FC000L ++#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x0FE00000L ++//DIDT_TCP_EDC_STALL_DELAY_2 ++#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 ++#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000007FL ++//DIDT_SQ_STALL_EVENT_COUNTER ++#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 ++#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL ++//DIDT_DB_STALL_EVENT_COUNTER ++#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 ++#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL ++//DIDT_TD_STALL_EVENT_COUNTER ++#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 ++#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL ++//DIDT_TCP_STALL_EVENT_COUNTER ++#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 ++#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL ++//DIDT_DBR_STALL_EVENT_COUNTER ++#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 ++#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL ++//DIDT_SQ_CTRL1 ++#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 ++#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 ++#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL ++#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L ++//DIDT_SQ_EDC_THRESHOLD ++#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 ++#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL ++//DIDT_DB_CTRL1 ++#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 ++#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 ++#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL ++#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L ++//DIDT_DB_EDC_THRESHOLD ++#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 ++#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL ++//DIDT_TD_CTRL1 ++#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 ++#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 ++#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL ++#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L ++//DIDT_TD_EDC_THRESHOLD ++#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 ++#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL ++//DIDT_TCP_CTRL1 ++#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 ++#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 ++#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL ++#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L ++//DIDT_TCP_EDC_THRESHOLD ++#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 ++#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL ++ ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h +new file mode 100644 +index 0000000..904ae53 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h +@@ -0,0 +1,1991 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _mmhub_9_3_0_OFFSET_HEADER ++#define _mmhub_9_3_0_OFFSET_HEADER ++ ++ ++ ++// addressBlock: mmhub_dagbdec ++// base address: 0x68000 ++#define mmDAGB0_RDCLI0 0x0000 ++#define mmDAGB0_RDCLI0_BASE_IDX 0 ++#define mmDAGB0_RDCLI1 0x0001 ++#define mmDAGB0_RDCLI1_BASE_IDX 0 ++#define mmDAGB0_RDCLI2 0x0002 ++#define mmDAGB0_RDCLI2_BASE_IDX 0 ++#define mmDAGB0_RDCLI3 0x0003 ++#define mmDAGB0_RDCLI3_BASE_IDX 0 ++#define mmDAGB0_RDCLI4 0x0004 ++#define mmDAGB0_RDCLI4_BASE_IDX 0 ++#define mmDAGB0_RDCLI5 0x0005 ++#define mmDAGB0_RDCLI5_BASE_IDX 0 ++#define mmDAGB0_RDCLI6 0x0006 ++#define mmDAGB0_RDCLI6_BASE_IDX 0 ++#define mmDAGB0_RDCLI7 0x0007 ++#define mmDAGB0_RDCLI7_BASE_IDX 0 ++#define mmDAGB0_RDCLI8 0x0008 ++#define mmDAGB0_RDCLI8_BASE_IDX 0 ++#define mmDAGB0_RDCLI9 0x0009 ++#define mmDAGB0_RDCLI9_BASE_IDX 0 ++#define mmDAGB0_RDCLI10 0x000a ++#define mmDAGB0_RDCLI10_BASE_IDX 0 ++#define mmDAGB0_RDCLI11 0x000b ++#define mmDAGB0_RDCLI11_BASE_IDX 0 ++#define mmDAGB0_RDCLI12 0x000c ++#define mmDAGB0_RDCLI12_BASE_IDX 0 ++#define mmDAGB0_RDCLI13 0x000d ++#define mmDAGB0_RDCLI13_BASE_IDX 0 ++#define mmDAGB0_RDCLI14 0x000e ++#define mmDAGB0_RDCLI14_BASE_IDX 0 ++#define mmDAGB0_RDCLI15 0x000f ++#define mmDAGB0_RDCLI15_BASE_IDX 0 ++#define mmDAGB0_RD_CNTL 0x0010 ++#define mmDAGB0_RD_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_GMI_CNTL 0x0011 ++#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB 0x0012 ++#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 ++#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 ++#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 ++#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 ++#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 ++#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015 ++#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 ++#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 ++#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a ++#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b ++#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB0_RD_VC0_CNTL 0x001c ++#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC1_CNTL 0x001d ++#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC2_CNTL 0x001e ++#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC3_CNTL 0x001f ++#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC4_CNTL 0x0020 ++#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC5_CNTL 0x0021 ++#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC6_CNTL 0x0022 ++#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_VC7_CNTL 0x0023 ++#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 ++#define mmDAGB0_RD_CNTL_MISC 0x0024 ++#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB0_RD_TLB_CREDIT 0x0025 ++#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 ++#define mmDAGB0_RDCLI_ASK_PENDING 0x0026 ++#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_GO_PENDING 0x0027 ++#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028 ++#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_TLB_PENDING 0x0029 ++#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_OARB_PENDING 0x002a ++#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 ++#define mmDAGB0_RDCLI_OSD_PENDING 0x002b ++#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI0 0x002c ++#define mmDAGB0_WRCLI0_BASE_IDX 0 ++#define mmDAGB0_WRCLI1 0x002d ++#define mmDAGB0_WRCLI1_BASE_IDX 0 ++#define mmDAGB0_WRCLI2 0x002e ++#define mmDAGB0_WRCLI2_BASE_IDX 0 ++#define mmDAGB0_WRCLI3 0x002f ++#define mmDAGB0_WRCLI3_BASE_IDX 0 ++#define mmDAGB0_WRCLI4 0x0030 ++#define mmDAGB0_WRCLI4_BASE_IDX 0 ++#define mmDAGB0_WRCLI5 0x0031 ++#define mmDAGB0_WRCLI5_BASE_IDX 0 ++#define mmDAGB0_WRCLI6 0x0032 ++#define mmDAGB0_WRCLI6_BASE_IDX 0 ++#define mmDAGB0_WRCLI7 0x0033 ++#define mmDAGB0_WRCLI7_BASE_IDX 0 ++#define mmDAGB0_WRCLI8 0x0034 ++#define mmDAGB0_WRCLI8_BASE_IDX 0 ++#define mmDAGB0_WRCLI9 0x0035 ++#define mmDAGB0_WRCLI9_BASE_IDX 0 ++#define mmDAGB0_WRCLI10 0x0036 ++#define mmDAGB0_WRCLI10_BASE_IDX 0 ++#define mmDAGB0_WRCLI11 0x0037 ++#define mmDAGB0_WRCLI11_BASE_IDX 0 ++#define mmDAGB0_WRCLI12 0x0038 ++#define mmDAGB0_WRCLI12_BASE_IDX 0 ++#define mmDAGB0_WRCLI13 0x0039 ++#define mmDAGB0_WRCLI13_BASE_IDX 0 ++#define mmDAGB0_WRCLI14 0x003a ++#define mmDAGB0_WRCLI14_BASE_IDX 0 ++#define mmDAGB0_WRCLI15 0x003b ++#define mmDAGB0_WRCLI15_BASE_IDX 0 ++#define mmDAGB0_WR_CNTL 0x003c ++#define mmDAGB0_WR_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_GMI_CNTL 0x003d ++#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB 0x003e ++#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 ++#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f ++#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 ++#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040 ++#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 ++#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041 ++#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042 ++#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043 ++#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046 ++#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047 ++#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB 0x0048 ++#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b ++#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c ++#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB0_WR_VC0_CNTL 0x004d ++#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC1_CNTL 0x004e ++#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC2_CNTL 0x004f ++#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC3_CNTL 0x0050 ++#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC4_CNTL 0x0051 ++#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC5_CNTL 0x0052 ++#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC6_CNTL 0x0053 ++#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_VC7_CNTL 0x0054 ++#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 ++#define mmDAGB0_WR_CNTL_MISC 0x0055 ++#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB0_WR_TLB_CREDIT 0x0056 ++#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 ++#define mmDAGB0_WR_DATA_CREDIT 0x0057 ++#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 ++#define mmDAGB0_WR_MISC_CREDIT 0x0058 ++#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 ++#define mmDAGB0_WRCLI_ASK_PENDING 0x0059 ++#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_GO_PENDING 0x005a ++#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005b ++#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_TLB_PENDING 0x005c ++#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_OARB_PENDING 0x005d ++#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_OSD_PENDING 0x005e ++#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x005f ++#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0060 ++#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 ++#define mmDAGB0_DAGB_DLY 0x0061 ++#define mmDAGB0_DAGB_DLY_BASE_IDX 0 ++#define mmDAGB0_CNTL_MISC 0x0062 ++#define mmDAGB0_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB0_CNTL_MISC2 0x0063 ++#define mmDAGB0_CNTL_MISC2_BASE_IDX 0 ++#define mmDAGB0_FIFO_EMPTY 0x0064 ++#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 ++#define mmDAGB0_FIFO_FULL 0x0065 ++#define mmDAGB0_FIFO_FULL_BASE_IDX 0 ++#define mmDAGB0_WR_CREDITS_FULL 0x0066 ++#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 ++#define mmDAGB0_RD_CREDITS_FULL 0x0067 ++#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER_LO 0x0068 ++#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER_HI 0x0069 ++#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER0_CFG 0x006a ++#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER1_CFG 0x006b ++#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER2_CFG 0x006c ++#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 ++#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x006d ++#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++#define mmDAGB0_RESERVE0 0x006e ++#define mmDAGB0_RESERVE0_BASE_IDX 0 ++#define mmDAGB0_RESERVE1 0x006f ++#define mmDAGB0_RESERVE1_BASE_IDX 0 ++#define mmDAGB0_RESERVE2 0x0070 ++#define mmDAGB0_RESERVE2_BASE_IDX 0 ++#define mmDAGB0_RESERVE3 0x0071 ++#define mmDAGB0_RESERVE3_BASE_IDX 0 ++#define mmDAGB0_RESERVE4 0x0072 ++#define mmDAGB0_RESERVE4_BASE_IDX 0 ++#define mmDAGB0_RESERVE5 0x0073 ++#define mmDAGB0_RESERVE5_BASE_IDX 0 ++#define mmDAGB0_RESERVE6 0x0074 ++#define mmDAGB0_RESERVE6_BASE_IDX 0 ++#define mmDAGB0_RESERVE7 0x0075 ++#define mmDAGB0_RESERVE7_BASE_IDX 0 ++#define mmDAGB0_RESERVE8 0x0076 ++#define mmDAGB0_RESERVE8_BASE_IDX 0 ++#define mmDAGB0_RESERVE9 0x0077 ++#define mmDAGB0_RESERVE9_BASE_IDX 0 ++#define mmDAGB0_RESERVE10 0x0078 ++#define mmDAGB0_RESERVE10_BASE_IDX 0 ++#define mmDAGB0_RESERVE11 0x0079 ++#define mmDAGB0_RESERVE11_BASE_IDX 0 ++#define mmDAGB0_RESERVE12 0x007a ++#define mmDAGB0_RESERVE12_BASE_IDX 0 ++#define mmDAGB0_RESERVE13 0x007b ++#define mmDAGB0_RESERVE13_BASE_IDX 0 ++#define mmDAGB0_RESERVE14 0x007c ++#define mmDAGB0_RESERVE14_BASE_IDX 0 ++#define mmDAGB0_RESERVE15 0x007d ++#define mmDAGB0_RESERVE15_BASE_IDX 0 ++#define mmDAGB0_RESERVE16 0x007e ++#define mmDAGB0_RESERVE16_BASE_IDX 0 ++#define mmDAGB0_RESERVE17 0x007f ++#define mmDAGB0_RESERVE17_BASE_IDX 0 ++#define mmDAGB1_RDCLI0 0x0080 ++#define mmDAGB1_RDCLI0_BASE_IDX 0 ++#define mmDAGB1_RDCLI1 0x0081 ++#define mmDAGB1_RDCLI1_BASE_IDX 0 ++#define mmDAGB1_RDCLI2 0x0082 ++#define mmDAGB1_RDCLI2_BASE_IDX 0 ++#define mmDAGB1_RDCLI3 0x0083 ++#define mmDAGB1_RDCLI3_BASE_IDX 0 ++#define mmDAGB1_RDCLI4 0x0084 ++#define mmDAGB1_RDCLI4_BASE_IDX 0 ++#define mmDAGB1_RDCLI5 0x0085 ++#define mmDAGB1_RDCLI5_BASE_IDX 0 ++#define mmDAGB1_RDCLI6 0x0086 ++#define mmDAGB1_RDCLI6_BASE_IDX 0 ++#define mmDAGB1_RDCLI7 0x0087 ++#define mmDAGB1_RDCLI7_BASE_IDX 0 ++#define mmDAGB1_RDCLI8 0x0088 ++#define mmDAGB1_RDCLI8_BASE_IDX 0 ++#define mmDAGB1_RDCLI9 0x0089 ++#define mmDAGB1_RDCLI9_BASE_IDX 0 ++#define mmDAGB1_RDCLI10 0x008a ++#define mmDAGB1_RDCLI10_BASE_IDX 0 ++#define mmDAGB1_RDCLI11 0x008b ++#define mmDAGB1_RDCLI11_BASE_IDX 0 ++#define mmDAGB1_RDCLI12 0x008c ++#define mmDAGB1_RDCLI12_BASE_IDX 0 ++#define mmDAGB1_RDCLI13 0x008d ++#define mmDAGB1_RDCLI13_BASE_IDX 0 ++#define mmDAGB1_RDCLI14 0x008e ++#define mmDAGB1_RDCLI14_BASE_IDX 0 ++#define mmDAGB1_RDCLI15 0x008f ++#define mmDAGB1_RDCLI15_BASE_IDX 0 ++#define mmDAGB1_RD_CNTL 0x0090 ++#define mmDAGB1_RD_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_GMI_CNTL 0x0091 ++#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_ADDR_DAGB 0x0092 ++#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 0 ++#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 ++#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 ++#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 ++#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 ++#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095 ++#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 ++#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 ++#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 ++#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 ++#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a ++#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b ++#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB1_RD_VC0_CNTL 0x009c ++#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_VC1_CNTL 0x009d ++#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_VC2_CNTL 0x009e ++#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_VC3_CNTL 0x009f ++#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_VC4_CNTL 0x00a0 ++#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_VC5_CNTL 0x00a1 ++#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_VC6_CNTL 0x00a2 ++#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_VC7_CNTL 0x00a3 ++#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 0 ++#define mmDAGB1_RD_CNTL_MISC 0x00a4 ++#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB1_RD_TLB_CREDIT 0x00a5 ++#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 0 ++#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6 ++#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB1_RDCLI_GO_PENDING 0x00a7 ++#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 ++#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8 ++#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 ++#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9 ++#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 ++#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa ++#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 ++#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab ++#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI0 0x00ac ++#define mmDAGB1_WRCLI0_BASE_IDX 0 ++#define mmDAGB1_WRCLI1 0x00ad ++#define mmDAGB1_WRCLI1_BASE_IDX 0 ++#define mmDAGB1_WRCLI2 0x00ae ++#define mmDAGB1_WRCLI2_BASE_IDX 0 ++#define mmDAGB1_WRCLI3 0x00af ++#define mmDAGB1_WRCLI3_BASE_IDX 0 ++#define mmDAGB1_WRCLI4 0x00b0 ++#define mmDAGB1_WRCLI4_BASE_IDX 0 ++#define mmDAGB1_WRCLI5 0x00b1 ++#define mmDAGB1_WRCLI5_BASE_IDX 0 ++#define mmDAGB1_WRCLI6 0x00b2 ++#define mmDAGB1_WRCLI6_BASE_IDX 0 ++#define mmDAGB1_WRCLI7 0x00b3 ++#define mmDAGB1_WRCLI7_BASE_IDX 0 ++#define mmDAGB1_WRCLI8 0x00b4 ++#define mmDAGB1_WRCLI8_BASE_IDX 0 ++#define mmDAGB1_WRCLI9 0x00b5 ++#define mmDAGB1_WRCLI9_BASE_IDX 0 ++#define mmDAGB1_WRCLI10 0x00b6 ++#define mmDAGB1_WRCLI10_BASE_IDX 0 ++#define mmDAGB1_WRCLI11 0x00b7 ++#define mmDAGB1_WRCLI11_BASE_IDX 0 ++#define mmDAGB1_WRCLI12 0x00b8 ++#define mmDAGB1_WRCLI12_BASE_IDX 0 ++#define mmDAGB1_WRCLI13 0x00b9 ++#define mmDAGB1_WRCLI13_BASE_IDX 0 ++#define mmDAGB1_WRCLI14 0x00ba ++#define mmDAGB1_WRCLI14_BASE_IDX 0 ++#define mmDAGB1_WRCLI15 0x00bb ++#define mmDAGB1_WRCLI15_BASE_IDX 0 ++#define mmDAGB1_WR_CNTL 0x00bc ++#define mmDAGB1_WR_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_GMI_CNTL 0x00bd ++#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_ADDR_DAGB 0x00be ++#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 0 ++#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf ++#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 ++#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0 ++#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 ++#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1 ++#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2 ++#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3 ++#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4 ++#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5 ++#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6 ++#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7 ++#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB1_WR_DATA_DAGB 0x00c8 ++#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 0 ++#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9 ++#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 ++#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca ++#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 ++#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb ++#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 ++#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc ++#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 ++#define mmDAGB1_WR_VC0_CNTL 0x00cd ++#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_VC1_CNTL 0x00ce ++#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_VC2_CNTL 0x00cf ++#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_VC3_CNTL 0x00d0 ++#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_VC4_CNTL 0x00d1 ++#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_VC5_CNTL 0x00d2 ++#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_VC6_CNTL 0x00d3 ++#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_VC7_CNTL 0x00d4 ++#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 0 ++#define mmDAGB1_WR_CNTL_MISC 0x00d5 ++#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB1_WR_TLB_CREDIT 0x00d6 ++#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 0 ++#define mmDAGB1_WR_DATA_CREDIT 0x00d7 ++#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 0 ++#define mmDAGB1_WR_MISC_CREDIT 0x00d8 ++#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 0 ++#define mmDAGB1_WRCLI_ASK_PENDING 0x00d9 ++#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI_GO_PENDING 0x00da ++#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00db ++#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI_TLB_PENDING 0x00dc ++#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI_OARB_PENDING 0x00dd ++#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI_OSD_PENDING 0x00de ++#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00df ++#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 ++#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e0 ++#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 ++#define mmDAGB1_DAGB_DLY 0x00e1 ++#define mmDAGB1_DAGB_DLY_BASE_IDX 0 ++#define mmDAGB1_CNTL_MISC 0x00e2 ++#define mmDAGB1_CNTL_MISC_BASE_IDX 0 ++#define mmDAGB1_CNTL_MISC2 0x00e3 ++#define mmDAGB1_CNTL_MISC2_BASE_IDX 0 ++#define mmDAGB1_FIFO_EMPTY 0x00e4 ++#define mmDAGB1_FIFO_EMPTY_BASE_IDX 0 ++#define mmDAGB1_FIFO_FULL 0x00e5 ++#define mmDAGB1_FIFO_FULL_BASE_IDX 0 ++#define mmDAGB1_WR_CREDITS_FULL 0x00e6 ++#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 0 ++#define mmDAGB1_RD_CREDITS_FULL 0x00e7 ++#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 0 ++#define mmDAGB1_PERFCOUNTER_LO 0x00e8 ++#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmDAGB1_PERFCOUNTER_HI 0x00e9 ++#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmDAGB1_PERFCOUNTER0_CFG 0x00ea ++#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmDAGB1_PERFCOUNTER1_CFG 0x00eb ++#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmDAGB1_PERFCOUNTER2_CFG 0x00ec ++#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 ++#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00ed ++#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++#define mmDAGB1_RESERVE0 0x00ee ++#define mmDAGB1_RESERVE0_BASE_IDX 0 ++#define mmDAGB1_RESERVE1 0x00ef ++#define mmDAGB1_RESERVE1_BASE_IDX 0 ++#define mmDAGB1_RESERVE2 0x00f0 ++#define mmDAGB1_RESERVE2_BASE_IDX 0 ++#define mmDAGB1_RESERVE3 0x00f1 ++#define mmDAGB1_RESERVE3_BASE_IDX 0 ++#define mmDAGB1_RESERVE4 0x00f2 ++#define mmDAGB1_RESERVE4_BASE_IDX 0 ++#define mmDAGB1_RESERVE5 0x00f3 ++#define mmDAGB1_RESERVE5_BASE_IDX 0 ++#define mmDAGB1_RESERVE6 0x00f4 ++#define mmDAGB1_RESERVE6_BASE_IDX 0 ++#define mmDAGB1_RESERVE7 0x00f5 ++#define mmDAGB1_RESERVE7_BASE_IDX 0 ++#define mmDAGB1_RESERVE8 0x00f6 ++#define mmDAGB1_RESERVE8_BASE_IDX 0 ++#define mmDAGB1_RESERVE9 0x00f7 ++#define mmDAGB1_RESERVE9_BASE_IDX 0 ++#define mmDAGB1_RESERVE10 0x00f8 ++#define mmDAGB1_RESERVE10_BASE_IDX 0 ++#define mmDAGB1_RESERVE11 0x00f9 ++#define mmDAGB1_RESERVE11_BASE_IDX 0 ++#define mmDAGB1_RESERVE12 0x00fa ++#define mmDAGB1_RESERVE12_BASE_IDX 0 ++#define mmDAGB1_RESERVE13 0x00fb ++#define mmDAGB1_RESERVE13_BASE_IDX 0 ++#define mmDAGB1_RESERVE14 0x00fc ++#define mmDAGB1_RESERVE14_BASE_IDX 0 ++#define mmDAGB1_RESERVE15 0x00fd ++#define mmDAGB1_RESERVE15_BASE_IDX 0 ++#define mmDAGB1_RESERVE16 0x00fe ++#define mmDAGB1_RESERVE16_BASE_IDX 0 ++#define mmDAGB1_RESERVE17 0x00ff ++#define mmDAGB1_RESERVE17_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_ea_mmeadec ++// base address: 0x68400 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 ++#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 ++#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 ++#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 ++#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_LAZY 0x0106 ++#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_LAZY 0x0107 ++#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 ++#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 ++#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 ++#define mmMMEA0_DRAM_PAGE_BURST 0x010a ++#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b ++#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c ++#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d ++#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e ++#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f ++#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 ++#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 ++#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 ++#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 ++#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 ++#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134 ++#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136 ++#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137 ++#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 ++#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138 ++#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 ++#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143 ++#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 ++#define mmMMEA0_ADDRNORMDRAM_TRICHANNEL_CFG 0x0145 ++#define mmMMEA0_ADDRNORMDRAM_TRICHANNEL_CFG_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC_BANK_CFG 0x0147 ++#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC_MISC_CFG 0x0148 ++#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014e ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014f ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0150 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0151 ++#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0152 ++#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x015d ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x015e ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x015f ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0160 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0161 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x0162 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x0163 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x0164 ++#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0165 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0166 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0167 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0168 ++#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0169 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x016a ++#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x016b ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x016c ++#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x016d ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x016e ++#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x016f ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0170 ++#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x0171 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x0172 ++#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x0173 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x0174 ++#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0175 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0176 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0177 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0178 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0179 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x017a ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x017b ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x017c ++#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x017d ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x017e ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x017f ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0180 ++#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0181 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0182 ++#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0183 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0184 ++#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0185 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0186 ++#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0187 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0188 ++#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0189 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x018a ++#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x018b ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x018c ++#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01d5 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01d6 ++#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01d7 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01d8 ++#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01d9 ++#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 ++#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01da ++#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 ++#define mmMMEA0_IO_GROUP_BURST 0x01db ++#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_AGE 0x01dc ++#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_AGE 0x01dd ++#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUEUING 0x01de ++#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUEUING 0x01df ++#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_FIXED 0x01e0 ++#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_FIXED 0x01e1 ++#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_URGENCY 0x01e2 ++#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_URGENCY 0x01e3 ++#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_URGENCY_MASK 0x01e4 ++#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_URGENCY_MASK 0x01e5 ++#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01e6 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01e7 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01e8 ++#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01e9 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01ea ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01eb ++#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA0_SDP_ARB_DRAM 0x01ec ++#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 ++#define mmMMEA0_SDP_ARB_FINAL 0x01ee ++#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 ++#define mmMMEA0_SDP_DRAM_PRIORITY 0x01ef ++#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 ++#define mmMMEA0_SDP_IO_PRIORITY 0x01f1 ++#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 ++#define mmMMEA0_SDP_CREDITS 0x01f2 ++#define mmMMEA0_SDP_CREDITS_BASE_IDX 0 ++#define mmMMEA0_SDP_TAG_RESERVE0 0x01f3 ++#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 ++#define mmMMEA0_SDP_TAG_RESERVE1 0x01f4 ++#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 ++#define mmMMEA0_SDP_VCC_RESERVE0 0x01f5 ++#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 ++#define mmMMEA0_SDP_VCC_RESERVE1 0x01f6 ++#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 ++#define mmMMEA0_SDP_VCD_RESERVE0 0x01f7 ++#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 ++#define mmMMEA0_SDP_VCD_RESERVE1 0x01f8 ++#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 ++#define mmMMEA0_SDP_REQ_CNTL 0x01f9 ++#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 ++#define mmMMEA0_MISC 0x01fa ++#define mmMMEA0_MISC_BASE_IDX 0 ++#define mmMMEA0_LATENCY_SAMPLING 0x01fb ++#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER_LO 0x01fc ++#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER_HI 0x01fd ++#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER0_CFG 0x01fe ++#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER1_CFG 0x01ff ++#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0200 ++#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++#define mmMMEA0_EDC_CNT 0x0206 ++#define mmMMEA0_EDC_CNT_BASE_IDX 0 ++#define mmMMEA0_EDC_CNT2 0x0207 ++#define mmMMEA0_EDC_CNT2_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL 0x0208 ++#define mmMMEA0_DSM_CNTL_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTLA 0x0209 ++#define mmMMEA0_DSM_CNTLA_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTLB 0x020a ++#define mmMMEA0_DSM_CNTLB_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL2 0x020b ++#define mmMMEA0_DSM_CNTL2_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL2A 0x020c ++#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 ++#define mmMMEA0_DSM_CNTL2B 0x020d ++#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 ++#define mmMMEA0_CGTT_CLK_CTRL 0x020f ++#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmMMEA0_EDC_MODE 0x0210 ++#define mmMMEA0_EDC_MODE_BASE_IDX 0 ++#define mmMMEA0_ERR_STATUS 0x0211 ++#define mmMMEA0_ERR_STATUS_BASE_IDX 0 ++#define mmMMEA0_MISC2 0x0212 ++#define mmMMEA0_MISC2_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0240 ++#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0241 ++#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0242 ++#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0243 ++#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x0244 ++#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x0245 ++#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_LAZY 0x0246 ++#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_LAZY 0x0247 ++#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_CAM_CNTL 0x0248 ++#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_CAM_CNTL 0x0249 ++#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 ++#define mmMMEA1_DRAM_PAGE_BURST 0x024a ++#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_PRI_AGE 0x024b ++#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_PRI_AGE 0x024c ++#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x024d ++#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x024e ++#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_PRI_FIXED 0x024f ++#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_PRI_FIXED 0x0250 ++#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x0251 ++#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x0252 ++#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0253 ++#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0254 ++#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0255 ++#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0256 ++#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0257 ++#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0258 ++#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x0274 ++#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0 ++#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x0275 ++#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 ++#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x0276 ++#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0 ++#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x0277 ++#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 ++#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x0278 ++#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 ++#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0283 ++#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 ++#define mmMMEA1_ADDRNORMDRAM_TRICHANNEL_CFG 0x0285 ++#define mmMMEA1_ADDRNORMDRAM_TRICHANNEL_CFG_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC_BANK_CFG 0x0287 ++#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC_MISC_CFG 0x0288 ++#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0289 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x028a ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x028b ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x028c ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x028d ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x028e ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x028f ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x0290 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x0291 ++#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 ++#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0292 ++#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x029d ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x029e ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x029f ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x02a0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x02a1 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x02a2 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x02a3 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x02a4 ++#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x02a5 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x02a6 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x02a7 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x02a8 ++#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x02a9 ++#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x02aa ++#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x02ab ++#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x02ac ++#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x02ad ++#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x02ae ++#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x02af ++#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x02b0 ++#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x02b1 ++#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x02b2 ++#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x02b3 ++#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x02b4 ++#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x02b5 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x02b6 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x02b7 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x02b8 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x02b9 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x02ba ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x02bb ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x02bc ++#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x02bd ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x02be ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x02bf ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x02c0 ++#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x02c1 ++#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x02c2 ++#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x02c3 ++#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x02c4 ++#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x02c5 ++#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x02c6 ++#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x02c7 ++#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x02c8 ++#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x02c9 ++#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x02ca ++#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x02cb ++#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 ++#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x02cc ++#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 ++#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0315 ++#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0316 ++#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0317 ++#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 ++#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0318 ++#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 ++#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0319 ++#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 ++#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x031a ++#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 ++#define mmMMEA1_IO_GROUP_BURST 0x031b ++#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_AGE 0x031c ++#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_AGE 0x031d ++#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_QUEUING 0x031e ++#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_QUEUING 0x031f ++#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_FIXED 0x0320 ++#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_FIXED 0x0321 ++#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_URGENCY 0x0322 ++#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_URGENCY 0x0323 ++#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_URGENCY_MASK 0x0324 ++#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_URGENCY_MASK 0x0325 ++#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x0326 ++#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x0327 ++#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x0328 ++#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x0329 ++#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x032a ++#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 ++#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x032b ++#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 ++#define mmMMEA1_SDP_ARB_DRAM 0x032c ++#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 0 ++#define mmMMEA1_SDP_ARB_FINAL 0x032e ++#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 0 ++#define mmMMEA1_SDP_DRAM_PRIORITY 0x032f ++#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 ++#define mmMMEA1_SDP_IO_PRIORITY 0x0331 ++#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 ++#define mmMMEA1_SDP_CREDITS 0x0332 ++#define mmMMEA1_SDP_CREDITS_BASE_IDX 0 ++#define mmMMEA1_SDP_TAG_RESERVE0 0x0333 ++#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 ++#define mmMMEA1_SDP_TAG_RESERVE1 0x0334 ++#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 ++#define mmMMEA1_SDP_VCC_RESERVE0 0x0335 ++#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 ++#define mmMMEA1_SDP_VCC_RESERVE1 0x0336 ++#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 ++#define mmMMEA1_SDP_VCD_RESERVE0 0x0337 ++#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 ++#define mmMMEA1_SDP_VCD_RESERVE1 0x0338 ++#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 ++#define mmMMEA1_SDP_REQ_CNTL 0x0339 ++#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 0 ++#define mmMMEA1_MISC 0x033a ++#define mmMMEA1_MISC_BASE_IDX 0 ++#define mmMMEA1_LATENCY_SAMPLING 0x033b ++#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 0 ++#define mmMMEA1_PERFCOUNTER_LO 0x033c ++#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMMEA1_PERFCOUNTER_HI 0x033d ++#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 0 ++#define mmMMEA1_PERFCOUNTER0_CFG 0x033e ++#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMMEA1_PERFCOUNTER1_CFG 0x033f ++#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x0340 ++#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++#define mmMMEA1_EDC_CNT 0x0346 ++#define mmMMEA1_EDC_CNT_BASE_IDX 0 ++#define mmMMEA1_EDC_CNT2 0x0347 ++#define mmMMEA1_EDC_CNT2_BASE_IDX 0 ++#define mmMMEA1_DSM_CNTL 0x0348 ++#define mmMMEA1_DSM_CNTL_BASE_IDX 0 ++#define mmMMEA1_DSM_CNTLA 0x0349 ++#define mmMMEA1_DSM_CNTLA_BASE_IDX 0 ++#define mmMMEA1_DSM_CNTLB 0x034a ++#define mmMMEA1_DSM_CNTLB_BASE_IDX 0 ++#define mmMMEA1_DSM_CNTL2 0x034b ++#define mmMMEA1_DSM_CNTL2_BASE_IDX 0 ++#define mmMMEA1_DSM_CNTL2A 0x034c ++#define mmMMEA1_DSM_CNTL2A_BASE_IDX 0 ++#define mmMMEA1_DSM_CNTL2B 0x034d ++#define mmMMEA1_DSM_CNTL2B_BASE_IDX 0 ++#define mmMMEA1_CGTT_CLK_CTRL 0x034f ++#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmMMEA1_EDC_MODE 0x0350 ++#define mmMMEA1_EDC_MODE_BASE_IDX 0 ++#define mmMMEA1_ERR_STATUS 0x0351 ++#define mmMMEA1_ERR_STATUS_BASE_IDX 0 ++#define mmMMEA1_MISC2 0x0352 ++#define mmMMEA1_MISC2_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_pctldec ++// base address: 0x68e00 ++#define mmPCTL_MISC 0x0380 ++#define mmPCTL_MISC_BASE_IDX 0 ++#define mmPCTL_MMHUB_DEEPSLEEP 0x0381 ++#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 ++#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 ++#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 ++#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 ++#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 ++#define mmPCTL_PG_DAGB 0x0384 ++#define mmPCTL_PG_DAGB_BASE_IDX 0 ++#define mmPCTL0_RENG_RAM_INDEX 0x0385 ++#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 ++#define mmPCTL0_RENG_RAM_DATA 0x0386 ++#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 ++#define mmPCTL0_RENG_EXECUTE 0x0387 ++#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 ++#define mmPCTL0_MISC 0x0388 ++#define mmPCTL0_MISC_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x0389 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038a ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x038b ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3 0x038c ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4 0x038d ++#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x038e ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x038f ++#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 ++#define mmPCTL1_RENG_RAM_INDEX 0x0390 ++#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 ++#define mmPCTL1_RENG_RAM_DATA 0x0391 ++#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 ++#define mmPCTL1_RENG_EXECUTE 0x0392 ++#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 ++#define mmPCTL1_MISC 0x0393 ++#define mmPCTL1_MISC_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0394 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0395 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0396 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3 0x0397 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4 0x0398 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x0399 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039a ++#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 ++#define mmPCTL2_RENG_RAM_INDEX 0x039b ++#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 ++#define mmPCTL2_RENG_RAM_DATA 0x039c ++#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 ++#define mmPCTL2_RENG_EXECUTE 0x039d ++#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 ++#define mmPCTL2_MISC 0x039e ++#define mmPCTL2_MISC_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039f ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x03a0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x03a1 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3 0x03a2 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4 0x03a3 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x03a4 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a5 ++#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_l1tlb_vml1dec ++// base address: 0x69600 ++#define mmMC_VM_MX_L1_TLB0_STATUS 0x0588 ++#define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB1_STATUS 0x0589 ++#define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB2_STATUS 0x058a ++#define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB3_STATUS 0x058b ++#define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB4_STATUS 0x058c ++#define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB5_STATUS 0x058d ++#define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB6_STATUS 0x058e ++#define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB7_STATUS 0x058f ++#define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_l1tlb_vml1pldec ++// base address: 0x69650 ++#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 ++#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 ++#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 ++#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 ++#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 ++#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 ++#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 ++#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_l1tlb_vml1prdec ++// base address: 0x69670 ++#define mmMC_VM_MX_L1_PERFCOUNTER_LO 0x059c ++#define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d ++#define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_atcl2dec ++// base address: 0x69900 ++#define mmATC_L2_CNTL 0x0640 ++#define mmATC_L2_CNTL_BASE_IDX 0 ++#define mmATC_L2_CNTL2 0x0641 ++#define mmATC_L2_CNTL2_BASE_IDX 0 ++#define mmATC_L2_CACHE_DATA0 0x0644 ++#define mmATC_L2_CACHE_DATA0_BASE_IDX 0 ++#define mmATC_L2_CACHE_DATA1 0x0645 ++#define mmATC_L2_CACHE_DATA1_BASE_IDX 0 ++#define mmATC_L2_CACHE_DATA2 0x0646 ++#define mmATC_L2_CACHE_DATA2_BASE_IDX 0 ++#define mmATC_L2_CNTL3 0x0647 ++#define mmATC_L2_CNTL3_BASE_IDX 0 ++#define mmATC_L2_STATUS 0x0648 ++#define mmATC_L2_STATUS_BASE_IDX 0 ++#define mmATC_L2_STATUS2 0x0649 ++#define mmATC_L2_STATUS2_BASE_IDX 0 ++#define mmATC_L2_MISC_CG 0x064a ++#define mmATC_L2_MISC_CG_BASE_IDX 0 ++#define mmATC_L2_MEM_POWER_LS 0x064b ++#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0 ++#define mmATC_L2_CGTT_CLK_CTRL 0x064c ++#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_vml2pfdec ++// base address: 0x69a00 ++#define mmVM_L2_CNTL 0x0680 ++#define mmVM_L2_CNTL_BASE_IDX 0 ++#define mmVM_L2_CNTL2 0x0681 ++#define mmVM_L2_CNTL2_BASE_IDX 0 ++#define mmVM_L2_CNTL3 0x0682 ++#define mmVM_L2_CNTL3_BASE_IDX 0 ++#define mmVM_L2_STATUS 0x0683 ++#define mmVM_L2_STATUS_BASE_IDX 0 ++#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0684 ++#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0687 ++#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0688 ++#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0689 ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068a ++#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_STATUS 0x068b ++#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068c ++#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068d ++#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068e ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x068f ++#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0691 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0692 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0693 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0694 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0695 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0696 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 ++#define mmVM_L2_CNTL4 0x0697 ++#define mmVM_L2_CNTL4_BASE_IDX 0 ++#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0698 ++#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 ++#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0699 ++#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 ++#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x069a ++#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 ++#define mmVM_L2_CACHE_PARITY_CNTL 0x069b ++#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 ++#define mmVM_L2_CGTT_CLK_CTRL 0x069e ++#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_vml2vcdec ++// base address: 0x69b00 ++#define mmVM_CONTEXT0_CNTL 0x06c0 ++#define mmVM_CONTEXT0_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT1_CNTL 0x06c1 ++#define mmVM_CONTEXT1_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT2_CNTL 0x06c2 ++#define mmVM_CONTEXT2_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT3_CNTL 0x06c3 ++#define mmVM_CONTEXT3_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT4_CNTL 0x06c4 ++#define mmVM_CONTEXT4_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT5_CNTL 0x06c5 ++#define mmVM_CONTEXT5_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT6_CNTL 0x06c6 ++#define mmVM_CONTEXT6_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT7_CNTL 0x06c7 ++#define mmVM_CONTEXT7_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT8_CNTL 0x06c8 ++#define mmVM_CONTEXT8_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT9_CNTL 0x06c9 ++#define mmVM_CONTEXT9_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT10_CNTL 0x06ca ++#define mmVM_CONTEXT10_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT11_CNTL 0x06cb ++#define mmVM_CONTEXT11_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT12_CNTL 0x06cc ++#define mmVM_CONTEXT12_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT13_CNTL 0x06cd ++#define mmVM_CONTEXT13_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT14_CNTL 0x06ce ++#define mmVM_CONTEXT14_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXT15_CNTL 0x06cf ++#define mmVM_CONTEXT15_CNTL_BASE_IDX 0 ++#define mmVM_CONTEXTS_DISABLE 0x06d0 ++#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_SEM 0x06d1 ++#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_SEM 0x06d2 ++#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_SEM 0x06d3 ++#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_SEM 0x06d4 ++#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_SEM 0x06d5 ++#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_SEM 0x06d6 ++#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_SEM 0x06d7 ++#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_SEM 0x06d8 ++#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_SEM 0x06d9 ++#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_SEM 0x06da ++#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_SEM 0x06db ++#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_SEM 0x06dc ++#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_SEM 0x06dd ++#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_SEM 0x06de ++#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_SEM 0x06df ++#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_SEM 0x06e0 ++#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_SEM 0x06e1 ++#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_SEM 0x06e2 ++#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_REQ 0x06e3 ++#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_REQ 0x06e4 ++#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_REQ 0x06e5 ++#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_REQ 0x06e6 ++#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_REQ 0x06e7 ++#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_REQ 0x06e8 ++#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_REQ 0x06e9 ++#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_REQ 0x06ea ++#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_REQ 0x06eb ++#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_REQ 0x06ec ++#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_REQ 0x06ed ++#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_REQ 0x06ee ++#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_REQ 0x06ef ++#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_REQ 0x06f0 ++#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_REQ 0x06f1 ++#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_REQ 0x06f2 ++#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_REQ 0x06f3 ++#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_REQ 0x06f4 ++#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_ACK 0x06f5 ++#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_ACK 0x06f6 ++#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_ACK 0x06f7 ++#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_ACK 0x06f8 ++#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_ACK 0x06f9 ++#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_ACK 0x06fa ++#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_ACK 0x06fb ++#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_ACK 0x06fc ++#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_ACK 0x06fd ++#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_ACK 0x06fe ++#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_ACK 0x06ff ++#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_ACK 0x0700 ++#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_ACK 0x0701 ++#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_ACK 0x0702 ++#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_ACK 0x0703 ++#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_ACK 0x0704 ++#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_ACK 0x0705 ++#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_ACK 0x0706 ++#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 ++#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a ++#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c ++#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e ++#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 ++#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 ++#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 ++#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 ++#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 ++#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a ++#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c ++#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e ++#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 ++#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 ++#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 ++#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 ++#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 ++#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a ++#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 ++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 ++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 ++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 ++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 ++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a ++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c ++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e ++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 ++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 ++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 ++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 ++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 ++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a ++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 ++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 ++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 ++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 ++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 ++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a ++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c ++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e ++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 ++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 ++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 ++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 ++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 ++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a ++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_vml2pldec ++// base address: 0x69e90 ++#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 ++#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 ++#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 ++#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 ++#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 ++#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 ++#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x07aa ++#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x07ab ++#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac ++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_vml2prdec ++// base address: 0x69ee0 ++#define mmMC_VM_L2_PERFCOUNTER_LO 0x07b8 ++#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmMC_VM_L2_PERFCOUNTER_HI 0x07b9 ++#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_vmsharedhvdec ++// base address: 0x69f30 ++#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x07cc ++#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x07cd ++#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x07ce ++#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x07cf ++#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 ++#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 ++#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 ++#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 ++#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 ++#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 ++#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 ++#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 ++#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 ++#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x07da ++#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 ++#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x07db ++#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 ++#define mmVM_IOMMU_MMIO_CNTRL_1 0x07dc ++#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_LO_0 0x07dd ++#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_LO_1 0x07de ++#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_LO_2 0x07df ++#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_LO_3 0x07e0 ++#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_HI_0 0x07e1 ++#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_HI_1 0x07e2 ++#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_HI_2 0x07e3 ++#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 0 ++#define mmMC_VM_MARC_BASE_HI_3 0x07e4 ++#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_LO_0 0x07e5 ++#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_LO_1 0x07e6 ++#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_LO_2 0x07e7 ++#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_LO_3 0x07e8 ++#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_HI_0 0x07e9 ++#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_HI_1 0x07ea ++#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_HI_2 0x07eb ++#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 ++#define mmMC_VM_MARC_RELOC_HI_3 0x07ec ++#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_LO_0 0x07ed ++#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_LO_1 0x07ee ++#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_LO_2 0x07ef ++#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_LO_3 0x07f0 ++#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_HI_0 0x07f1 ++#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_HI_1 0x07f2 ++#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_HI_2 0x07f3 ++#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 0 ++#define mmMC_VM_MARC_LEN_HI_3 0x07f4 ++#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 0 ++#define mmVM_IOMMU_CONTROL_REGISTER 0x07f5 ++#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 ++#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07f6 ++#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL 0x07f7 ++#define mmVM_PCIE_ATS_CNTL_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_0 0x07f8 ++#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_1 0x07f9 ++#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_2 0x07fa ++#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_3 0x07fb ++#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_4 0x07fc ++#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_5 0x07fd ++#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_6 0x07fe ++#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_7 0x07ff ++#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_8 0x0800 ++#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_9 0x0801 ++#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_10 0x0802 ++#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_11 0x0803 ++#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_12 0x0804 ++#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_13 0x0805 ++#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_14 0x0806 ++#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 ++#define mmVM_PCIE_ATS_CNTL_VF_15 0x0807 ++#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 ++#define mmUTCL2_CGTT_CLK_CTRL 0x0808 ++#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 ++#define mmMC_SHARED_ACTIVE_FCN_ID 0x0809 ++#define mmMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmMC_VM_XGMI_GPUIOV_ENABLE 0x080a ++#define mmMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_vmsharedpfdec ++// base address: 0x6a040 ++#define mmMC_VM_NB_MMIOBASE 0x0810 ++#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0 ++#define mmMC_VM_NB_MMIOLIMIT 0x0811 ++#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0 ++#define mmMC_VM_NB_PCI_CTRL 0x0812 ++#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0 ++#define mmMC_VM_NB_PCI_ARB 0x0813 ++#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0 ++#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0814 ++#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 ++#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0815 ++#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 ++#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0816 ++#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 ++#define mmMC_VM_FB_OFFSET 0x0817 ++#define mmMC_VM_FB_OFFSET_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0818 ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0819 ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 ++#define mmMC_VM_STEERING 0x081a ++#define mmMC_VM_STEERING_BASE_IDX 0 ++#define mmMC_SHARED_VIRT_RESET_REQ 0x081b ++#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmMC_MEM_POWER_LS 0x081c ++#define mmMC_MEM_POWER_LS_BASE_IDX 0 ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x081d ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x081e ++#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 ++#define mmMC_VM_APT_CNTL 0x081f ++#define mmMC_VM_APT_CNTL_BASE_IDX 0 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0820 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0821 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0822 ++#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 ++#define mmMC_VM_XGMI_LFB_CNTL 0x0823 ++#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 ++#define mmMC_VM_XGMI_LFB_SIZE 0x0824 ++#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_vmsharedvcdec ++// base address: 0x6a0b0 ++#define mmMC_VM_FB_LOCATION_BASE 0x082c ++#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0 ++#define mmMC_VM_FB_LOCATION_TOP 0x082d ++#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0 ++#define mmMC_VM_AGP_TOP 0x082e ++#define mmMC_VM_AGP_TOP_BASE_IDX 0 ++#define mmMC_VM_AGP_BOT 0x082f ++#define mmMC_VM_AGP_BOT_BASE_IDX 0 ++#define mmMC_VM_AGP_BASE 0x0830 ++#define mmMC_VM_AGP_BASE_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0831 ++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 ++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0832 ++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 ++#define mmMC_VM_MX_L1_TLB_CNTL 0x0833 ++#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_atcl2pfcntrdec ++// base address: 0x6a100 ++#define mmATC_L2_PERFCOUNTER_LO 0x0840 ++#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 0 ++#define mmATC_L2_PERFCOUNTER_HI 0x0841 ++#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 0 ++ ++ ++// addressBlock: mmhub_utcl2_atcl2pfcntldec ++// base address: 0x6a120 ++#define mmATC_L2_PERFCOUNTER0_CFG 0x0848 ++#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 ++#define mmATC_L2_PERFCOUNTER1_CFG 0x0849 ++#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 ++#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a ++#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h +new file mode 100644 +index 0000000..3936c1d +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h +@@ -0,0 +1,10265 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _mmhub_9_3_0_SH_MASK_HEADER ++#define _mmhub_9_3_0_SH_MASK_HEADER ++ ++ ++// addressBlock: mmhub_dagbdec ++//DAGB0_RDCLI0 ++#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI1 ++#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI2 ++#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI3 ++#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI4 ++#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI5 ++#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI6 ++#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI7 ++#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI8 ++#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI9 ++#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI10 ++#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI11 ++#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI12 ++#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI13 ++#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI14 ++#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RDCLI15 ++#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 ++#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 ++#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd ++#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 ++#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a ++#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L ++#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L ++#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L ++#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L ++//DAGB0_RD_CNTL ++#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 ++#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 ++#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa ++#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 ++#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 ++#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 ++#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 ++#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL ++#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L ++#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L ++#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L ++#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L ++#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L ++#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L ++//DAGB0_RD_GMI_CNTL ++#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 ++#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 ++#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd ++#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL ++#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L ++#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L ++#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L ++//DAGB0_RD_ADDR_DAGB ++#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB0_RD_OUTPUT_DAGB_MAX_BURST ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L ++#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L ++//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L ++#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L ++//DAGB0_RD_CGTT_CLK_CTRL ++#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_L1TLB_RD_CGTT_CLK_CTRL ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_ATCVM_RD_CGTT_CLK_CTRL ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_RD_ADDR_DAGB_MAX_BURST0 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_MAX_BURST1 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB0_RD_VC0_CNTL ++#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC1_CNTL ++#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC2_CNTL ++#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC3_CNTL ++#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC4_CNTL ++#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC5_CNTL ++#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC6_CNTL ++#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_VC7_CNTL ++#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_RD_CNTL_MISC ++#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 ++#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 ++#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd ++#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 ++#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 ++#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 ++#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL ++#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L ++#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L ++#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L ++#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L ++#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L ++//DAGB0_RD_TLB_CREDIT ++#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 ++#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 ++#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa ++#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf ++#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 ++#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 ++#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL ++#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L ++#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L ++#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L ++#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L ++#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L ++//DAGB0_RDCLI_ASK_PENDING ++#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_GO_PENDING ++#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_GBLSEND_PENDING ++#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_TLB_PENDING ++#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_OARB_PENDING ++#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_RDCLI_OSD_PENDING ++#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI0 ++#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI1 ++#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI2 ++#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI3 ++#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI4 ++#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI5 ++#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI6 ++#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI7 ++#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI8 ++#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI9 ++#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI10 ++#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI11 ++#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI12 ++#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI13 ++#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI14 ++#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WRCLI15 ++#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 ++#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 ++#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 ++#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd ++#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 ++#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a ++#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L ++#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L ++#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L ++#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L ++#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L ++#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L ++//DAGB0_WR_CNTL ++#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 ++#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 ++#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa ++#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 ++#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 ++#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 ++#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 ++#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL ++#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L ++#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L ++#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L ++#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L ++#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L ++#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L ++//DAGB0_WR_GMI_CNTL ++#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 ++#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 ++#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd ++#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL ++#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L ++#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L ++#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L ++//DAGB0_WR_ADDR_DAGB ++#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB0_WR_OUTPUT_DAGB_MAX_BURST ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L ++#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L ++//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L ++#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L ++//DAGB0_WR_CGTT_CLK_CTRL ++#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_L1TLB_WR_CGTT_CLK_CTRL ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_ATCVM_WR_CGTT_CLK_CTRL ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB0_WR_ADDR_DAGB_MAX_BURST0 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_MAX_BURST1 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB ++#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB0_WR_DATA_DAGB_MAX_BURST0 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_MAX_BURST1 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB0_WR_VC0_CNTL ++#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC1_CNTL ++#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC2_CNTL ++#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC3_CNTL ++#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC4_CNTL ++#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC5_CNTL ++#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC6_CNTL ++#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_VC7_CNTL ++#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB0_WR_CNTL_MISC ++#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 ++#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd ++#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 ++#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 ++#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 ++#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL ++#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L ++#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L ++#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L ++#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L ++#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L ++//DAGB0_WR_TLB_CREDIT ++#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 ++#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 ++#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa ++#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf ++#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 ++#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 ++#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL ++#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L ++#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L ++#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L ++#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L ++#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L ++//DAGB0_WR_DATA_CREDIT ++#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 ++#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 ++#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 ++#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 ++#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL ++#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L ++#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L ++#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L ++//DAGB0_WR_MISC_CREDIT ++#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 ++#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 ++#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 ++#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 ++#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL ++#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L ++#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L ++#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L ++//DAGB0_WRCLI_ASK_PENDING ++#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_GO_PENDING ++#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_GBLSEND_PENDING ++#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_TLB_PENDING ++#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_OARB_PENDING ++#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_OSD_PENDING ++#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_DBUS_ASK_PENDING ++#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_WRCLI_DBUS_GO_PENDING ++#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB0_DAGB_DLY ++#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 ++#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 ++#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 ++#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL ++#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L ++#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L ++//DAGB0_CNTL_MISC ++#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 ++#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 ++#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 ++#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 ++#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc ++#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf ++#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 ++#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 ++#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 ++#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e ++#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L ++#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L ++#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L ++#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L ++#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L ++#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L ++#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L ++#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L ++#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L ++#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L ++//DAGB0_CNTL_MISC2 ++#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 ++#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 ++#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 ++#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 ++#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 ++#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 ++#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 ++#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 ++#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 ++#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 ++#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa ++#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L ++#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L ++#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L ++#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L ++#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L ++#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L ++#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L ++#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L ++#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L ++#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L ++#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L ++//DAGB0_FIFO_EMPTY ++#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 ++#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL ++//DAGB0_FIFO_FULL ++#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 ++#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL ++//DAGB0_WR_CREDITS_FULL ++#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 ++#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL ++//DAGB0_RD_CREDITS_FULL ++#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 ++#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL ++//DAGB0_PERFCOUNTER_LO ++#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//DAGB0_PERFCOUNTER_HI ++#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//DAGB0_PERFCOUNTER0_CFG ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//DAGB0_PERFCOUNTER1_CFG ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//DAGB0_PERFCOUNTER2_CFG ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//DAGB0_PERFCOUNTER_RSLT_CNTL ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++//DAGB0_RESERVE0 ++#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE1 ++#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE2 ++#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE3 ++#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE4 ++#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE5 ++#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE6 ++#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE7 ++#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE8 ++#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE9 ++#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE10 ++#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE11 ++#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE12 ++#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE13 ++#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE14 ++#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE15 ++#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE16 ++#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL ++//DAGB0_RESERVE17 ++#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 ++#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RDCLI0 ++#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI1 ++#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI2 ++#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI3 ++#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI4 ++#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI5 ++#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI6 ++#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI7 ++#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI8 ++#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI9 ++#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI10 ++#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI11 ++#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI12 ++#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI13 ++#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI14 ++#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RDCLI15 ++#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 ++#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 ++#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd ++#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 ++#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a ++#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L ++#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L ++#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L ++#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L ++//DAGB1_RD_CNTL ++#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 ++#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 ++#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa ++#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 ++#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 ++#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 ++#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 ++#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL ++#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L ++#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L ++#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L ++#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L ++#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L ++#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L ++//DAGB1_RD_GMI_CNTL ++#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 ++#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 ++#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd ++#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL ++#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L ++#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L ++#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L ++//DAGB1_RD_ADDR_DAGB ++#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB1_RD_OUTPUT_DAGB_MAX_BURST ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L ++#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L ++//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L ++#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L ++//DAGB1_RD_CGTT_CLK_CTRL ++#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB1_L1TLB_RD_CGTT_CLK_CTRL ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB1_ATCVM_RD_CGTT_CLK_CTRL ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB1_RD_ADDR_DAGB_MAX_BURST0 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB1_RD_ADDR_DAGB_MAX_BURST1 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB1_RD_VC0_CNTL ++#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_VC1_CNTL ++#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_VC2_CNTL ++#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_VC3_CNTL ++#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_VC4_CNTL ++#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_VC5_CNTL ++#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_VC6_CNTL ++#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_VC7_CNTL ++#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_RD_CNTL_MISC ++#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 ++#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 ++#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd ++#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 ++#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 ++#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 ++#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL ++#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L ++#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L ++#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L ++#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L ++#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L ++//DAGB1_RD_TLB_CREDIT ++#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 ++#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 ++#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa ++#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf ++#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 ++#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 ++#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL ++#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L ++#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L ++#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L ++#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L ++#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L ++//DAGB1_RDCLI_ASK_PENDING ++#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_RDCLI_GO_PENDING ++#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_RDCLI_GBLSEND_PENDING ++#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_RDCLI_TLB_PENDING ++#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_RDCLI_OARB_PENDING ++#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_RDCLI_OSD_PENDING ++#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI0 ++#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI1 ++#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI2 ++#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI3 ++#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI4 ++#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI5 ++#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI6 ++#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI7 ++#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI8 ++#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI9 ++#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI10 ++#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI11 ++#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI12 ++#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI13 ++#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI14 ++#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WRCLI15 ++#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 ++#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 ++#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 ++#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 ++#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc ++#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd ++#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 ++#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 ++#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 ++#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a ++#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L ++#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L ++#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L ++#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L ++#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L ++#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L ++#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L ++#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L ++#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L ++#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L ++//DAGB1_WR_CNTL ++#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 ++#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 ++#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa ++#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 ++#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 ++#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 ++#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 ++#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL ++#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L ++#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L ++#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L ++#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L ++#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L ++#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L ++//DAGB1_WR_GMI_CNTL ++#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 ++#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 ++#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd ++#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL ++#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L ++#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L ++#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L ++//DAGB1_WR_ADDR_DAGB ++#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB1_WR_OUTPUT_DAGB_MAX_BURST ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L ++#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L ++//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L ++#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L ++//DAGB1_WR_CGTT_CLK_CTRL ++#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB1_L1TLB_WR_CGTT_CLK_CTRL ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB1_ATCVM_WR_CGTT_CLK_CTRL ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L ++#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L ++//DAGB1_WR_ADDR_DAGB_MAX_BURST0 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB1_WR_ADDR_DAGB_MAX_BURST1 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB1_WR_DATA_DAGB ++#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 ++#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 ++#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 ++#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 ++#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L ++#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L ++#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L ++#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L ++//DAGB1_WR_DATA_DAGB_MAX_BURST0 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L ++//DAGB1_WR_DATA_DAGB_LAZY_TIMER0 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L ++//DAGB1_WR_DATA_DAGB_MAX_BURST1 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L ++#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L ++//DAGB1_WR_DATA_DAGB_LAZY_TIMER1 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L ++#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L ++//DAGB1_WR_VC0_CNTL ++#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_VC1_CNTL ++#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_VC2_CNTL ++#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_VC3_CNTL ++#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_VC4_CNTL ++#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_VC5_CNTL ++#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_VC6_CNTL ++#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_VC7_CNTL ++#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 ++#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb ++#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc ++#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 ++#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 ++#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 ++#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 ++#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL ++#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L ++#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L ++#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L ++#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L ++#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L ++#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L ++#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L ++//DAGB1_WR_CNTL_MISC ++#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 ++#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd ++#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 ++#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 ++#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 ++#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL ++#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L ++#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L ++#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L ++#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L ++#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L ++//DAGB1_WR_TLB_CREDIT ++#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 ++#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 ++#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa ++#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf ++#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 ++#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 ++#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL ++#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L ++#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L ++#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L ++#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L ++#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L ++//DAGB1_WR_DATA_CREDIT ++#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 ++#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 ++#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 ++#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 ++#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL ++#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L ++#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L ++#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L ++//DAGB1_WR_MISC_CREDIT ++#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 ++#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 ++#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 ++#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 ++#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL ++#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L ++#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L ++#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L ++//DAGB1_WRCLI_ASK_PENDING ++#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI_GO_PENDING ++#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI_GBLSEND_PENDING ++#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI_TLB_PENDING ++#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI_OARB_PENDING ++#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI_OSD_PENDING ++#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI_DBUS_ASK_PENDING ++#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_WRCLI_DBUS_GO_PENDING ++#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 ++#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL ++//DAGB1_DAGB_DLY ++#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 ++#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 ++#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 ++#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL ++#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L ++#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L ++//DAGB1_CNTL_MISC ++#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 ++#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 ++#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 ++#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 ++#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc ++#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf ++#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 ++#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 ++#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 ++#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e ++#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L ++#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L ++#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L ++#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L ++#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L ++#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L ++#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L ++#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L ++#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L ++#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L ++//DAGB1_CNTL_MISC2 ++#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 ++#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 ++#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 ++#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 ++#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 ++#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 ++#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 ++#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 ++#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 ++#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 ++#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa ++#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L ++#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L ++#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L ++#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L ++#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L ++#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L ++#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L ++#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L ++#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L ++#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L ++#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L ++//DAGB1_FIFO_EMPTY ++#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 ++#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL ++//DAGB1_FIFO_FULL ++#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 ++#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL ++//DAGB1_WR_CREDITS_FULL ++#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 ++#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL ++//DAGB1_RD_CREDITS_FULL ++#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 ++#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL ++//DAGB1_PERFCOUNTER_LO ++#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//DAGB1_PERFCOUNTER_HI ++#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//DAGB1_PERFCOUNTER0_CFG ++#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//DAGB1_PERFCOUNTER1_CFG ++#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//DAGB1_PERFCOUNTER2_CFG ++#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//DAGB1_PERFCOUNTER_RSLT_CNTL ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++//DAGB1_RESERVE0 ++#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE1 ++#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE2 ++#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE3 ++#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE4 ++#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE5 ++#define DAGB1_RESERVE5__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE6 ++#define DAGB1_RESERVE6__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE7 ++#define DAGB1_RESERVE7__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE8 ++#define DAGB1_RESERVE8__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE9 ++#define DAGB1_RESERVE9__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE10 ++#define DAGB1_RESERVE10__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE11 ++#define DAGB1_RESERVE11__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE12 ++#define DAGB1_RESERVE12__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE13 ++#define DAGB1_RESERVE13__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE14 ++#define DAGB1_RESERVE14__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE14__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE15 ++#define DAGB1_RESERVE15__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE15__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE16 ++#define DAGB1_RESERVE16__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE16__RESERVE_MASK 0xFFFFFFFFL ++//DAGB1_RESERVE17 ++#define DAGB1_RESERVE17__RESERVE__SHIFT 0x0 ++#define DAGB1_RESERVE17__RESERVE_MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: mmhub_ea_mmeadec ++//MMEA0_DRAM_RD_CLI2GRP_MAP0 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_RD_CLI2GRP_MAP1 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_WR_CLI2GRP_MAP0 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_WR_CLI2GRP_MAP1 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_DRAM_RD_GRP2VC_MAP ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//MMEA0_DRAM_WR_GRP2VC_MAP ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//MMEA0_DRAM_RD_LAZY ++#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++//MMEA0_DRAM_WR_LAZY ++#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++//MMEA0_DRAM_RD_CAM_CNTL ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++//MMEA0_DRAM_WR_CAM_CNTL ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++//MMEA0_DRAM_PAGE_BURST ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//MMEA0_DRAM_RD_PRI_AGE ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_DRAM_WR_PRI_AGE ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_DRAM_RD_PRI_QUEUING ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_WR_PRI_QUEUING ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_RD_PRI_FIXED ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_WR_PRI_FIXED ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_DRAM_RD_PRI_URGENCY ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_DRAM_WR_PRI_URGENCY ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_DRAM_RD_PRI_QUANT_PRI1 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_RD_PRI_QUANT_PRI2 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_RD_PRI_QUANT_PRI3 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_WR_PRI_QUANT_PRI1 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_WR_PRI_QUANT_PRI2 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_DRAM_WR_PRI_QUANT_PRI3 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_ADDRNORM_BASE_ADDR0 ++#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 ++#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 ++#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L ++#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L ++#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L ++#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_LIMIT_ADDR0 ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L ++#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_BASE_ADDR1 ++#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 ++#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 ++#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L ++#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L ++#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L ++#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_LIMIT_ADDR1 ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L ++#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L ++//MMEA0_ADDRNORM_OFFSET_ADDR1 ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L ++#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L ++//MMEA0_ADDRNORMDRAM_HOLE_CNTL ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L ++#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L ++//MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG ++#define MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0 ++#define MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL ++//MMEA0_ADDRDEC_BANK_CFG ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL ++#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L ++#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L ++//MMEA0_ADDRDEC_MISC_CFG ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L ++#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L ++#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L ++#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L ++#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L ++#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_PC ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L ++//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL ++//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDECDRAM_HARVEST_ENABLE ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L ++#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L ++//MMEA0_ADDRDEC0_BASE_ADDR_CS0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_CS1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_CS2 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_CS3 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_CS01 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_CS23 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC0_ADDR_CFG_CS01 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC0_ADDR_CFG_CS23 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC0_ADDR_SEL_CS01 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_ADDR_SEL_CS23 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC0_RM_SEL_CS01 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC0_RM_SEL_CS23 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC0_RM_SEL_SECCS01 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC0_RM_SEL_SECCS23 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_BASE_ADDR_CS0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_CS1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_CS2 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_CS3 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_CS01 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_CS23 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA0_ADDRDEC1_ADDR_CFG_CS01 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC1_ADDR_CFG_CS23 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//MMEA0_ADDRDEC1_ADDR_SEL_CS01 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_ADDR_SEL_CS23 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//MMEA0_ADDRDEC1_RM_SEL_CS01 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_RM_SEL_CS23 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_RM_SEL_SECCS01 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_ADDRDEC1_RM_SEL_SECCS23 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA0_IO_RD_CLI2GRP_MAP0 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_IO_RD_CLI2GRP_MAP1 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_IO_WR_CLI2GRP_MAP0 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA0_IO_WR_CLI2GRP_MAP1 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA0_IO_RD_COMBINE_FLUSH ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//MMEA0_IO_WR_COMBINE_FLUSH ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//MMEA0_IO_GROUP_BURST ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//MMEA0_IO_RD_PRI_AGE ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_IO_WR_PRI_AGE ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA0_IO_RD_PRI_QUEUING ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_WR_PRI_QUEUING ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_RD_PRI_FIXED ++#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_WR_PRI_FIXED ++#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA0_IO_RD_PRI_URGENCY ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_IO_WR_PRI_URGENCY ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA0_IO_RD_PRI_URGENCY_MASK ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L ++#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L ++//MMEA0_IO_WR_PRI_URGENCY_MASK ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L ++#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L ++//MMEA0_IO_RD_PRI_QUANT_PRI1 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_RD_PRI_QUANT_PRI2 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_RD_PRI_QUANT_PRI3 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_WR_PRI_QUANT_PRI1 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_WR_PRI_QUANT_PRI2 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_IO_WR_PRI_QUANT_PRI3 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA0_SDP_ARB_DRAM ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 ++#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL ++#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L ++#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L ++#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L ++//MMEA0_SDP_ARB_FINAL ++#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 ++#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 ++#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa ++#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 ++#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 ++#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a ++#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL ++#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L ++#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L ++#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L ++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L ++#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L ++#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L ++//MMEA0_SDP_DRAM_PRIORITY ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//MMEA0_SDP_IO_PRIORITY ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//MMEA0_SDP_CREDITS ++#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 ++#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 ++#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 ++#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL ++#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L ++#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L ++//MMEA0_SDP_TAG_RESERVE0 ++#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 ++#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 ++#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 ++#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 ++#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL ++#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L ++#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L ++#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L ++//MMEA0_SDP_TAG_RESERVE1 ++#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 ++#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 ++#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 ++#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 ++#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL ++#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L ++#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L ++#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L ++//MMEA0_SDP_VCC_RESERVE0 ++#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//MMEA0_SDP_VCC_RESERVE1 ++#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//MMEA0_SDP_VCD_RESERVE0 ++#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//MMEA0_SDP_VCD_RESERVE1 ++#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//MMEA0_SDP_REQ_CNTL ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 ++#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 ++#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L ++#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L ++#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L ++#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L ++//MMEA0_MISC ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 ++#define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 ++#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 ++#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 ++#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa ++#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc ++#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L ++#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L ++#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L ++#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L ++#define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L ++#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L ++#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L ++#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L ++#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L ++#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L ++#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L ++#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L ++#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L ++//MMEA0_LATENCY_SAMPLING ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L ++#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L ++//MMEA0_PERFCOUNTER_LO ++#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MMEA0_PERFCOUNTER_HI ++#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//MMEA0_PERFCOUNTER0_CFG ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MMEA0_PERFCOUNTER1_CFG ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MMEA0_PERFCOUNTER_RSLT_CNTL ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++//MMEA0_EDC_CNT ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc ++#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe ++#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 ++#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 ++#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 ++#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 ++#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 ++#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a ++#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L ++#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L ++#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L ++#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L ++#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L ++#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L ++#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L ++#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L ++#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L ++//MMEA0_EDC_CNT2 ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc ++#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L ++#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L ++//MMEA0_DSM_CNTL ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L ++#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L ++//MMEA0_DSM_CNTLA ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++//MMEA0_DSM_CNTLB ++//MMEA0_DSM_CNTL2 ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L ++//MMEA0_DSM_CNTL2A ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++//MMEA0_DSM_CNTL2B ++//MMEA0_CGTT_CLK_CTRL ++#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 ++#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f ++#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L ++#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L ++#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L ++//MMEA0_EDC_MODE ++#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 ++#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 ++#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 ++#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d ++#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f ++#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L ++#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L ++#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L ++#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L ++#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L ++//MMEA0_ERR_STATUS ++#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 ++#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa ++#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb ++#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc ++#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd ++#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL ++#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L ++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L ++#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L ++#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L ++#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L ++//MMEA0_MISC2 ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 ++#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L ++#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL ++#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L ++#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L ++//MMEA1_DRAM_RD_CLI2GRP_MAP0 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA1_DRAM_RD_CLI2GRP_MAP1 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA1_DRAM_WR_CLI2GRP_MAP0 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA1_DRAM_WR_CLI2GRP_MAP1 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA1_DRAM_RD_GRP2VC_MAP ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//MMEA1_DRAM_WR_GRP2VC_MAP ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L ++#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L ++//MMEA1_DRAM_RD_LAZY ++#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++//MMEA1_DRAM_WR_LAZY ++#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 ++#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 ++#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 ++#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 ++#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc ++#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 ++#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L ++#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L ++#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L ++#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L ++#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L ++#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L ++//MMEA1_DRAM_RD_CAM_CNTL ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++//MMEA1_DRAM_WR_CAM_CNTL ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L ++#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L ++#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L ++//MMEA1_DRAM_PAGE_BURST ++#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//MMEA1_DRAM_RD_PRI_AGE ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA1_DRAM_WR_PRI_AGE ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA1_DRAM_RD_PRI_QUEUING ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_DRAM_WR_PRI_QUEUING ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_DRAM_RD_PRI_FIXED ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_DRAM_WR_PRI_FIXED ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_DRAM_RD_PRI_URGENCY ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA1_DRAM_WR_PRI_URGENCY ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA1_DRAM_RD_PRI_QUANT_PRI1 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_DRAM_RD_PRI_QUANT_PRI2 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_DRAM_RD_PRI_QUANT_PRI3 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_DRAM_WR_PRI_QUANT_PRI1 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_DRAM_WR_PRI_QUANT_PRI2 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_DRAM_WR_PRI_QUANT_PRI3 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_ADDRNORM_BASE_ADDR0 ++#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 ++#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 ++#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 ++#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc ++#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L ++#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L ++#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L ++#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L ++//MMEA1_ADDRNORM_LIMIT_ADDR0 ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L ++#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L ++//MMEA1_ADDRNORM_BASE_ADDR1 ++#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 ++#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 ++#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 ++#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 ++#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc ++#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L ++#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L ++#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L ++#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L ++#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L ++//MMEA1_ADDRNORM_LIMIT_ADDR1 ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L ++#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L ++//MMEA1_ADDRNORM_OFFSET_ADDR1 ++#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 ++#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 ++#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L ++#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L ++//MMEA1_ADDRNORMDRAM_HOLE_CNTL ++#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 ++#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 ++#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L ++#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L ++//MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG ++#define MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0 ++#define MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL ++//MMEA1_ADDRDEC_BANK_CFG ++#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 ++#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 ++#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL ++#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L ++#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L ++//MMEA1_ADDRDEC_MISC_CFG ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 ++#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 ++#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 ++#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc ++#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 ++#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 ++#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 ++#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a ++#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L ++#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L ++#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L ++#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L ++#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L ++#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L ++#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L ++#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L ++#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L ++#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L ++//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L ++//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L ++//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L ++//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L ++//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L ++//MMEA1_ADDRDECDRAM_ADDR_HASH_PC ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L ++//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL ++//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDECDRAM_HARVEST_ENABLE ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L ++#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L ++//MMEA1_ADDRDEC0_BASE_ADDR_CS0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_BASE_ADDR_CS1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_BASE_ADDR_CS2 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_BASE_ADDR_CS3 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_ADDR_MASK_CS01 ++#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_ADDR_MASK_CS23 ++#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 ++#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 ++#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC0_ADDR_CFG_CS01 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//MMEA1_ADDRDEC0_ADDR_CFG_CS23 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//MMEA1_ADDRDEC0_ADDR_SEL_CS01 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//MMEA1_ADDRDEC0_ADDR_SEL_CS23 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//MMEA1_ADDRDEC0_COL_SEL_LO_CS01 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//MMEA1_ADDRDEC0_COL_SEL_LO_CS23 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//MMEA1_ADDRDEC0_COL_SEL_HI_CS01 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//MMEA1_ADDRDEC0_COL_SEL_HI_CS23 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//MMEA1_ADDRDEC0_RM_SEL_CS01 ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_ADDRDEC0_RM_SEL_CS23 ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_ADDRDEC0_RM_SEL_SECCS01 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_ADDRDEC0_RM_SEL_SECCS23 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_ADDRDEC1_BASE_ADDR_CS0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_BASE_ADDR_CS1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_BASE_ADDR_CS2 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_BASE_ADDR_CS3 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L ++#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_ADDR_MASK_CS01 ++#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_ADDR_MASK_CS23 ++#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 ++#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 ++#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 ++#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL ++//MMEA1_ADDRDEC1_ADDR_CFG_CS01 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L ++//MMEA1_ADDRDEC1_ADDR_CFG_CS23 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L ++#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L ++//MMEA1_ADDRDEC1_ADDR_SEL_CS01 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L ++//MMEA1_ADDRDEC1_ADDR_SEL_CS23 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L ++#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L ++//MMEA1_ADDRDEC1_COL_SEL_LO_CS01 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L ++//MMEA1_ADDRDEC1_COL_SEL_LO_CS23 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L ++#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L ++//MMEA1_ADDRDEC1_COL_SEL_HI_CS01 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L ++//MMEA1_ADDRDEC1_COL_SEL_HI_CS23 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L ++#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L ++//MMEA1_ADDRDEC1_RM_SEL_CS01 ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_ADDRDEC1_RM_SEL_CS23 ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_ADDRDEC1_RM_SEL_SECCS01 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_ADDRDEC1_RM_SEL_SECCS23 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L ++#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L ++//MMEA1_IO_RD_CLI2GRP_MAP0 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA1_IO_RD_CLI2GRP_MAP1 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA1_IO_WR_CLI2GRP_MAP0 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L ++#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L ++//MMEA1_IO_WR_CLI2GRP_MAP1 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L ++#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L ++//MMEA1_IO_RD_COMBINE_FLUSH ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//MMEA1_IO_WR_COMBINE_FLUSH ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L ++#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L ++//MMEA1_IO_GROUP_BURST ++#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 ++#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 ++#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 ++#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 ++#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL ++#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L ++#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L ++#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L ++//MMEA1_IO_RD_PRI_AGE ++#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA1_IO_WR_PRI_AGE ++#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 ++#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 ++#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 ++#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc ++#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf ++#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 ++#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 ++#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L ++#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L ++#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L ++#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L ++#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L ++#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L ++#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L ++#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L ++//MMEA1_IO_RD_PRI_QUEUING ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_IO_WR_PRI_QUEUING ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_IO_RD_PRI_FIXED ++#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_IO_WR_PRI_FIXED ++#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L ++//MMEA1_IO_RD_PRI_URGENCY ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA1_IO_WR_PRI_URGENCY ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L ++#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L ++//MMEA1_IO_RD_PRI_URGENCY_MASK ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L ++#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L ++//MMEA1_IO_WR_PRI_URGENCY_MASK ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L ++#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L ++//MMEA1_IO_RD_PRI_QUANT_PRI1 ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_IO_RD_PRI_QUANT_PRI2 ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_IO_RD_PRI_QUANT_PRI3 ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_IO_WR_PRI_QUANT_PRI1 ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_IO_WR_PRI_QUANT_PRI2 ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_IO_WR_PRI_QUANT_PRI3 ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L ++#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L ++//MMEA1_SDP_ARB_DRAM ++#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 ++#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 ++#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 ++#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL ++#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L ++#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L ++#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L ++//MMEA1_SDP_ARB_FINAL ++#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 ++#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 ++#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa ++#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 ++#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 ++#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a ++#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL ++#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L ++#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L ++#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L ++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L ++#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L ++#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L ++//MMEA1_SDP_DRAM_PRIORITY ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//MMEA1_SDP_IO_PRIORITY ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L ++#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L ++#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L ++//MMEA1_SDP_CREDITS ++#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 ++#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 ++#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 ++#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL ++#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L ++#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L ++//MMEA1_SDP_TAG_RESERVE0 ++#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 ++#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 ++#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 ++#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 ++#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL ++#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L ++#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L ++#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L ++//MMEA1_SDP_TAG_RESERVE1 ++#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 ++#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 ++#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 ++#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 ++#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL ++#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L ++#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L ++#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L ++//MMEA1_SDP_VCC_RESERVE0 ++#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//MMEA1_SDP_VCC_RESERVE1 ++#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//MMEA1_SDP_VCD_RESERVE0 ++#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 ++#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 ++#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc ++#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 ++#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 ++#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL ++#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L ++#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L ++#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L ++#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L ++//MMEA1_SDP_VCD_RESERVE1 ++#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 ++#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 ++#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc ++#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f ++#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL ++#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L ++#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L ++#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L ++//MMEA1_SDP_REQ_CNTL ++#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 ++#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 ++#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 ++#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 ++#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 ++#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L ++#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L ++#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L ++#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L ++#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L ++//MMEA1_MISC ++#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 ++#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 ++#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 ++#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 ++#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 ++#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 ++#define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 ++#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 ++#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 ++#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa ++#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc ++#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe ++#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 ++#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 ++#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 ++#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 ++#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 ++#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 ++#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L ++#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L ++#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L ++#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L ++#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L ++#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L ++#define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L ++#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L ++#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L ++#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L ++#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L ++#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L ++#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L ++#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L ++#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L ++#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L ++#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L ++#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L ++//MMEA1_LATENCY_SAMPLING ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L ++#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L ++//MMEA1_PERFCOUNTER_LO ++#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MMEA1_PERFCOUNTER_HI ++#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++//MMEA1_PERFCOUNTER0_CFG ++#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MMEA1_PERFCOUNTER1_CFG ++#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MMEA1_PERFCOUNTER_RSLT_CNTL ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++//MMEA1_EDC_CNT ++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc ++#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe ++#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 ++#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 ++#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 ++#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 ++#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 ++#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a ++#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c ++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L ++#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L ++#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L ++#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L ++#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L ++#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L ++#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L ++#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L ++#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L ++//MMEA1_EDC_CNT2 ++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc ++#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe ++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L ++#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L ++//MMEA1_DSM_CNTL ++#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 ++#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 ++#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L ++#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L ++//MMEA1_DSM_CNTLA ++#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 ++#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 ++#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 ++#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 ++#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 ++#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 ++#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 ++#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb ++#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc ++#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe ++#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf ++#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 ++#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 ++#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 ++#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L ++#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L ++#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L ++#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L ++#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L ++#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L ++#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L ++#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L ++#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L ++#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L ++#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L ++#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L ++#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L ++#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L ++//MMEA1_DSM_CNTLB ++//MMEA1_DSM_CNTL2 ++#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 ++#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 ++#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a ++#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L ++#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L ++#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L ++//MMEA1_DSM_CNTL2A ++#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 ++#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 ++#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 ++#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 ++#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 ++#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 ++#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 ++#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb ++#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc ++#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe ++#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf ++#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 ++#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 ++#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 ++#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L ++#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L ++#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L ++#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L ++#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L ++#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L ++#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L ++#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L ++#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L ++#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L ++#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L ++#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L ++#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L ++#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L ++//MMEA1_DSM_CNTL2B ++//MMEA1_CGTT_CLK_CTRL ++#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 ++#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 ++#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 ++#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f ++#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L ++#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L ++#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L ++#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L ++#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L ++//MMEA1_EDC_MODE ++#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 ++#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 ++#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 ++#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d ++#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f ++#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L ++#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L ++#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L ++#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L ++#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L ++//MMEA1_ERR_STATUS ++#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 ++#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 ++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 ++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa ++#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb ++#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc ++#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd ++#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL ++#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L ++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L ++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L ++#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L ++#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L ++#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L ++//MMEA1_MISC2 ++#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 ++#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 ++#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 ++#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 ++#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc ++#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L ++#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L ++#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL ++#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L ++#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L ++ ++ ++// addressBlock: mmhub_pctldec ++//PCTL_MISC ++#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 ++#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 ++#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 ++#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb ++#define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc ++#define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd ++#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe ++#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L ++#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L ++#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L ++#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L ++#define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L ++#define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L ++#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L ++//PCTL_MMHUB_DEEPSLEEP ++#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 ++#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 ++#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 ++#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 ++#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 ++#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 ++#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 ++#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 ++#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 ++#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 ++#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa ++#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb ++#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc ++#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd ++#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe ++#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf ++#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 ++#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f ++#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L ++#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L ++#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L ++#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L ++#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L ++#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L ++#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L ++#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L ++#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L ++#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L ++#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L ++#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L ++#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L ++#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L ++#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L ++#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L ++#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L ++#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L ++//PCTL_MMHUB_DEEPSLEEP_OVERRIDE ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L ++#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L ++//PCTL_PG_IGNORE_DEEPSLEEP ++#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 ++#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L ++#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L ++//PCTL_PG_DAGB ++#define PCTL_PG_DAGB__DS0__SHIFT 0x0 ++#define PCTL_PG_DAGB__DS1__SHIFT 0x1 ++#define PCTL_PG_DAGB__DS2__SHIFT 0x2 ++#define PCTL_PG_DAGB__DS3__SHIFT 0x3 ++#define PCTL_PG_DAGB__DS4__SHIFT 0x4 ++#define PCTL_PG_DAGB__DS5__SHIFT 0x5 ++#define PCTL_PG_DAGB__DS6__SHIFT 0x6 ++#define PCTL_PG_DAGB__DS7__SHIFT 0x7 ++#define PCTL_PG_DAGB__DS8__SHIFT 0x8 ++#define PCTL_PG_DAGB__DS9__SHIFT 0x9 ++#define PCTL_PG_DAGB__DS10__SHIFT 0xa ++#define PCTL_PG_DAGB__DS11__SHIFT 0xb ++#define PCTL_PG_DAGB__DS12__SHIFT 0xc ++#define PCTL_PG_DAGB__DS13__SHIFT 0xd ++#define PCTL_PG_DAGB__DS14__SHIFT 0xe ++#define PCTL_PG_DAGB__DS15__SHIFT 0xf ++#define PCTL_PG_DAGB__DS16__SHIFT 0x10 ++#define PCTL_PG_DAGB__DS0_MASK 0x00000001L ++#define PCTL_PG_DAGB__DS1_MASK 0x00000002L ++#define PCTL_PG_DAGB__DS2_MASK 0x00000004L ++#define PCTL_PG_DAGB__DS3_MASK 0x00000008L ++#define PCTL_PG_DAGB__DS4_MASK 0x00000010L ++#define PCTL_PG_DAGB__DS5_MASK 0x00000020L ++#define PCTL_PG_DAGB__DS6_MASK 0x00000040L ++#define PCTL_PG_DAGB__DS7_MASK 0x00000080L ++#define PCTL_PG_DAGB__DS8_MASK 0x00000100L ++#define PCTL_PG_DAGB__DS9_MASK 0x00000200L ++#define PCTL_PG_DAGB__DS10_MASK 0x00000400L ++#define PCTL_PG_DAGB__DS11_MASK 0x00000800L ++#define PCTL_PG_DAGB__DS12_MASK 0x00001000L ++#define PCTL_PG_DAGB__DS13_MASK 0x00002000L ++#define PCTL_PG_DAGB__DS14_MASK 0x00004000L ++#define PCTL_PG_DAGB__DS15_MASK 0x00008000L ++#define PCTL_PG_DAGB__DS16_MASK 0x00010000L ++//PCTL0_RENG_RAM_INDEX ++#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 ++#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL ++//PCTL0_RENG_RAM_DATA ++#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 ++#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL ++//PCTL0_RENG_EXECUTE ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L ++#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L ++//PCTL0_MISC ++#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb ++#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc ++#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf ++#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 ++#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L ++#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L ++#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L ++#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE1 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE2 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE3 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_RANGE4 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L ++//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL ++#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L ++//PCTL1_RENG_RAM_INDEX ++#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 ++#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL ++//PCTL1_RENG_RAM_DATA ++#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 ++#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL ++//PCTL1_RENG_EXECUTE ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L ++#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L ++//PCTL1_MISC ++#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa ++#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb ++#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe ++#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf ++#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 ++#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L ++#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L ++#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L ++#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L ++#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE1 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE2 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE3 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_RANGE4 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L ++//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL ++#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L ++//PCTL2_RENG_RAM_INDEX ++#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 ++#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL ++//PCTL2_RENG_RAM_DATA ++#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 ++#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL ++//PCTL2_RENG_EXECUTE ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L ++#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L ++//PCTL2_MISC ++#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa ++#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb ++#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe ++#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf ++#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 ++#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L ++#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L ++#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L ++#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L ++#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE1 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE2 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE3 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_RANGE4 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L ++//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL ++#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L ++ ++ ++// addressBlock: mmhub_l1tlb_vml1dec ++//MC_VM_MX_L1_TLB0_STATUS ++#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MC_VM_MX_L1_TLB1_STATUS ++#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MC_VM_MX_L1_TLB2_STATUS ++#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MC_VM_MX_L1_TLB3_STATUS ++#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MC_VM_MX_L1_TLB4_STATUS ++#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MC_VM_MX_L1_TLB5_STATUS ++#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MC_VM_MX_L1_TLB6_STATUS ++#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++//MC_VM_MX_L1_TLB7_STATUS ++#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L ++ ++ ++// addressBlock: mmhub_l1tlb_vml1pldec ++//MC_VM_MX_L1_PERFCOUNTER0_CFG ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_MX_L1_PERFCOUNTER1_CFG ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_MX_L1_PERFCOUNTER2_CFG ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_MX_L1_PERFCOUNTER3_CFG ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++ ++// addressBlock: mmhub_l1tlb_vml1prdec ++//MC_VM_MX_L1_PERFCOUNTER_LO ++#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MC_VM_MX_L1_PERFCOUNTER_HI ++#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: mmhub_utcl2_atcl2dec ++//ATC_L2_CNTL ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 ++#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 ++#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L ++#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L ++#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L ++//ATC_L2_CNTL2 ++#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 ++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 ++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf ++#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L ++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L ++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L ++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L ++//ATC_L2_CACHE_DATA0 ++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 ++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 ++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 ++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L ++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L ++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL ++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L ++//ATC_L2_CACHE_DATA1 ++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL ++//ATC_L2_CACHE_DATA2 ++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL ++//ATC_L2_CNTL3 ++#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 ++#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 ++#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 ++#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L ++#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L ++#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L ++//ATC_L2_STATUS ++#define ATC_L2_STATUS__BUSY__SHIFT 0x0 ++#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 ++#define ATC_L2_STATUS__BUSY_MASK 0x00000001L ++#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL ++//ATC_L2_STATUS2 ++#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 ++#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 ++#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL ++#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L ++//ATC_L2_MISC_CG ++#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 ++#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 ++#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L ++#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L ++#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L ++//ATC_L2_MEM_POWER_LS ++#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 ++#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 ++#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL ++#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L ++//ATC_L2_CGTT_CLK_CTRL ++#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++ ++ ++// addressBlock: mmhub_utcl2_vml2pfdec ++//VM_L2_CNTL ++#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 ++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 ++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 ++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 ++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 ++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 ++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa ++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb ++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc ++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf ++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 ++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 ++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 ++#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a ++#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L ++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L ++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL ++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L ++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L ++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L ++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L ++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L ++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L ++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L ++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L ++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L ++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L ++#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L ++//VM_L2_CNTL2 ++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 ++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 ++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 ++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 ++#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 ++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a ++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c ++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L ++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L ++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L ++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L ++#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L ++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L ++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L ++//VM_L2_CNTL3 ++#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf ++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 ++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 ++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d ++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e ++#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f ++#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L ++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L ++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L ++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L ++#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L ++//VM_L2_STATUS ++#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 ++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 ++#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 ++#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 ++#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 ++#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 ++#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 ++#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L ++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL ++#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L ++#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L ++#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L ++#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L ++#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L ++//VM_DUMMY_PAGE_FAULT_CNTL ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL ++//VM_DUMMY_PAGE_FAULT_ADDR_LO32 ++#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 ++#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//VM_DUMMY_PAGE_FAULT_ADDR_HI32 ++#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 ++#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL ++//VM_L2_PROTECTION_FAULT_CNTL ++#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 ++#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 ++#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 ++#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 ++#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 ++#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 ++#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb ++#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd ++#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f ++#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L ++#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L ++#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L ++#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L ++#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L ++#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L ++#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L ++#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L ++#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L ++#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L ++#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L ++#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L ++//VM_L2_PROTECTION_FAULT_CNTL2 ++#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 ++#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 ++#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL ++#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L ++#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L ++#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L ++//VM_L2_PROTECTION_FAULT_MM_CNTL3 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_MM_CNTL4 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_STATUS ++#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 ++#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 ++#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 ++#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 ++#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 ++#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 ++#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 ++#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 ++#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 ++#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L ++#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL ++#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L ++#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L ++#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L ++#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L ++#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L ++#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L ++#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L ++#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L ++//VM_L2_PROTECTION_FAULT_ADDR_LO32 ++#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_ADDR_HI32 ++#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL ++//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL ++//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 ++#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL ++//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL ++//VM_L2_CNTL4 ++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 ++#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 ++#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 ++#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 ++#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 ++#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c ++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL ++#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L ++#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L ++#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L ++#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L ++#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L ++//VM_L2_MM_GROUP_RT_CLASSES ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L ++#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L ++//VM_L2_BANK_SELECT_RESERVED_CID ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa ++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L ++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L ++//VM_L2_BANK_SELECT_RESERVED_CID2 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa ++#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L ++#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L ++#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L ++//VM_L2_CACHE_PARITY_CNTL ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L ++#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L ++#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L ++//VM_L2_CGTT_CLK_CTRL ++#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++ ++ ++// addressBlock: mmhub_utcl2_vml2vcdec ++//VM_CONTEXT0_CNTL ++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT1_CNTL ++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT2_CNTL ++#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT3_CNTL ++#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT4_CNTL ++#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT5_CNTL ++#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT6_CNTL ++#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT7_CNTL ++#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT8_CNTL ++#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT9_CNTL ++#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT10_CNTL ++#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT11_CNTL ++#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT12_CNTL ++#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT13_CNTL ++#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT14_CNTL ++#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXT15_CNTL ++#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 ++#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 ++#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L ++#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L ++#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L ++#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L ++#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L ++#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L ++#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L ++#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L ++#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L ++#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L ++#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L ++//VM_CONTEXTS_DISABLE ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L ++//VM_INVALIDATE_ENG0_SEM ++#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG1_SEM ++#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG2_SEM ++#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG3_SEM ++#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG4_SEM ++#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG5_SEM ++#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG6_SEM ++#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG7_SEM ++#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG8_SEM ++#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG9_SEM ++#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG10_SEM ++#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG11_SEM ++#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG12_SEM ++#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG13_SEM ++#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG14_SEM ++#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG15_SEM ++#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG16_SEM ++#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG17_SEM ++#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L ++//VM_INVALIDATE_ENG0_REQ ++#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG1_REQ ++#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG2_REQ ++#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG3_REQ ++#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG4_REQ ++#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG5_REQ ++#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG6_REQ ++#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG7_REQ ++#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG8_REQ ++#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG9_REQ ++#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG10_REQ ++#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG11_REQ ++#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG12_REQ ++#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG13_REQ ++#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG14_REQ ++#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG15_REQ ++#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG16_REQ ++#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG17_REQ ++#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 ++#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 ++#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L ++#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L ++#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L ++//VM_INVALIDATE_ENG0_ACK ++#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG1_ACK ++#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG2_ACK ++#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG3_ACK ++#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG4_ACK ++#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG5_ACK ++#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG6_ACK ++#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG7_ACK ++#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG8_ACK ++#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG9_ACK ++#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG10_ACK ++#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG11_ACK ++#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG12_ACK ++#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG13_ACK ++#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG14_ACK ++#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG15_ACK ++#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG16_ACK ++#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG17_ACK ++#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 ++#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL ++#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L ++//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL ++//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 ++#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL ++//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL ++//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL ++ ++ ++// addressBlock: mmhub_utcl2_vml2pldec ++//MC_VM_L2_PERFCOUNTER0_CFG ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER1_CFG ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER2_CFG ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER3_CFG ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER4_CFG ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER5_CFG ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER6_CFG ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER7_CFG ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L ++#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L ++#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L ++//MC_VM_L2_PERFCOUNTER_RSLT_CNTL ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++ ++// addressBlock: mmhub_utcl2_vml2prdec ++//MC_VM_L2_PERFCOUNTER_LO ++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//MC_VM_L2_PERFCOUNTER_HI ++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: mmhub_utcl2_vmsharedhvdec ++//MC_VM_FB_SIZE_OFFSET_VF0 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF1 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF2 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF3 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF4 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF5 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF6 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF7 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF8 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF9 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF10 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF11 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF12 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF13 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF14 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L ++//MC_VM_FB_SIZE_OFFSET_VF15 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L ++//VM_IOMMU_MMIO_CNTRL_1 ++#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 ++#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L ++//MC_VM_MARC_BASE_LO_0 ++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_LO_1 ++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_LO_2 ++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_LO_3 ++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L ++//MC_VM_MARC_BASE_HI_0 ++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL ++//MC_VM_MARC_BASE_HI_1 ++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL ++//MC_VM_MARC_BASE_HI_2 ++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL ++//MC_VM_MARC_BASE_HI_3 ++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_LO_0 ++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_LO_1 ++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_LO_2 ++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_LO_3 ++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L ++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L ++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L ++//MC_VM_MARC_RELOC_HI_0 ++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_HI_1 ++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_HI_2 ++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL ++//MC_VM_MARC_RELOC_HI_3 ++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_LO_0 ++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_LO_1 ++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_LO_2 ++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_LO_3 ++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L ++//MC_VM_MARC_LEN_HI_0 ++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_HI_1 ++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_HI_2 ++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL ++//MC_VM_MARC_LEN_HI_3 ++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL ++//VM_IOMMU_CONTROL_REGISTER ++#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 ++#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L ++//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER ++#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd ++#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L ++//VM_PCIE_ATS_CNTL ++#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 ++#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L ++#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_0 ++#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_1 ++#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_2 ++#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_3 ++#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_4 ++#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_5 ++#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_6 ++#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_7 ++#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_8 ++#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_9 ++#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_10 ++#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_11 ++#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_12 ++#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_13 ++#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_14 ++#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L ++//VM_PCIE_ATS_CNTL_VF_15 ++#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f ++#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L ++//UTCL2_CGTT_CLK_CTRL ++#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc ++#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf ++#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 ++#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L ++#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L ++#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L ++#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L ++//MC_SHARED_ACTIVE_FCN_ID ++#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//MC_VM_XGMI_GPUIOV_ENABLE ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L ++#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L ++ ++ ++// addressBlock: mmhub_utcl2_vmsharedpfdec ++//MC_VM_NB_MMIOBASE ++#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 ++#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL ++//MC_VM_NB_MMIOLIMIT ++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 ++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL ++//MC_VM_NB_PCI_CTRL ++#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 ++#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L ++//MC_VM_NB_PCI_ARB ++#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 ++#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L ++//MC_VM_NB_TOP_OF_DRAM_SLOT1 ++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 ++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L ++//MC_VM_NB_LOWER_TOP_OF_DRAM2 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L ++//MC_VM_NB_UPPER_TOP_OF_DRAM2 ++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 ++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL ++//MC_VM_FB_OFFSET ++#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 ++#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL ++//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL ++//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL ++//MC_VM_STEERING ++#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 ++#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L ++//MC_SHARED_VIRT_RESET_REQ ++#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL ++#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//MC_MEM_POWER_LS ++#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 ++#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 ++#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL ++#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L ++//MC_VM_CACHEABLE_DRAM_ADDRESS_START ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_CACHEABLE_DRAM_ADDRESS_END ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 ++#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_APT_CNTL ++#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 ++#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 ++#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L ++#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L ++//MC_VM_LOCAL_HBM_ADDRESS_START ++#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 ++#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_LOCAL_HBM_ADDRESS_END ++#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 ++#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL ++//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL ++#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 ++#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L ++//MC_VM_XGMI_LFB_CNTL ++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 ++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x3 ++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L ++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000038L ++//MC_VM_XGMI_LFB_SIZE ++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 ++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL ++ ++ ++// addressBlock: mmhub_utcl2_vmsharedvcdec ++//MC_VM_FB_LOCATION_BASE ++#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 ++#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL ++//MC_VM_FB_LOCATION_TOP ++#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 ++#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL ++//MC_VM_AGP_TOP ++#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 ++#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL ++//MC_VM_AGP_BOT ++#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 ++#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL ++//MC_VM_AGP_BASE ++#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 ++#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL ++//MC_VM_SYSTEM_APERTURE_LOW_ADDR ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL ++//MC_VM_SYSTEM_APERTURE_HIGH_ADDR ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL ++//MC_VM_MX_L1_TLB_CNTL ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 ++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 ++#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb ++#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L ++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L ++#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L ++#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L ++ ++ ++// addressBlock: mmhub_utcl2_atcl2pfcntrdec ++//ATC_L2_PERFCOUNTER_LO ++#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL ++//ATC_L2_PERFCOUNTER_HI ++#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL ++#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L ++ ++ ++// addressBlock: mmhub_utcl2_atcl2pfcntldec ++//ATC_L2_PERFCOUNTER0_CFG ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L ++#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L ++#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L ++//ATC_L2_PERFCOUNTER1_CFG ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L ++#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L ++#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L ++#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L ++//ATC_L2_PERFCOUNTER_RSLT_CNTL ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L ++#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h +new file mode 100644 +index 0000000..54503d2 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h +@@ -0,0 +1,337 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _osssys_4_0_1_OFFSET_HEADER ++#define _osssys_4_0_1_OFFSET_HEADER ++ ++ ++ ++// addressBlock: osssys_osssysdec ++// base address: 0x4280 ++#define mmIH_VMID_0_LUT 0x0000 ++#define mmIH_VMID_0_LUT_BASE_IDX 0 ++#define mmIH_VMID_1_LUT 0x0001 ++#define mmIH_VMID_1_LUT_BASE_IDX 0 ++#define mmIH_VMID_2_LUT 0x0002 ++#define mmIH_VMID_2_LUT_BASE_IDX 0 ++#define mmIH_VMID_3_LUT 0x0003 ++#define mmIH_VMID_3_LUT_BASE_IDX 0 ++#define mmIH_VMID_4_LUT 0x0004 ++#define mmIH_VMID_4_LUT_BASE_IDX 0 ++#define mmIH_VMID_5_LUT 0x0005 ++#define mmIH_VMID_5_LUT_BASE_IDX 0 ++#define mmIH_VMID_6_LUT 0x0006 ++#define mmIH_VMID_6_LUT_BASE_IDX 0 ++#define mmIH_VMID_7_LUT 0x0007 ++#define mmIH_VMID_7_LUT_BASE_IDX 0 ++#define mmIH_VMID_8_LUT 0x0008 ++#define mmIH_VMID_8_LUT_BASE_IDX 0 ++#define mmIH_VMID_9_LUT 0x0009 ++#define mmIH_VMID_9_LUT_BASE_IDX 0 ++#define mmIH_VMID_10_LUT 0x000a ++#define mmIH_VMID_10_LUT_BASE_IDX 0 ++#define mmIH_VMID_11_LUT 0x000b ++#define mmIH_VMID_11_LUT_BASE_IDX 0 ++#define mmIH_VMID_12_LUT 0x000c ++#define mmIH_VMID_12_LUT_BASE_IDX 0 ++#define mmIH_VMID_13_LUT 0x000d ++#define mmIH_VMID_13_LUT_BASE_IDX 0 ++#define mmIH_VMID_14_LUT 0x000e ++#define mmIH_VMID_14_LUT_BASE_IDX 0 ++#define mmIH_VMID_15_LUT 0x000f ++#define mmIH_VMID_15_LUT_BASE_IDX 0 ++#define mmIH_VMID_0_LUT_MM 0x0010 ++#define mmIH_VMID_0_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_1_LUT_MM 0x0011 ++#define mmIH_VMID_1_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_2_LUT_MM 0x0012 ++#define mmIH_VMID_2_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_3_LUT_MM 0x0013 ++#define mmIH_VMID_3_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_4_LUT_MM 0x0014 ++#define mmIH_VMID_4_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_5_LUT_MM 0x0015 ++#define mmIH_VMID_5_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_6_LUT_MM 0x0016 ++#define mmIH_VMID_6_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_7_LUT_MM 0x0017 ++#define mmIH_VMID_7_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_8_LUT_MM 0x0018 ++#define mmIH_VMID_8_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_9_LUT_MM 0x0019 ++#define mmIH_VMID_9_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_10_LUT_MM 0x001a ++#define mmIH_VMID_10_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_11_LUT_MM 0x001b ++#define mmIH_VMID_11_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_12_LUT_MM 0x001c ++#define mmIH_VMID_12_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_13_LUT_MM 0x001d ++#define mmIH_VMID_13_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_14_LUT_MM 0x001e ++#define mmIH_VMID_14_LUT_MM_BASE_IDX 0 ++#define mmIH_VMID_15_LUT_MM 0x001f ++#define mmIH_VMID_15_LUT_MM_BASE_IDX 0 ++#define mmIH_COOKIE_0 0x0020 ++#define mmIH_COOKIE_0_BASE_IDX 0 ++#define mmIH_COOKIE_1 0x0021 ++#define mmIH_COOKIE_1_BASE_IDX 0 ++#define mmIH_COOKIE_2 0x0022 ++#define mmIH_COOKIE_2_BASE_IDX 0 ++#define mmIH_COOKIE_3 0x0023 ++#define mmIH_COOKIE_3_BASE_IDX 0 ++#define mmIH_COOKIE_4 0x0024 ++#define mmIH_COOKIE_4_BASE_IDX 0 ++#define mmIH_COOKIE_5 0x0025 ++#define mmIH_COOKIE_5_BASE_IDX 0 ++#define mmIH_COOKIE_6 0x0026 ++#define mmIH_COOKIE_6_BASE_IDX 0 ++#define mmIH_COOKIE_7 0x0027 ++#define mmIH_COOKIE_7_BASE_IDX 0 ++#define mmIH_REGISTER_LAST_PART0 0x003f ++#define mmIH_REGISTER_LAST_PART0_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_0 0x0040 ++#define mmSEM_REQ_INPUT_0_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_1 0x0041 ++#define mmSEM_REQ_INPUT_1_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_2 0x0042 ++#define mmSEM_REQ_INPUT_2_BASE_IDX 0 ++#define mmSEM_REQ_INPUT_3 0x0043 ++#define mmSEM_REQ_INPUT_3_BASE_IDX 0 ++#define mmSEM_REGISTER_LAST_PART0 0x007f ++#define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0 ++#define mmIH_RB_CNTL 0x0080 ++#define mmIH_RB_CNTL_BASE_IDX 0 ++#define mmIH_RB_BASE 0x0081 ++#define mmIH_RB_BASE_BASE_IDX 0 ++#define mmIH_RB_BASE_HI 0x0082 ++#define mmIH_RB_BASE_HI_BASE_IDX 0 ++#define mmIH_RB_RPTR 0x0083 ++#define mmIH_RB_RPTR_BASE_IDX 0 ++#define mmIH_RB_WPTR 0x0084 ++#define mmIH_RB_WPTR_BASE_IDX 0 ++#define mmIH_RB_WPTR_ADDR_HI 0x0085 ++#define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0 ++#define mmIH_RB_WPTR_ADDR_LO 0x0086 ++#define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0 ++#define mmIH_DOORBELL_RPTR 0x0087 ++#define mmIH_DOORBELL_RPTR_BASE_IDX 0 ++#define mmIH_RB_CNTL_RING1 0x0088 ++#define mmIH_RB_CNTL_RING1_BASE_IDX 0 ++#define mmIH_RB_BASE_RING1 0x0089 ++#define mmIH_RB_BASE_RING1_BASE_IDX 0 ++#define mmIH_RB_BASE_HI_RING1 0x008a ++#define mmIH_RB_BASE_HI_RING1_BASE_IDX 0 ++#define mmIH_RB_RPTR_RING1 0x008b ++#define mmIH_RB_RPTR_RING1_BASE_IDX 0 ++#define mmIH_RB_WPTR_RING1 0x008c ++#define mmIH_RB_WPTR_RING1_BASE_IDX 0 ++#define mmIH_DOORBELL_RPTR_RING1 0x008f ++#define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0 ++#define mmIH_RB_CNTL_RING2 0x0090 ++#define mmIH_RB_CNTL_RING2_BASE_IDX 0 ++#define mmIH_RB_BASE_RING2 0x0091 ++#define mmIH_RB_BASE_RING2_BASE_IDX 0 ++#define mmIH_RB_BASE_HI_RING2 0x0092 ++#define mmIH_RB_BASE_HI_RING2_BASE_IDX 0 ++#define mmIH_RB_RPTR_RING2 0x0093 ++#define mmIH_RB_RPTR_RING2_BASE_IDX 0 ++#define mmIH_RB_WPTR_RING2 0x0094 ++#define mmIH_RB_WPTR_RING2_BASE_IDX 0 ++#define mmIH_DOORBELL_RPTR_RING2 0x0097 ++#define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0 ++#define mmIH_VERSION 0x0098 ++#define mmIH_VERSION_BASE_IDX 0 ++#define mmIH_CNTL 0x00c0 ++#define mmIH_CNTL_BASE_IDX 0 ++#define mmIH_CNTL2 0x00c1 ++#define mmIH_CNTL2_BASE_IDX 0 ++#define mmIH_STATUS 0x00c2 ++#define mmIH_STATUS_BASE_IDX 0 ++#define mmIH_PERFMON_CNTL 0x00c3 ++#define mmIH_PERFMON_CNTL_BASE_IDX 0 ++#define mmIH_PERFCOUNTER0_RESULT 0x00c4 ++#define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0 ++#define mmIH_PERFCOUNTER1_RESULT 0x00c5 ++#define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0 ++#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 ++#define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 ++#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 ++#define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 ++#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 ++#define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 ++#define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca ++#define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 ++#define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb ++#define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 ++#define mmIH_DSM_MATCH_FCN_ID 0x00cc ++#define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0 ++#define mmIH_LIMIT_INT_RATE_CNTL 0x00cd ++#define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 ++#define mmIH_VF_RB_STATUS 0x00ce ++#define mmIH_VF_RB_STATUS_BASE_IDX 0 ++#define mmIH_VF_RB_STATUS2 0x00cf ++#define mmIH_VF_RB_STATUS2_BASE_IDX 0 ++#define mmIH_VF_RB1_STATUS 0x00d0 ++#define mmIH_VF_RB1_STATUS_BASE_IDX 0 ++#define mmIH_VF_RB1_STATUS2 0x00d1 ++#define mmIH_VF_RB1_STATUS2_BASE_IDX 0 ++#define mmIH_VF_RB2_STATUS 0x00d2 ++#define mmIH_VF_RB2_STATUS_BASE_IDX 0 ++#define mmIH_VF_RB2_STATUS2 0x00d3 ++#define mmIH_VF_RB2_STATUS2_BASE_IDX 0 ++#define mmIH_INT_FLOOD_CNTL 0x00d5 ++#define mmIH_INT_FLOOD_CNTL_BASE_IDX 0 ++#define mmIH_RB0_INT_FLOOD_STATUS 0x00d6 ++#define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_RB1_INT_FLOOD_STATUS 0x00d7 ++#define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_RB2_INT_FLOOD_STATUS 0x00d8 ++#define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_INT_FLOOD_STATUS 0x00d9 ++#define mmIH_INT_FLOOD_STATUS_BASE_IDX 0 ++#define mmIH_STORM_CLIENT_LIST_CNTL 0x00da ++#define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 ++#define mmIH_CLK_CTRL 0x00db ++#define mmIH_CLK_CTRL_BASE_IDX 0 ++#define mmIH_INT_FLAGS 0x00dc ++#define mmIH_INT_FLAGS_BASE_IDX 0 ++#define mmIH_LAST_INT_INFO0 0x00dd ++#define mmIH_LAST_INT_INFO0_BASE_IDX 0 ++#define mmIH_LAST_INT_INFO1 0x00de ++#define mmIH_LAST_INT_INFO1_BASE_IDX 0 ++#define mmIH_LAST_INT_INFO2 0x00df ++#define mmIH_LAST_INT_INFO2_BASE_IDX 0 ++#define mmIH_SCRATCH 0x00e0 ++#define mmIH_SCRATCH_BASE_IDX 0 ++#define mmIH_CLIENT_CREDIT_ERROR 0x00e1 ++#define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 ++#define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2 ++#define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 ++#define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3 ++#define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 ++#define mmIH_CREDIT_STATUS 0x00e4 ++#define mmIH_CREDIT_STATUS_BASE_IDX 0 ++#define mmIH_MMHUB_ERROR 0x00e5 ++#define mmIH_MMHUB_ERROR_BASE_IDX 0 ++#define mmIH_REGISTER_LAST_PART2 0x00ff ++#define mmIH_REGISTER_LAST_PART2_BASE_IDX 0 ++#define mmSEM_CLK_CTRL 0x0100 ++#define mmSEM_CLK_CTRL_BASE_IDX 0 ++#define mmSEM_UTC_CREDIT 0x0101 ++#define mmSEM_UTC_CREDIT_BASE_IDX 0 ++#define mmSEM_UTC_CONFIG 0x0102 ++#define mmSEM_UTC_CONFIG_BASE_IDX 0 ++#define mmSEM_UTCL2_TRAN_EN_LUT 0x0103 ++#define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0 ++#define mmSEM_MCIF_CONFIG 0x0104 ++#define mmSEM_MCIF_CONFIG_BASE_IDX 0 ++#define mmSEM_PERFMON_CNTL 0x0105 ++#define mmSEM_PERFMON_CNTL_BASE_IDX 0 ++#define mmSEM_PERFCOUNTER0_RESULT 0x0106 ++#define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0 ++#define mmSEM_PERFCOUNTER1_RESULT 0x0107 ++#define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0 ++#define mmSEM_STATUS 0x0108 ++#define mmSEM_STATUS_BASE_IDX 0 ++#define mmSEM_MAILBOX_CLIENTCONFIG 0x0109 ++#define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0 ++#define mmSEM_MAILBOX 0x010a ++#define mmSEM_MAILBOX_BASE_IDX 0 ++#define mmSEM_MAILBOX_CONTROL 0x010b ++#define mmSEM_MAILBOX_CONTROL_BASE_IDX 0 ++#define mmSEM_CHICKEN_BITS 0x010c ++#define mmSEM_CHICKEN_BITS_BASE_IDX 0 ++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d ++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0 ++#define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e ++#define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 ++#define mmSEM_OUTSTANDING_THRESHOLD 0x010f ++#define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0 ++#define mmSEM_REGISTER_LAST_PART2 0x017f ++#define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0 ++#define mmIH_ACTIVE_FCN_ID 0x0180 ++#define mmIH_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmIH_VIRT_RESET_REQ 0x0181 ++#define mmIH_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmIH_CLIENT_CFG 0x0184 ++#define mmIH_CLIENT_CFG_BASE_IDX 0 ++#define mmIH_CLIENT_CFG_INDEX 0x0188 ++#define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0 ++#define mmIH_CLIENT_CFG_DATA 0x0189 ++#define mmIH_CLIENT_CFG_DATA_BASE_IDX 0 ++#define mmIH_CID_REMAP_INDEX 0x018a ++#define mmIH_CID_REMAP_INDEX_BASE_IDX 0 ++#define mmIH_CID_REMAP_DATA 0x018b ++#define mmIH_CID_REMAP_DATA_BASE_IDX 0 ++#define mmIH_CHICKEN 0x018c ++#define mmIH_CHICKEN_BASE_IDX 0 ++#define mmIH_MMHUB_CNTL 0x018d ++#define mmIH_MMHUB_CNTL_BASE_IDX 0 ++#define mmIH_INT_DROP_CNTL 0x018e ++#define mmIH_INT_DROP_CNTL_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_VALUE0 0x018f ++#define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_VALUE1 0x0190 ++#define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_MASK0 0x0191 ++#define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 ++#define mmIH_INT_DROP_MATCH_MASK1 0x0192 ++#define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 ++#define mmIH_REGISTER_LAST_PART1 0x019f ++#define mmIH_REGISTER_LAST_PART1_BASE_IDX 0 ++#define mmSEM_ACTIVE_FCN_ID 0x01a0 ++#define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmSEM_VIRT_RESET_REQ 0x01a1 ++#define mmSEM_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmSEM_RESP_SDMA0 0x01a4 ++#define mmSEM_RESP_SDMA0_BASE_IDX 0 ++#define mmSEM_RESP_SDMA1 0x01a5 ++#define mmSEM_RESP_SDMA1_BASE_IDX 0 ++#define mmSEM_RESP_UVD 0x01a6 ++#define mmSEM_RESP_UVD_BASE_IDX 0 ++#define mmSEM_RESP_VCE_0 0x01a7 ++#define mmSEM_RESP_VCE_0_BASE_IDX 0 ++#define mmSEM_RESP_ACP 0x01a8 ++#define mmSEM_RESP_ACP_BASE_IDX 0 ++#define mmSEM_RESP_ISP 0x01a9 ++#define mmSEM_RESP_ISP_BASE_IDX 0 ++#define mmSEM_RESP_VCE_1 0x01aa ++#define mmSEM_RESP_VCE_1_BASE_IDX 0 ++#define mmSEM_RESP_VP8 0x01ab ++#define mmSEM_RESP_VP8_BASE_IDX 0 ++#define mmSEM_RESP_GC 0x01ac ++#define mmSEM_RESP_GC_BASE_IDX 0 ++#define mmSEM_CID_REMAP_INDEX 0x01b0 ++#define mmSEM_CID_REMAP_INDEX_BASE_IDX 0 ++#define mmSEM_CID_REMAP_DATA 0x01b1 ++#define mmSEM_CID_REMAP_DATA_BASE_IDX 0 ++#define mmSEM_ATOMIC_OP_LUT 0x01b2 ++#define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0 ++#define mmSEM_EDC_CONFIG 0x01b3 ++#define mmSEM_EDC_CONFIG_BASE_IDX 0 ++#define mmSEM_CHICKEN_BITS2 0x01b4 ++#define mmSEM_CHICKEN_BITS2_BASE_IDX 0 ++#define mmSEM_MMHUB_CNTL 0x01b5 ++#define mmSEM_MMHUB_CNTL_BASE_IDX 0 ++#define mmSEM_REGISTER_LAST_PART1 0x01bf ++#define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h +new file mode 100644 +index 0000000..19c4a40 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h +@@ -0,0 +1,1249 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _osssys_4_0_1_SH_MASK_HEADER ++#define _osssys_4_0_1_SH_MASK_HEADER ++ ++ ++// addressBlock: osssys_osssysdec ++//IH_VMID_0_LUT ++#define IH_VMID_0_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_1_LUT ++#define IH_VMID_1_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_2_LUT ++#define IH_VMID_2_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_3_LUT ++#define IH_VMID_3_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_4_LUT ++#define IH_VMID_4_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_5_LUT ++#define IH_VMID_5_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_6_LUT ++#define IH_VMID_6_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_7_LUT ++#define IH_VMID_7_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_8_LUT ++#define IH_VMID_8_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_9_LUT ++#define IH_VMID_9_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_10_LUT ++#define IH_VMID_10_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_11_LUT ++#define IH_VMID_11_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_12_LUT ++#define IH_VMID_12_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_13_LUT ++#define IH_VMID_13_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_14_LUT ++#define IH_VMID_14_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_15_LUT ++#define IH_VMID_15_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL ++//IH_VMID_0_LUT_MM ++#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_1_LUT_MM ++#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_2_LUT_MM ++#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_3_LUT_MM ++#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_4_LUT_MM ++#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_5_LUT_MM ++#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_6_LUT_MM ++#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_7_LUT_MM ++#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_8_LUT_MM ++#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_9_LUT_MM ++#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_10_LUT_MM ++#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_11_LUT_MM ++#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_12_LUT_MM ++#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_13_LUT_MM ++#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_14_LUT_MM ++#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_VMID_15_LUT_MM ++#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 ++#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL ++//IH_COOKIE_0 ++#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 ++#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 ++#define IH_COOKIE_0__RING_ID__SHIFT 0x10 ++#define IH_COOKIE_0__VM_ID__SHIFT 0x18 ++#define IH_COOKIE_0__RESERVED__SHIFT 0x1c ++#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f ++#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL ++#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L ++#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L ++#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L ++#define IH_COOKIE_0__RESERVED_MASK 0x70000000L ++#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L ++//IH_COOKIE_1 ++#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 ++#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL ++//IH_COOKIE_2 ++#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 ++#define IH_COOKIE_2__RESERVED__SHIFT 0x10 ++#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f ++#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL ++#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L ++#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L ++//IH_COOKIE_3 ++#define IH_COOKIE_3__PAS_ID__SHIFT 0x0 ++#define IH_COOKIE_3__RESERVED__SHIFT 0x10 ++#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f ++#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL ++#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L ++#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L ++//IH_COOKIE_4 ++#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 ++#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL ++//IH_COOKIE_5 ++#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 ++#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL ++//IH_COOKIE_6 ++#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 ++#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL ++//IH_COOKIE_7 ++#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 ++#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL ++//IH_REGISTER_LAST_PART0 ++#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 ++#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_0 ++#define SEM_REQ_INPUT_0__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_1 ++#define SEM_REQ_INPUT_1__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_2 ++#define SEM_REQ_INPUT_2__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL ++//SEM_REQ_INPUT_3 ++#define SEM_REQ_INPUT_3__DATA__SHIFT 0x0 ++#define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL ++//SEM_REGISTER_LAST_PART0 ++#define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 ++#define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL ++//IH_RB_CNTL ++#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 ++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 ++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 ++#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa ++#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb ++#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc ++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 ++#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 ++#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 ++#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 ++#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 ++#define IH_RB_CNTL__MC_RO__SHIFT 0x16 ++#define IH_RB_CNTL__MC_VMID__SHIFT 0x18 ++#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c ++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L ++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L ++#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L ++#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L ++#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L ++#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L ++#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L ++#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L ++#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L ++#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L ++#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L ++#define IH_RB_CNTL__MC_RO_MASK 0x00400000L ++#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L ++#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L ++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L ++//IH_RB_BASE ++#define IH_RB_BASE__ADDR__SHIFT 0x0 ++#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//IH_RB_BASE_HI ++#define IH_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL ++//IH_RB_RPTR ++#define IH_RB_RPTR__OFFSET__SHIFT 0x2 ++#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL ++//IH_RB_WPTR ++#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 ++#define IH_RB_WPTR__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 ++#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 ++#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L ++#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL ++#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L ++#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L ++//IH_RB_WPTR_ADDR_HI ++#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL ++//IH_RB_WPTR_ADDR_LO ++#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//IH_DOORBELL_RPTR ++#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 ++#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c ++#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL ++#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L ++//IH_RB_CNTL_RING1 ++#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 ++#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 ++#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7 ++#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 ++#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa ++#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb ++#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 ++#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 ++#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 ++#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 ++#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 ++#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L ++#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL ++#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L ++#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L ++#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L ++#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L ++#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L ++#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L ++#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L ++#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L ++#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L ++#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L ++#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L ++//IH_RB_BASE_RING1 ++#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL ++//IH_RB_BASE_HI_RING1 ++#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL ++//IH_RB_RPTR_RING1 ++#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 ++#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL ++//IH_RB_WPTR_RING1 ++#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 ++#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 ++#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 ++#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L ++#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL ++#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L ++#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L ++//IH_DOORBELL_RPTR_RING1 ++#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 ++#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c ++#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL ++#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L ++//IH_RB_CNTL_RING2 ++#define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0 ++#define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1 ++#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7 ++#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 ++#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa ++#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR__SHIFT 0xb ++#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 ++#define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12 ++#define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14 ++#define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16 ++#define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18 ++#define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L ++#define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL ++#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L ++#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L ++#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L ++#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR_MASK 0x00000800L ++#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L ++#define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L ++#define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L ++#define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L ++#define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L ++#define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L ++#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L ++//IH_RB_BASE_RING2 ++#define IH_RB_BASE_RING2__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL ++//IH_RB_BASE_HI_RING2 ++#define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0 ++#define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL ++//IH_RB_RPTR_RING2 ++#define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2 ++#define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL ++//IH_RB_WPTR_RING2 ++#define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0 ++#define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12 ++#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13 ++#define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L ++#define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL ++#define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L ++#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L ++//IH_DOORBELL_RPTR_RING2 ++#define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0 ++#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c ++#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL ++#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L ++//IH_VERSION ++#define IH_VERSION__MINVER__SHIFT 0x0 ++#define IH_VERSION__MAJVER__SHIFT 0x8 ++#define IH_VERSION__REV__SHIFT 0x10 ++#define IH_VERSION__MINVER_MASK 0x0000007FL ++#define IH_VERSION__MAJVER_MASK 0x00007F00L ++#define IH_VERSION__REV_MASK 0x003F0000L ++//IH_CNTL ++#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 ++#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 ++#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 ++#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 ++#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL ++#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L ++#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L ++#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L ++//IH_CNTL2 ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL ++#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L ++//IH_STATUS ++#define IH_STATUS__IDLE__SHIFT 0x0 ++#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 ++#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 ++#define IH_STATUS__RB_FULL__SHIFT 0x3 ++#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 ++#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 ++#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 ++#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 ++#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 ++#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 ++#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa ++#define IH_STATUS__SWITCH_READY__SHIFT 0xb ++#define IH_STATUS__RB1_FULL__SHIFT 0xc ++#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd ++#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe ++#define IH_STATUS__RB2_FULL__SHIFT 0xf ++#define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10 ++#define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11 ++#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 ++#define IH_STATUS__IDLE_MASK 0x00000001L ++#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L ++#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L ++#define IH_STATUS__RB_FULL_MASK 0x00000008L ++#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L ++#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L ++#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L ++#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L ++#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L ++#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L ++#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L ++#define IH_STATUS__SWITCH_READY_MASK 0x00000800L ++#define IH_STATUS__RB1_FULL_MASK 0x00001000L ++#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L ++#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L ++#define IH_STATUS__RB2_FULL_MASK 0x00008000L ++#define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L ++#define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L ++#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L ++//IH_PERFMON_CNTL ++#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 ++#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 ++#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 ++#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 ++#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 ++#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L ++#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L ++#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000007FCL ++#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L ++#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L ++#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x07FC0000L ++//IH_PERFCOUNTER0_RESULT ++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//IH_PERFCOUNTER1_RESULT ++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_VALUE_BIT_31_0 ++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_VALUE_BIT_63_32 ++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_VALUE_BIT_95_64 ++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL ++//IH_DSM_MATCH_FIELD_CONTROL ++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 ++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 ++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 ++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 ++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 ++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 ++#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 ++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L ++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L ++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L ++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L ++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L ++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L ++#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L ++//IH_DSM_MATCH_DATA_CONTROL ++#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL ++//IH_DSM_MATCH_FCN_ID ++#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x0 ++#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x1 ++#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L ++#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001EL ++//IH_LIMIT_INT_RATE_CNTL ++#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 ++#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 ++#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 ++#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 ++#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 ++#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L ++#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL ++#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L ++#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L ++#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L ++//IH_VF_RB_STATUS ++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 ++#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 ++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL ++#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L ++//IH_VF_RB_STATUS2 ++#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 ++#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 ++#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL ++#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0xFFFF0000L ++//IH_VF_RB1_STATUS ++#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 ++#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 ++#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL ++#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L ++//IH_VF_RB1_STATUS2 ++#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 ++#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL ++//IH_VF_RB2_STATUS ++#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 ++#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 ++#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL ++#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L ++//IH_VF_RB2_STATUS2 ++#define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0 ++#define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL ++//IH_INT_FLOOD_CNTL ++#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 ++#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 ++#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 ++#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L ++#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L ++#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L ++//IH_RB0_INT_FLOOD_STATUS ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL ++#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L ++//IH_RB1_INT_FLOOD_STATUS ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL ++#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L ++//IH_RB2_INT_FLOOD_STATUS ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL ++#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L ++//IH_INT_FLOOD_STATUS ++#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1c ++#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e ++#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L ++#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L ++#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L ++//IH_STORM_CLIENT_LIST_CNTL ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L ++#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L ++//IH_CLK_CTRL ++#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b ++#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c ++#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d ++#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e ++#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f ++#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L ++#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L ++#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L ++#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L ++#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L ++//IH_INT_FLAGS ++#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 ++#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 ++#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 ++#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 ++#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 ++#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 ++#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 ++#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 ++#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 ++#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 ++#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa ++#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb ++#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc ++#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd ++#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe ++#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf ++#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 ++#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 ++#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 ++#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 ++#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 ++#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 ++#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 ++#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 ++#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 ++#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 ++#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a ++#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b ++#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c ++#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d ++#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e ++#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f ++#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L ++#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L ++#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L ++#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L ++#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L ++#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L ++#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L ++#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L ++#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L ++#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L ++#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L ++#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L ++#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L ++#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L ++#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L ++#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L ++#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L ++#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L ++#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L ++#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L ++#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L ++#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L ++#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L ++#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L ++#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L ++#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L ++#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L ++#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L ++#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L ++#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L ++#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L ++#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L ++//IH_LAST_INT_INFO0 ++#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 ++#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 ++#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 ++#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 ++#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f ++#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL ++#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L ++#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L ++#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L ++#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L ++//IH_LAST_INT_INFO1 ++#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 ++#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL ++//IH_LAST_INT_INFO2 ++#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 ++#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 ++#define IH_LAST_INT_INFO2__VF__SHIFT 0x14 ++#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL ++#define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L ++#define IH_LAST_INT_INFO2__VF_MASK 0x00100000L ++//IH_SCRATCH ++#define IH_SCRATCH__DATA__SHIFT 0x0 ++#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL ++//IH_CLIENT_CREDIT_ERROR ++#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f ++#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L ++#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L ++//IH_GPU_IOV_VIOLATION_LOG ++#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 ++#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 ++#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 ++#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 ++#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 ++#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 ++#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L ++#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL ++#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L ++#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L ++#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L ++#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L ++//IH_COOKIE_REC_VIOLATION_LOG ++#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x10 ++#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 ++#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x00FF0000L ++#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L ++//IH_CREDIT_STATUS ++#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 ++#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 ++#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 ++#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 ++#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 ++#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 ++#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 ++#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 ++#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 ++#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa ++#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb ++#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc ++#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd ++#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe ++#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf ++#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 ++#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 ++#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 ++#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 ++#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 ++#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 ++#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 ++#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 ++#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 ++#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 ++#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a ++#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b ++#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c ++#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d ++#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e ++#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f ++#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L ++#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L ++#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L ++#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L ++#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L ++#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L ++#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L ++#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L ++#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L ++#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L ++#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L ++#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L ++#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L ++#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L ++#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L ++#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L ++#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L ++#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L ++#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L ++#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L ++#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L ++#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L ++#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L ++#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L ++#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L ++#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L ++#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L ++#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L ++#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L ++#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L ++#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L ++//IH_MMHUB_ERROR ++#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 ++#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 ++#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 ++#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L ++#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L ++#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L ++#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L ++//IH_REGISTER_LAST_PART2 ++#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 ++#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL ++//SEM_CLK_CTRL ++#define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define SEM_CLK_CTRL__RESERVED__SHIFT 0xc ++#define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define SEM_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define SEM_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define SEM_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define SEM_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//SEM_UTC_CREDIT ++#define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0 ++#define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8 ++#define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL ++#define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L ++//SEM_UTC_CONFIG ++#define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0 ++#define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3 ++#define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4 ++#define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5 ++#define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L ++#define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L ++#define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L ++#define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L ++//SEM_UTCL2_TRAN_EN_LUT ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0 ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1 ++#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2 ++#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3 ++#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4 ++#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5 ++#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6 ++#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7 ++#define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x8 ++#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L ++#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L ++#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L ++#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L ++#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L ++#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L ++#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L ++#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L ++#define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFF00L ++#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L ++//SEM_MCIF_CONFIG ++#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 ++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 ++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 ++#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L ++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL ++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L ++//SEM_PERFMON_CNTL ++#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 ++#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 ++#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa ++#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb ++#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc ++#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L ++#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L ++#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL ++#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L ++#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L ++#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L ++//SEM_PERFCOUNTER0_RESULT ++#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SEM_PERFCOUNTER1_RESULT ++#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SEM_STATUS ++#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 ++#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 ++#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 ++#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 ++#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 ++#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 ++#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 ++#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 ++#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 ++#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 ++#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa ++#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb ++#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc ++#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd ++#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe ++#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf ++#define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10 ++#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11 ++#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12 ++#define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13 ++#define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14 ++#define SEM_STATUS__MIF_IDLE__SHIFT 0x15 ++#define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16 ++#define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17 ++#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f ++#define SEM_STATUS__SEM_IDLE_MASK 0x00000001L ++#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L ++#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L ++#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L ++#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L ++#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L ++#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L ++#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L ++#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L ++#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L ++#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L ++#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L ++#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L ++#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L ++#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L ++#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L ++#define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L ++#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L ++#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L ++#define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L ++#define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L ++#define SEM_STATUS__MIF_IDLE_MASK 0x00200000L ++#define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L ++#define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L ++#define SEM_STATUS__SWITCH_READY_MASK 0x80000000L ++//SEM_MAILBOX_CLIENTCONFIG ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc ++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 ++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L ++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L ++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L ++//SEM_MAILBOX ++#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 ++#define SEM_MAILBOX__RESERVED__SHIFT 0x10 ++#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL ++#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L ++//SEM_MAILBOX_CONTROL ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0 ++#define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10 ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL ++#define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L ++//SEM_CHICKEN_BITS ++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 ++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 ++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 ++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 ++#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6 ++#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7 ++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 ++#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa ++#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc ++#define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe ++#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf ++#define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10 ++#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12 ++#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13 ++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L ++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L ++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L ++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L ++#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L ++#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L ++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L ++#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L ++#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L ++#define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L ++#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L ++#define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L ++#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L ++#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L ++//SEM_MAILBOX_CLIENTCONFIG_EXTRA ++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 ++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL ++//SEM_GPU_IOV_VIOLATION_LOG ++#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 ++#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 ++#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 ++#define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 ++#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 ++#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 ++#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L ++#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL ++#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L ++#define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L ++#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L ++#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L ++//SEM_OUTSTANDING_THRESHOLD ++#define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0 ++#define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL ++//SEM_REGISTER_LAST_PART2 ++#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 ++#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL ++//IH_ACTIVE_FCN_ID ++#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 ++#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 ++#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f ++#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL ++#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L ++#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L ++//IH_VIRT_RESET_REQ ++#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define IH_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL ++#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//IH_CLIENT_CFG ++#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 ++#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL ++//IH_CLIENT_CFG_INDEX ++#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 ++#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL ++//IH_CLIENT_CFG_DATA ++#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0 ++#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 ++#define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14 ++#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 ++#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 ++#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0001FFFFL ++#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L ++#define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L ++#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L ++#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L ++//IH_CID_REMAP_INDEX ++#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 ++#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L ++//IH_CID_REMAP_DATA ++#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 ++#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 ++#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 ++#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL ++#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L ++#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L ++//IH_CHICKEN ++#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 ++#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L ++//IH_MMHUB_CNTL ++#define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 ++#define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 ++#define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc ++#define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL ++#define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L ++#define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L ++//IH_INT_DROP_CNTL ++#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 ++#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 ++#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 ++#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 ++#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 ++#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 ++#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 ++#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 ++#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 ++#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L ++#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L ++#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L ++#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L ++#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L ++#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L ++#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L ++#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L ++#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L ++//IH_INT_DROP_MATCH_VALUE0 ++#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 ++#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 ++#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 ++#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 ++#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL ++#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L ++#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x000F0000L ++#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L ++#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L ++//IH_INT_DROP_MATCH_VALUE1 ++#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL ++//IH_INT_DROP_MATCH_MASK0 ++#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 ++#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 ++#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 ++#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 ++#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL ++#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L ++#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x000F0000L ++#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L ++#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L ++//IH_INT_DROP_MATCH_MASK1 ++#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 ++#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL ++//IH_REGISTER_LAST_PART1 ++#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 ++#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL ++//SEM_ACTIVE_FCN_ID ++#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//SEM_VIRT_RESET_REQ ++#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define SEM_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL ++#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//SEM_RESP_SDMA0 ++#define SEM_RESP_SDMA0__ADDR__SHIFT 0x2 ++#define SEM_RESP_SDMA0__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_SDMA1 ++#define SEM_RESP_SDMA1__ADDR__SHIFT 0x2 ++#define SEM_RESP_SDMA1__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_UVD ++#define SEM_RESP_UVD__ADDR__SHIFT 0x2 ++#define SEM_RESP_UVD__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_VCE_0 ++#define SEM_RESP_VCE_0__ADDR__SHIFT 0x2 ++#define SEM_RESP_VCE_0__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_ACP ++#define SEM_RESP_ACP__ADDR__SHIFT 0x2 ++#define SEM_RESP_ACP__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_ISP ++#define SEM_RESP_ISP__ADDR__SHIFT 0x2 ++#define SEM_RESP_ISP__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_VCE_1 ++#define SEM_RESP_VCE_1__ADDR__SHIFT 0x2 ++#define SEM_RESP_VCE_1__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_VP8 ++#define SEM_RESP_VP8__ADDR__SHIFT 0x2 ++#define SEM_RESP_VP8__ADDR_MASK 0x000FFFFCL ++//SEM_RESP_GC ++#define SEM_RESP_GC__ADDR__SHIFT 0x2 ++#define SEM_RESP_GC__ADDR_MASK 0x000FFFFCL ++//SEM_CID_REMAP_INDEX ++#define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0 ++#define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L ++//SEM_CID_REMAP_DATA ++#define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 ++#define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 ++#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 ++#define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL ++#define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L ++#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L ++//SEM_ATOMIC_OP_LUT ++#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0 ++#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7 ++#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe ++#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15 ++#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL ++#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L ++#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L ++#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L ++//SEM_EDC_CONFIG ++#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 ++#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L ++//SEM_CHICKEN_BITS2 ++#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 ++#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1 ++#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L ++#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L ++//SEM_MMHUB_CNTL ++#define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 ++#define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8 ++#define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL ++#define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L ++//SEM_REGISTER_LAST_PART1 ++#define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 ++#define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL ++ ++#endif +-- +2.7.4 + |