diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3818-drm-amd-pp-Delete-get_xclk-function-in-powerplay.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3818-drm-amd-pp-Delete-get_xclk-function-in-powerplay.patch | 256 |
1 files changed, 256 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3818-drm-amd-pp-Delete-get_xclk-function-in-powerplay.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3818-drm-amd-pp-Delete-get_xclk-function-in-powerplay.patch new file mode 100644 index 00000000..9f2bfc0b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3818-drm-amd-pp-Delete-get_xclk-function-in-powerplay.patch @@ -0,0 +1,256 @@ +From 0819c4b83417adf2c042e1ce49acbde0269322cc Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Fri, 16 Mar 2018 16:56:58 +0800 +Subject: [PATCH 3818/4131] drm/amd/pp: Delete get_xclk function in powerplay + +use asic's callback function get_xclk in amdgpu + +Change-Id: Iaec15f34749d699729d3a45a62fe6727319eb0ae +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 +--- + drivers/gpu/drm/amd/include/cgs_common.h | 1 - + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 27 ++-------------------- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 1 - + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 4 ++-- + .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 4 ++-- + .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 2 +- + drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 2 +- + drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 2 +- + .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +- + .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 6 ++--- + .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 +- + 12 files changed, 15 insertions(+), 43 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +index 37098c6..5b37c1a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +@@ -715,12 +715,9 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, + return -EINVAL; + + mode_info = info->mode_info; +- if (mode_info) { ++ if (mode_info) + /* if the displays are off, vblank time is max */ + mode_info->vblank_time_us = 0xffffffff; +- /* always set the reference clock */ +- mode_info->ref_clock = adev->clock.spll.reference_freq; +- } + + if (!amdgpu_device_has_dc_support(adev)) { + struct amdgpu_crtc *amdgpu_crtc; +diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h +index 8602219..6ff8f35 100644 +--- a/drivers/gpu/drm/amd/include/cgs_common.h ++++ b/drivers/gpu/drm/amd/include/cgs_common.h +@@ -106,7 +106,6 @@ struct cgs_firmware_info { + + struct cgs_mode_info { + uint32_t refresh_rate; +- uint32_t ref_clock; + uint32_t vblank_time_us; + }; + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 96306ae..b0ff526 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -891,30 +891,6 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) + return 0; + } + +-uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr) +-{ +- uint32_t reference_clock, tmp; +- struct cgs_display_info info = {0}; +- struct cgs_mode_info mode_info = {0}; +- +- info.mode_info = &mode_info; +- +- tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK); +- +- if (tmp) +- return TCLK; +- +- cgs_get_active_displays_info(hwmgr->device, &info); +- reference_clock = mode_info.ref_clock; +- +- tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE); +- +- if (0 != tmp) +- return reference_clock / 4; +- +- return reference_clock; +-} +- + static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) + { + +@@ -3967,7 +3943,8 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) + display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); + cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); + +- ref_clock = mode_info.ref_clock; ++ ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); ++ pr_info("ref_clock is %d \n", ref_clock); + refresh_rate = mode_info.refresh_rate; + + if (0 == refresh_rate) +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h +index 3bcfc61..f40179c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h +@@ -361,7 +361,6 @@ enum SMU7_I2CLineID { + #define SMU7_I2C_DDCVGACLK 0x4d + + #define SMU7_UNUSED_GPIO_PIN 0x7F +-uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr); + uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, + uint32_t clock_insr); + #endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c +index f6573ed..4dd26eb 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c +@@ -95,7 +95,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) + if (tach_period == 0) + return -EINVAL; + +- crystal_clock_freq = smu7_get_xclk(hwmgr); ++ crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + *speed = 60 * crystal_clock_freq * 10000 / tach_period; + +@@ -267,7 +267,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) + if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) + smu7_fan_ctrl_stop_smc_fan_control(hwmgr); + +- crystal_clock_freq = smu7_get_xclk(hwmgr); ++ crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +index 0147267..444337a 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +@@ -110,7 +110,7 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) + if (tach_period == 0) + return -EINVAL; + +- crystal_clock_freq = smu7_get_xclk(hwmgr); ++ crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + *speed = 60 * crystal_clock_freq * 10000 / tach_period; + } +@@ -331,7 +331,7 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) + result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr); + + if (!result) { +- crystal_clock_freq = smu7_get_xclk(hwmgr); ++ crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); + reg = soc15_get_register_offset(THM_HWID, 0, + mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h +index 82f10bd..21e7c4d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h +@@ -73,7 +73,7 @@ extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr); + extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr); + extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr, + struct PP_TemperatureRange *range); +-extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr); ++ + + #endif + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +index 5d6dfdf..08d0001 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +@@ -2222,7 +2222,7 @@ static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + + fan_table.TempRespLim = cpu_to_be16(5); + +- reference_clock = smu7_get_xclk(hwmgr); ++ reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600); + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +index 95fcda3..43432e4 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +@@ -2254,7 +2254,7 @@ static int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + + fan_table.TempRespLim = cpu_to_be16(5); + +- reference_clock = smu7_get_xclk(hwmgr); ++ reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr-> + thermal_controller.advanceFanControlParameters.ulCycleDelay * +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +index 4e2f62e..d4bb934 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +@@ -2158,7 +2158,7 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + + fan_table.TempRespLim = cpu_to_be16(5); + +- reference_clock = smu7_get_xclk(hwmgr); ++ reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600); + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +index 03ec1e5..f6b1298 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +@@ -811,7 +811,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, + + struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; + +- ref_clk = smu7_get_xclk(hwmgr); ++ ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { + for (i = 0; i < NUM_SCLK_RANGE; i++) { +@@ -876,7 +876,7 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, + return result; + } + +- ref_clock = smu7_get_xclk(hwmgr); ++ ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + for (i = 0; i < NUM_SCLK_RANGE; i++) { + if (clock > smu_data->range_table[i].trans_lower_frequency +@@ -2132,7 +2132,7 @@ static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + + fan_table.TempRespLim = cpu_to_be16(5); + +- reference_clock = smu7_get_xclk(hwmgr); ++ reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr-> + thermal_controller.advanceFanControlParameters.ulCycleDelay * +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +index 26cca8c..b51d746 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +@@ -2574,7 +2574,7 @@ static int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) + + fan_table.TempRespLim = cpu_to_be16(5); + +- reference_clock = smu7_get_xclk(hwmgr); ++ reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); + + fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600); + +-- +2.7.4 + |