diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3805-drm-amd-pp-Mv-cz-uvd-vce-pg-dpm-functions-to-cz_hwmg.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3805-drm-amd-pp-Mv-cz-uvd-vce-pg-dpm-functions-to-cz_hwmg.patch | 459 |
1 files changed, 459 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3805-drm-amd-pp-Mv-cz-uvd-vce-pg-dpm-functions-to-cz_hwmg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3805-drm-amd-pp-Mv-cz-uvd-vce-pg-dpm-functions-to-cz_hwmg.patch new file mode 100644 index 00000000..7f0e26b7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3805-drm-amd-pp-Mv-cz-uvd-vce-pg-dpm-functions-to-cz_hwmg.patch @@ -0,0 +1,459 @@ +From 002e75fc509fe94e4d6eef39e9b48adbf13f85eb Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Tue, 13 Mar 2018 15:44:42 +0800 +Subject: [PATCH 3805/4131] drm/amd/pp: Mv cz uvd/vce pg/dpm functions to + cz_hwmgr.c + +1. delete cz_clockpowergating.c/.h files +2. mark uvd/vce dpm/pg functions static + +Change-Id: I1905d3283f710696b34119142d2449900e67b222 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Evan Quan <evan.quan@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- + .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 131 --------------- + .../drm/amd/powerplay/hwmgr/cz_clockpowergating.h | 33 ---- + drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 175 ++++++++++++++++----- + drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h | 8 - + 5 files changed, 140 insertions(+), 209 deletions(-) + delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c + delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index d319c36..9e2589d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -5,7 +5,7 @@ + + HARDWARE_MGR = hwmgr.o processpptables.o \ + hardwaremanager.o cz_hwmgr.o \ +- cz_clockpowergating.o pppcielanes.o\ ++ pppcielanes.o\ + process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \ + smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ + smu7_clockpowergating.o \ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +deleted file mode 100644 +index 01e5612..0000000 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c ++++ /dev/null +@@ -1,131 +0,0 @@ +-/* +- * Copyright 2015 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "hwmgr.h" +-#include "cz_clockpowergating.h" +-#include "cz_ppsmc.h" +- +-int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) +-{ +- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); +- uint32_t dpm_features = 0; +- +- if (enable && +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_UVDDPM)) { +- cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled; +- dpm_features |= UVD_DPM_MASK; +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_EnableAllSmuFeatures, dpm_features); +- } else { +- dpm_features |= UVD_DPM_MASK; +- cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled; +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_DisableAllSmuFeatures, dpm_features); +- } +- return 0; +-} +- +-int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) +-{ +- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); +- uint32_t dpm_features = 0; +- +- if (enable && phm_cap_enabled( +- hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_VCEDPM)) { +- cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled; +- dpm_features |= VCE_DPM_MASK; +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_EnableAllSmuFeatures, dpm_features); +- } else { +- dpm_features |= VCE_DPM_MASK; +- cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled; +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_DisableAllSmuFeatures, dpm_features); +- } +- +- return 0; +-} +- +- +-void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) +-{ +- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); +- +- cz_hwmgr->uvd_power_gated = bgate; +- +- if (bgate) { +- cgs_set_powergating_state(hwmgr->device, +- AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_GATE); +- cgs_set_clockgating_state(hwmgr->device, +- AMD_IP_BLOCK_TYPE_UVD, +- AMD_CG_STATE_GATE); +- cz_dpm_update_uvd_dpm(hwmgr, true); +- cz_dpm_powerdown_uvd(hwmgr); +- } else { +- cz_dpm_powerup_uvd(hwmgr); +- cgs_set_clockgating_state(hwmgr->device, +- AMD_IP_BLOCK_TYPE_UVD, +- AMD_CG_STATE_UNGATE); +- cgs_set_powergating_state(hwmgr->device, +- AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_UNGATE); +- cz_dpm_update_uvd_dpm(hwmgr, false); +- } +- +-} +- +-void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) +-{ +- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); +- +- if (bgate) { +- cgs_set_powergating_state( +- hwmgr->device, +- AMD_IP_BLOCK_TYPE_VCE, +- AMD_PG_STATE_GATE); +- cgs_set_clockgating_state( +- hwmgr->device, +- AMD_IP_BLOCK_TYPE_VCE, +- AMD_CG_STATE_GATE); +- cz_enable_disable_vce_dpm(hwmgr, false); +- cz_dpm_powerdown_vce(hwmgr); +- cz_hwmgr->vce_power_gated = true; +- } else { +- cz_dpm_powerup_vce(hwmgr); +- cz_hwmgr->vce_power_gated = false; +- cgs_set_clockgating_state( +- hwmgr->device, +- AMD_IP_BLOCK_TYPE_VCE, +- AMD_CG_STATE_UNGATE); +- cgs_set_powergating_state( +- hwmgr->device, +- AMD_IP_BLOCK_TYPE_VCE, +- AMD_PG_STATE_UNGATE); +- cz_dpm_update_vce_dpm(hwmgr); +- cz_enable_disable_vce_dpm(hwmgr, true); +- } +-} +- +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h +deleted file mode 100644 +index 08d393f..0000000 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* +- * Copyright 2015 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef _CZ_CLOCK_POWER_GATING_H_ +-#define _CZ_CLOCK_POWER_GATING_H_ +- +-#include "cz_hwmgr.h" +- +-extern void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); +-extern void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); +-extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); +-extern int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable); +-#endif /* _CZ_CLOCK_POWER_GATING_H_ */ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +index 8c1f884..4b73f07 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +@@ -37,7 +37,6 @@ + #include "cz_ppsmc.h" + #include "cz_hwmgr.h" + #include "power_state.h" +-#include "cz_clockpowergating.h" + #include "pp_thermal.h" + + #define ixSMUSVI_NB_CURRENTVID 0xD8230044 +@@ -1223,14 +1222,14 @@ static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, + return ret; + } + +-int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) ++static int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) + { + if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF); + return 0; + } + +-int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) ++static int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) + { + if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) { + return smum_send_msg_to_smc_with_parameter( +@@ -1242,37 +1241,7 @@ int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) + return 0; + } + +-int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) +-{ +- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); +- struct phm_uvd_clock_voltage_dependency_table *ptable = +- hwmgr->dyn_state.uvd_clock_voltage_dependency_table; +- +- if (!bgate) { +- /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */ +- if (PP_CAP(PHM_PlatformCaps_StablePState) || +- hwmgr->en_umd_pstate) { +- cz_hwmgr->uvd_dpm.hard_min_clk = +- ptable->entries[ptable->count - 1].vclk; +- +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_SetUvdHardMin, +- cz_get_uvd_level(hwmgr, +- cz_hwmgr->uvd_dpm.hard_min_clk, +- PPSMC_MSG_SetUvdHardMin)); +- +- cz_enable_disable_uvd_dpm(hwmgr, true); +- } else { +- cz_enable_disable_uvd_dpm(hwmgr, true); +- } +- } else { +- cz_enable_disable_uvd_dpm(hwmgr, false); +- } +- +- return 0; +-} +- +-int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) ++static int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) + { + struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); + struct phm_vce_clock_voltage_dependency_table *ptable = +@@ -1301,7 +1270,7 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) + return 0; + } + +-int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) ++static int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) + { + if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) + return smum_send_msg_to_smc(hwmgr, +@@ -1309,7 +1278,7 @@ int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) + return 0; + } + +-int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr) ++static int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr) + { + if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) + return smum_send_msg_to_smc(hwmgr, +@@ -1845,6 +1814,140 @@ static int cz_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, + return 0; + } + ++static int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ uint32_t dpm_features = 0; ++ ++ if (enable && ++ phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_UVDDPM)) { ++ cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled; ++ dpm_features |= UVD_DPM_MASK; ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_EnableAllSmuFeatures, dpm_features); ++ } else { ++ dpm_features |= UVD_DPM_MASK; ++ cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled; ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_DisableAllSmuFeatures, dpm_features); ++ } ++ return 0; ++} ++ ++int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ struct phm_uvd_clock_voltage_dependency_table *ptable = ++ hwmgr->dyn_state.uvd_clock_voltage_dependency_table; ++ ++ if (!bgate) { ++ /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */ ++ if (PP_CAP(PHM_PlatformCaps_StablePState) || ++ hwmgr->en_umd_pstate) { ++ cz_hwmgr->uvd_dpm.hard_min_clk = ++ ptable->entries[ptable->count - 1].vclk; ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetUvdHardMin, ++ cz_get_uvd_level(hwmgr, ++ cz_hwmgr->uvd_dpm.hard_min_clk, ++ PPSMC_MSG_SetUvdHardMin)); ++ ++ cz_enable_disable_uvd_dpm(hwmgr, true); ++ } else { ++ cz_enable_disable_uvd_dpm(hwmgr, true); ++ } ++ } else { ++ cz_enable_disable_uvd_dpm(hwmgr, false); ++ } ++ ++ return 0; ++} ++ ++static int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ uint32_t dpm_features = 0; ++ ++ if (enable && phm_cap_enabled( ++ hwmgr->platform_descriptor.platformCaps, ++ PHM_PlatformCaps_VCEDPM)) { ++ cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled; ++ dpm_features |= VCE_DPM_MASK; ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_EnableAllSmuFeatures, dpm_features); ++ } else { ++ dpm_features |= VCE_DPM_MASK; ++ cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled; ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_DisableAllSmuFeatures, dpm_features); ++ } ++ ++ return 0; ++} ++ ++ ++static void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ cz_hwmgr->uvd_power_gated = bgate; ++ ++ if (bgate) { ++ cgs_set_powergating_state(hwmgr->device, ++ AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_GATE); ++ cgs_set_clockgating_state(hwmgr->device, ++ AMD_IP_BLOCK_TYPE_UVD, ++ AMD_CG_STATE_GATE); ++ cz_dpm_update_uvd_dpm(hwmgr, true); ++ cz_dpm_powerdown_uvd(hwmgr); ++ } else { ++ cz_dpm_powerup_uvd(hwmgr); ++ cgs_set_clockgating_state(hwmgr->device, ++ AMD_IP_BLOCK_TYPE_UVD, ++ AMD_CG_STATE_UNGATE); ++ cgs_set_powergating_state(hwmgr->device, ++ AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_UNGATE); ++ cz_dpm_update_uvd_dpm(hwmgr, false); ++ } ++ ++} ++ ++static void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) ++{ ++ struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); ++ ++ if (bgate) { ++ cgs_set_powergating_state( ++ hwmgr->device, ++ AMD_IP_BLOCK_TYPE_VCE, ++ AMD_PG_STATE_GATE); ++ cgs_set_clockgating_state( ++ hwmgr->device, ++ AMD_IP_BLOCK_TYPE_VCE, ++ AMD_CG_STATE_GATE); ++ cz_enable_disable_vce_dpm(hwmgr, false); ++ cz_dpm_powerdown_vce(hwmgr); ++ cz_hwmgr->vce_power_gated = true; ++ } else { ++ cz_dpm_powerup_vce(hwmgr); ++ cz_hwmgr->vce_power_gated = false; ++ cgs_set_clockgating_state( ++ hwmgr->device, ++ AMD_IP_BLOCK_TYPE_VCE, ++ AMD_CG_STATE_UNGATE); ++ cgs_set_powergating_state( ++ hwmgr->device, ++ AMD_IP_BLOCK_TYPE_VCE, ++ AMD_PG_STATE_UNGATE); ++ cz_dpm_update_vce_dpm(hwmgr); ++ cz_enable_disable_vce_dpm(hwmgr, true); ++ } ++} ++ + static const struct pp_hwmgr_func cz_hwmgr_funcs = { + .backend_init = cz_hwmgr_backend_init, + .backend_fini = cz_hwmgr_backend_fini, +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h +index b56720a..604102b 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.h +@@ -311,12 +311,4 @@ struct cz_hwmgr { + uint32_t num_of_clk_entries; + }; + +-struct pp_hwmgr; +- +-int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr); +-int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr); +-int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr); +-int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr); +-int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); +-int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr); + #endif /* _CZ_HWMGR_H_ */ +-- +2.7.4 + |