diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3752-drm-amd-display-fix-check-condition-for-edp-power-co.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3752-drm-amd-display-fix-check-condition-for-edp-power-co.patch | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3752-drm-amd-display-fix-check-condition-for-edp-power-co.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3752-drm-amd-display-fix-check-condition-for-edp-power-co.patch new file mode 100644 index 00000000..3072e6ac --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3752-drm-amd-display-fix-check-condition-for-edp-power-co.patch @@ -0,0 +1,83 @@ +From be740387191caeeab28115c774f8f3ff16d31fdd Mon Sep 17 00:00:00 2001 +From: Eric Yang <Eric.Yang2@amd.com> +Date: Tue, 27 Feb 2018 15:34:30 -0500 +Subject: [PATCH 3752/4131] drm/amd/display: fix check condition for edp power + control + +Per discussion with VBIOS team, the orginal check is not correct in +all cases on latest VBIOS. Additional check is needed. This change should +maintain old behaviour on older VBIOS. + +Signed-off-by: Eric Yang <Eric.Yang2@amd.com> +Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 14 ++++++++++---- + .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +++++++--- + 2 files changed, 17 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index c7ea2c6..19ca7f0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -329,6 +329,8 @@ struct dce_hwseq_registers { + HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ + SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ + HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) + +@@ -405,10 +407,12 @@ struct dce_hwseq_registers { + HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \ + HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ +- HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) ++ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ ++ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ ++ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) + + #define HWSEQ_REG_FIELD_LIST(type) \ + type DCFE_CLOCK_ENABLE; \ +@@ -440,7 +444,9 @@ struct dce_hwseq_registers { + type ENABLE_L1_TLB;\ + type SYSTEM_ACCESS_MODE;\ + type LVTMA_BLON;\ +- type LVTMA_PWRSEQ_TARGET_STATE_R; ++ type LVTMA_PWRSEQ_TARGET_STATE_R;\ ++ type LVTMA_DIGON;\ ++ type LVTMA_DIGON_OVRD; + + #define HWSEQ_DCN_REG_FIELD_LIST(type) \ + type HUBP_VTG_SEL; \ +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index ca04848..9de3d79 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -737,10 +737,14 @@ static bool is_panel_backlight_on(struct dce_hwseq *hws) + + static bool is_panel_powered_on(struct dce_hwseq *hws) + { +- uint32_t value; ++ uint32_t pwr_seq_state, dig_on, dig_on_ovrd; ++ ++ ++ REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); ++ ++ REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd); + +- REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value); +- return value == 1; ++ return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1); + } + + static enum bp_result link_transmitter_control( +-- +2.7.4 + |