diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3751-drm-amd-display-Fix-takover-from-VGA-mode.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3751-drm-amd-display-Fix-takover-from-VGA-mode.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3751-drm-amd-display-Fix-takover-from-VGA-mode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3751-drm-amd-display-Fix-takover-from-VGA-mode.patch new file mode 100644 index 00000000..169ddc9b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3751-drm-amd-display-Fix-takover-from-VGA-mode.patch @@ -0,0 +1,85 @@ +From 26c44242ac1a2a5e41fc9b6c3225f86a7a40ab76 Mon Sep 17 00:00:00 2001 +From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Date: Tue, 27 Feb 2018 12:12:46 -0500 +Subject: [PATCH 3751/4131] drm/amd/display: Fix takover from VGA mode + +HW Engineer's Notes: + During switch from vga->extended, if we set the VGA_TEST_ENABLE and then + hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly. + Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset + VGA_TEST_ENABLE, to leave it in the same state as before. + +Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 10 ++++++++-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++++++++++ + 2 files changed, 18 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 3336428..c7ea2c6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -190,6 +190,7 @@ + SR(D2VGA_CONTROL), \ + SR(D3VGA_CONTROL), \ + SR(D4VGA_CONTROL), \ ++ SR(VGA_TEST_CONTROL), \ + SR(DC_IP_REQUEST_CNTL), \ + BL_REG_LIST() + +@@ -261,6 +262,7 @@ struct dce_hwseq_registers { + uint32_t D2VGA_CONTROL; + uint32_t D3VGA_CONTROL; + uint32_t D4VGA_CONTROL; ++ uint32_t VGA_TEST_CONTROL; + /* MMHUB registers. read only. temporary hack */ + uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; + uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; +@@ -404,7 +406,9 @@ struct dce_hwseq_registers { + HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ +- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) ++ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \ ++ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ ++ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) + + #define HWSEQ_REG_FIELD_LIST(type) \ + type DCFE_CLOCK_ENABLE; \ +@@ -483,7 +487,9 @@ struct dce_hwseq_registers { + type DCFCLK_GATE_DIS; \ + type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ + type DENTIST_DPPCLK_WDIVIDER; \ +- type DENTIST_DISPCLK_WDIVIDER; ++ type DENTIST_DISPCLK_WDIVIDER; \ ++ type VGA_TEST_ENABLE; \ ++ type VGA_TEST_RENDER_START; + + struct dce_hwseq_shift { + HWSEQ_REG_FIELD_LIST(uint8_t) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index c1a07ec..f1990c3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -224,6 +224,16 @@ static void disable_vga( + REG_WRITE(D2VGA_CONTROL, 0); + REG_WRITE(D3VGA_CONTROL, 0); + REG_WRITE(D4VGA_CONTROL, 0); ++ ++ /* HW Engineer's Notes: ++ * During switch from vga->extended, if we set the VGA_TEST_ENABLE and ++ * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly. ++ * ++ * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset ++ * VGA_TEST_ENABLE, to leave it in the same state as before. ++ */ ++ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1); ++ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1); + } + + static void dpp_pg_control( +-- +2.7.4 + |