diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3717-drm-amdgpu-implement-mmio-byte-access-helper-for-MB.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3717-drm-amdgpu-implement-mmio-byte-access-helper-for-MB.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3717-drm-amdgpu-implement-mmio-byte-access-helper-for-MB.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3717-drm-amdgpu-implement-mmio-byte-access-helper-for-MB.patch new file mode 100644 index 00000000..4ceca9b3 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3717-drm-amdgpu-implement-mmio-byte-access-helper-for-MB.patch @@ -0,0 +1,85 @@ +From 19a62800cac80f1133cda39329f2bb391437545b Mon Sep 17 00:00:00 2001 +From: Monk Liu <Monk.Liu@amd.com> +Date: Thu, 4 Jan 2018 18:13:20 +0800 +Subject: [PATCH 3717/4131] drm/amdgpu: implement mmio byte access helper for + MB + +mailbox registers can be accessed with a byte boundry according +to BIF team, so this patch prepares register byte access +and will be used by following patches. + +Actually, for mailbox registers once the byte field is touched even not changed, +the mailbox behaves, so we need the byte width accessing to those sort of regs. + +Change-Id: I1e84f1c6e8e75dc42eb5be09c492fa5e7eb7502a +Signed-off-by: Monk Liu <Monk.Liu@amd.com> +Reviewed-by: Pixel Ding <Pixel.Ding@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 ++++++++++++++++++++++++++ + 2 files changed, 32 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index c367a07..6805ea8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1697,6 +1697,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags); + void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + uint32_t acc_flags); ++void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); ++uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); ++ + u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); + void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); + +@@ -1720,6 +1723,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev); + #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) + #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) + ++#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) ++#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) ++ + #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) + #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) + #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 953d2fb..4eba30d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -121,6 +121,32 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, + return ret; + } + ++/* ++ * MMIO register read with bytes helper functions ++ * @offset:bytes offset from MMIO start ++ * ++*/ ++ ++uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { ++ if (offset < adev->rmmio_size) ++ return (readb(adev->rmmio + offset)); ++ BUG(); ++} ++ ++/* ++ * MMIO register write with bytes helper functions ++ * @offset:bytes offset from MMIO start ++ * @value: the value want to be written to the register ++ * ++*/ ++void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { ++ if (offset < adev->rmmio_size) ++ writeb(value, adev->rmmio + offset); ++ else ++ BUG(); ++} ++ ++ + void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + uint32_t acc_flags) + { +-- +2.7.4 + |