diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3674-drm-amd-pp-Add-PCC-feature-support-on-Vega.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3674-drm-amd-pp-Add-PCC-feature-support-on-Vega.patch | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3674-drm-amd-pp-Add-PCC-feature-support-on-Vega.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3674-drm-amd-pp-Add-PCC-feature-support-on-Vega.patch new file mode 100644 index 00000000..29d8a64f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3674-drm-amd-pp-Add-PCC-feature-support-on-Vega.patch @@ -0,0 +1,124 @@ +From b62db3a759e3de31e6b1f695d39a1b12c67d690a Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Fri, 2 Mar 2018 13:50:59 +0800 +Subject: [PATCH 3674/4131] drm/amd/pp: Add PCC feature support on Vega + +This features controls vega peak current protection to allow +for a wider compatibility with power supplies. + +Change-Id: Ic3fe4871fdef1f7372fe09430e97a639b2e28abf +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 34 ++++++++++++++++++++++ + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 + + drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 1 + + 3 files changed, 36 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 4b9397b..d4d1dbb 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -299,6 +299,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) + { + struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + int i; ++ uint32_t sub_vendor_id, hw_revision; ++ struct amdgpu_device *adev = hwmgr->adev; + + vega10_initialize_power_tune_defaults(hwmgr); + +@@ -363,6 +365,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) + FEATURE_FAN_CONTROL_BIT; + data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; + data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; ++ data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT; + + if (!data->registry_data.prefetcher_dpm_key_disabled) + data->smu_features[GNLD_DPM_PREFETCHER].supported = true; +@@ -432,6 +435,15 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) + if (data->registry_data.didt_support) + data->smu_features[GNLD_DIDT].supported = true; + ++ hw_revision = adev->pdev->revision; ++ sub_vendor_id = adev->pdev->subsystem_vendor; ++ ++ if ((hwmgr->chip_id == 0x6862 || ++ hwmgr->chip_id == 0x6861 || ++ hwmgr->chip_id == 0x6868) && ++ (hw_revision == 0) && ++ (sub_vendor_id != 0x1002)) ++ data->smu_features[GNLD_PCC_LIMIT].supported = true; + } + + #ifdef PPLIB_VEGA10_EVV_SUPPORT +@@ -2844,12 +2856,32 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) + return 0; + } + ++static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) ++{ ++ struct vega10_hwmgr *data = ++ (struct vega10_hwmgr *)(hwmgr->backend); ++ ++ if (data->smu_features[GNLD_PCC_LIMIT].supported) { ++ if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled) ++ pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled"); ++ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, ++ enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap), ++ "Attempt to Enable PCC Limit feature Failed!", ++ return -EINVAL); ++ data->smu_features[GNLD_PCC_LIMIT].enabled = enable; ++ } ++ ++ return 0; ++} ++ + static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) + { + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + int tmp_result, result = 0; + ++ vega10_enable_disable_PCC_limit_feature(hwmgr, true); ++ + if ((hwmgr->smu_version == 0x001c2c00) || + (hwmgr->smu_version == 0x001c2d00)) + smum_send_msg_to_smc_with_parameter(hwmgr, +@@ -4702,6 +4734,8 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) + tmp_result = vega10_acg_disable(hwmgr); + PP_ASSERT_WITH_CODE((tmp_result == 0), + "Failed to disable acg!", result = tmp_result); ++ ++ vega10_enable_disable_PCC_limit_feature(hwmgr, false); + return result; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +index ab3e879..de3219f 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +@@ -66,6 +66,7 @@ enum { + GNLD_FEATURE_FAST_PPT_BIT, + GNLD_DIDT, + GNLD_ACG, ++ GNLD_PCC_LIMIT, + GNLD_FEATURES_MAX + }; + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h +index b5aa700..fdd9a7a 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h +@@ -131,6 +131,7 @@ typedef uint16_t PPSMC_Result; + #define PPSMC_MSG_RunAcgInOpenLoop 0x5E + #define PPSMC_MSG_InitializeAcg 0x5F + #define PPSMC_MSG_GetCurrPkgPwr 0x61 ++#define PPSMC_MSG_SetPccThrottleLevel 0x67 + #define PPSMC_MSG_UpdatePkgPwrPidAlpha 0x68 + #define PPSMC_MSG_UpdatePkgPwrPidAlpha 0x68 + #define PPSMC_Message_Count 0x69 +-- +2.7.4 + |