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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3591-drm-amdgpu-use-the-TTM-dummy-page-instead-of-allocat.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3591-drm-amdgpu-use-the-TTM-dummy-page-instead-of-allocat.patch307
1 files changed, 307 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3591-drm-amdgpu-use-the-TTM-dummy-page-instead-of-allocat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3591-drm-amdgpu-use-the-TTM-dummy-page-instead-of-allocat.patch
new file mode 100644
index 00000000..ec86ff4e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3591-drm-amdgpu-use-the-TTM-dummy-page-instead-of-allocat.patch
@@ -0,0 +1,307 @@
+From 47781ad9855877cf0c8e06935a12a3965fcc32e2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 22 Feb 2018 08:35:11 +0100
+Subject: [PATCH 3591/4131] drm/amdgpu: use the TTM dummy page instead of
+ allocating one
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We have a global dummy page in TTM, use that one instead of allocating a
+new one.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+Conflicts:
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h
+
+Change-Id: Id27c255224e5c0029b4ce732163e8ef4a09724db
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +---------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 29 +++++++++++++----------------
+ drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
+ 13 files changed, 30 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 15f4cc0..6bb5c6b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -347,14 +347,6 @@ bool amdgpu_get_bios(struct amdgpu_device *adev);
+ bool amdgpu_read_bios(struct amdgpu_device *adev);
+
+ /*
+- * Dummy page
+- */
+-struct amdgpu_dummy_page {
+- struct page *page;
+- dma_addr_t addr;
+-};
+-
+-/*
+ * Clocks
+ */
+
+@@ -1567,7 +1559,7 @@ struct amdgpu_device {
+ /* MC */
+ struct amdgpu_gmc gmc;
+ struct amdgpu_gart gart;
+- struct amdgpu_dummy_page dummy_page;
++ dma_addr_t dummy_page_addr;
+ struct amdgpu_vm_manager vm_manager;
+ struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+index 008eaee..137145d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -68,17 +68,15 @@
+ */
+ static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
+ {
+- if (adev->dummy_page.page)
++ struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page;
++
++ if (adev->dummy_page_addr)
+ return 0;
+- adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
+- if (adev->dummy_page.page == NULL)
+- return -ENOMEM;
+- adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
+- 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+- if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
++ adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0,
++ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
++ if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) {
+ dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
+- __free_page(adev->dummy_page.page);
+- adev->dummy_page.page = NULL;
++ adev->dummy_page_addr = 0;
+ return -ENOMEM;
+ }
+ return 0;
+@@ -93,12 +91,11 @@ static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
+ */
+ static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
+ {
+- if (adev->dummy_page.page == NULL)
++ if (!adev->dummy_page_addr)
+ return;
+- pci_unmap_page(adev->pdev, adev->dummy_page.addr,
+- PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+- __free_page(adev->dummy_page.page);
+- adev->dummy_page.page = NULL;
++ pci_unmap_page(adev->pdev, adev->dummy_page_addr,
++ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
++ adev->dummy_page_addr = 0;
+ }
+
+ /**
+@@ -236,7 +233,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
+ #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
+ adev->gart.pages[p] = NULL;
+ #endif
+- page_base = adev->dummy_page.addr;
++ page_base = adev->dummy_page_addr;
+ if (!adev->gart.ptr)
+ continue;
+
+@@ -347,7 +344,7 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
+ {
+ int r;
+
+- if (adev->dummy_page.page)
++ if (adev->dummy_page_addr)
+ return 0;
+
+ /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+index 07c7852..44d10c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+@@ -111,7 +111,7 @@ static int cik_ih_irq_init(struct amdgpu_device *adev)
+ cik_ih_disable_interrupts(adev);
+
+ /* setup interrupt control */
+- WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++ WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
+ /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+index cfd0ad0..960c29e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+@@ -111,7 +111,7 @@ static int cz_ih_irq_init(struct amdgpu_device *adev)
+ cz_ih_disable_interrupts(adev);
+
+ /* setup interrupt control */
+- WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++ WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
+ /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+index 94a07bc..acfbd2d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+@@ -92,9 +92,9 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
+
+ /* Program "protection fault". */
+ WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+- (u32)((u64)adev->dummy_page.addr >> 44));
++ (u32)((u64)adev->dummy_page_addr >> 44));
+
+ WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
+ ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index 82321f0..94c6b13 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -532,7 +532,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+ WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT0_CNTL2, 0);
+ WREG32(mmVM_CONTEXT0_CNTL,
+ VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
+@@ -562,7 +562,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
+
+ /* enable context1-15 */
+ WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT1_CNTL2, 4);
+ WREG32(mmVM_CONTEXT1_CNTL,
+ VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index e5cb4fea..5c0298b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -644,7 +644,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+ WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT0_CNTL2, 0);
+ tmp = RREG32(mmVM_CONTEXT0_CNTL);
+ tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+@@ -674,7 +674,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+
+ /* enable context1-15 */
+ WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT1_CNTL2, 4);
+ tmp = RREG32(mmVM_CONTEXT1_CNTL);
+ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index 6b5ac21..8211f70 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -864,7 +864,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
+ WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+ WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT0_CNTL2, 0);
+ tmp = RREG32(mmVM_CONTEXT0_CNTL);
+ tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+@@ -894,7 +894,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
+
+ /* enable context1-15 */
+ WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32(mmVM_CONTEXT1_CNTL2, 4);
+ tmp = RREG32(mmVM_CONTEXT1_CNTL);
+ tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+index 3237a57..842c4b6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+@@ -111,7 +111,7 @@ static int iceland_ih_irq_init(struct amdgpu_device *adev)
+ iceland_ih_disable_interrupts(adev);
+
+ /* setup interrupt control */
+- WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++ WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
+ /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index d0ade9f..3dd5816 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -103,9 +103,9 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
+
+ /* Program "protection fault". */
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+- (u32)(adev->dummy_page.addr >> 12));
++ (u32)(adev->dummy_page_addr >> 12));
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+- (u32)((u64)adev->dummy_page.addr >> 44));
++ (u32)((u64)adev->dummy_page_addr >> 44));
+
+ tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
+ tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+index 2daeef6..1cf3424 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+@@ -133,7 +133,7 @@ static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
+ u32 interrupt_cntl;
+
+ /* setup interrupt control */
+- WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++ WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
+ /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+index cd10c76..df34dc7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+@@ -208,7 +208,7 @@ static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
+ u32 interrupt_cntl;
+
+ /* setup interrupt control */
+- WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++ WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
+ /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+index 1843538..52853d8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+@@ -107,7 +107,7 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)
+ tonga_ih_disable_interrupts(adev);
+
+ /* setup interrupt control */
+- WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
++ WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
+ /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 09:41:16 +0000