diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3589-drm-amd-pp-Fix-error-handling-when-smu-return-failed.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3589-drm-amd-pp-Fix-error-handling-when-smu-return-failed.patch | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3589-drm-amd-pp-Fix-error-handling-when-smu-return-failed.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3589-drm-amd-pp-Fix-error-handling-when-smu-return-failed.patch new file mode 100644 index 00000000..30e734ec --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3589-drm-amd-pp-Fix-error-handling-when-smu-return-failed.patch @@ -0,0 +1,65 @@ +From a39bfcffa9b0f30ecb9314ade59ab560da24a5b5 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Sun, 11 Feb 2018 12:38:58 +0800 +Subject: [PATCH 3589/4131] drm/amd/pp: Fix error handling when smu return + failed on Vega10. + +Clamp the clock index to a valid range when reading it back + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 26 ++++++++++++---------- + 1 file changed, 14 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 46e98cf..1f12114 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -3911,28 +3911,30 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, + + switch (idx) { + case AMDGPU_PP_SENSOR_GFX_SCLK: +- ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex); +- if (!ret) { +- vega10_read_arg_from_smc(hwmgr, &sclk_idx); ++ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex); ++ vega10_read_arg_from_smc(hwmgr, &sclk_idx); ++ if (sclk_idx < dpm_table->gfx_table.count) { + *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value; + *size = 4; ++ } else { ++ ret = -EINVAL; + } + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: +- ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex); +- if (!ret) { +- vega10_read_arg_from_smc(hwmgr, &mclk_idx); ++ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex); ++ vega10_read_arg_from_smc(hwmgr, &mclk_idx); ++ if (mclk_idx < dpm_table->mem_table.count) { + *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; + *size = 4; ++ } else { ++ ret = -EINVAL; + } + break; + case AMDGPU_PP_SENSOR_GPU_LOAD: +- ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0); +- if (!ret) { +- vega10_read_arg_from_smc(hwmgr, &activity_percent); +- *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; +- *size = 4; +- } ++ smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0); ++ vega10_read_arg_from_smc(hwmgr, &activity_percent); ++ *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; ++ *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_TEMP: + *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); +-- +2.7.4 + |