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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3578-drm-amdgpu-separate-PASID-mapping-from-VM-flush-v2.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3578-drm-amdgpu-separate-PASID-mapping-from-VM-flush-v2.patch573
1 files changed, 573 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3578-drm-amdgpu-separate-PASID-mapping-from-VM-flush-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3578-drm-amdgpu-separate-PASID-mapping-from-VM-flush-v2.patch
new file mode 100644
index 00000000..c7a99161
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3578-drm-amdgpu-separate-PASID-mapping-from-VM-flush-v2.patch
@@ -0,0 +1,573 @@
+From 4edd8b913ba4ad3b7f48f8890dd500635d2fc9b2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Sun, 4 Feb 2018 10:32:35 +0100
+Subject: [PATCH 3578/4131] drm/amdgpu: separate PASID mapping from VM flush v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Stuffing the PASID mapping into the VM flush isn't flexible enough since
+the PASID mapping changes not as often as we need a VM flush.
+
+v2: add missing use of gmc_v7_0_emit_pasid_mapping
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 ++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +++++--
+ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 12 ++++++++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 12 ++++++++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 +++++++++++++++++-----------
+ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/si_dma.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 +++-----
+ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 10 ++++------
+ drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 ++++------
+ 22 files changed, 79 insertions(+), 76 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 99eb9cb..15f4cc0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1837,7 +1837,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
+ #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
+ #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
+ #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
+-#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
++#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
++#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
+ #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
+ #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
+ #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
+@@ -1852,7 +1853,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
+ #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
+ #define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
+ #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
+-#define amdgpu_ring_emit_vm_flush(r, vmid, pasid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (pasid), (addr))
++#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
+ #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
+ #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
+ #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index f4b82ef7..f4fdeb2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -54,7 +54,10 @@ struct amdgpu_gmc_funcs {
+ uint32_t vmid);
+ /* flush the vm tlb via ring */
+ uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
+- unsigned pasid, uint64_t pd_addr);
++ uint64_t pd_addr);
++ /* Change the VMID -> PASID mapping */
++ void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
++ unsigned pasid);
+ /* write pte/pde updates using the cpu */
+ int (*set_pte_pde)(struct amdgpu_device *adev,
+ void *cpu_pt_addr, /* cpu addr of page table */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+index 4ea2f15..4dc3208 100755
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+@@ -127,7 +127,7 @@ struct amdgpu_ring_funcs {
+ uint64_t seq, unsigned flags);
+ void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
+ void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
+- unsigned pasid, uint64_t pd_addr);
++ uint64_t pd_addr);
+ void (*emit_hdp_flush)(struct amdgpu_ring *ring);
+ void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
+ void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 6c3036b..08ba210 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -612,8 +612,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
+ struct dma_fence *fence;
+
+ trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
+- amdgpu_ring_emit_vm_flush(ring, job->vmid, job->pasid,
+- job->vm_pd_addr);
++ amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
++ if (adev->gmc.gmc_funcs->emit_pasid_mapping &&
++ ring->funcs->emit_wreg)
++ amdgpu_gmc_emit_pasid_mapping(ring, job->vmid,
++ job->pasid);
+
+ r = amdgpu_fence_emit(ring, &fence);
+ if (r)
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+index 6766f8c..55868fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+@@ -880,13 +880,12 @@ static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ * using sDMA (CIK).
+ */
+ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
+ SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
+
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
+ amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+index e6c3a24..c41415a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+@@ -2355,12 +2355,11 @@ static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ }
+
+ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for the invalidate to complete */
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 916ab66..eb819f9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -3239,12 +3239,11 @@ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ * using the CP (CIK).
+ */
+ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for the invalidate to complete */
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 83ecd27..668cd05 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -6327,12 +6327,11 @@ static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ }
+
+ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for the invalidate to complete */
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 05ccc94..b5505a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3690,10 +3690,9 @@ static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ }
+
+ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* compute doesn't have PFP */
+ if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index 5eacc08..82321f0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -362,8 +362,7 @@ static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
+ }
+
+ static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ uint32_t reg;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 4d2624f..e5cb4fea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -436,8 +436,7 @@ static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
+ }
+
+ static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ uint32_t reg;
+
+@@ -447,14 +446,18 @@ static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
+ amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
+
+- amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
+-
+ /* bits 0-15 are the VM contexts0-15 */
+ amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
+
+ return pd_addr;
+ }
+
++static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
++ unsigned pasid)
++{
++ amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
++}
++
+ /**
+ * gmc_v7_0_set_pte_pde - update the page tables using MMIO
+ *
+@@ -1358,6 +1361,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
+ static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
+ .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
+ .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
++ .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
+ .set_pte_pde = gmc_v7_0_set_pte_pde,
+ .set_prt = gmc_v7_0_set_prt,
+ .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index 6f9375b..6b5ac21 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -616,8 +616,7 @@ static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
+ }
+
+ static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ uint32_t reg;
+
+@@ -627,14 +626,18 @@ static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
+ amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
+
+- amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
+-
+ /* bits 0-15 are the VM contexts0-15 */
+ amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
+
+ return pd_addr;
+ }
+
++static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
++ unsigned pasid)
++{
++ amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
++}
++
+ /**
+ * gmc_v8_0_set_pte_pde - update the page tables using MMIO
+ *
+@@ -1696,6 +1699,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
+ static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
+ .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
+ .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
++ .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
+ .set_pte_pde = gmc_v8_0_set_pte_pde,
+ .set_prt = gmc_v8_0_set_prt,
+ .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index be40aa7..a842d6c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -367,17 +367,15 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
+ }
+
+ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
+ uint64_t flags = AMDGPU_PTE_VALID;
+ unsigned eng = ring->vm_inv_eng;
+- uint32_t reg;
+
+- amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
++ amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
+ pd_addr |= flags;
+
+ amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
+@@ -386,13 +384,6 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
+ upper_32_bits(pd_addr));
+
+- if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+- reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+- else
+- reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+-
+- amdgpu_ring_emit_wreg(ring, reg, pasid);
+-
+ amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
+
+ /* wait for the invalidate to complete */
+@@ -402,6 +393,20 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ return pd_addr;
+ }
+
++static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
++ unsigned pasid)
++{
++ struct amdgpu_device *adev = ring->adev;
++ uint32_t reg;
++
++ if (ring->funcs->vmhub == AMDGPU_GFXHUB)
++ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
++ else
++ reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
++
++ amdgpu_ring_emit_wreg(ring, reg, pasid);
++}
++
+ /**
+ * gmc_v9_0_set_pte_pde - update the page tables using MMIO
+ *
+@@ -528,6 +533,7 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
+ .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
+ .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
++ .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
+ .set_pte_pde = gmc_v9_0_set_pte_pde,
+ .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
+ .get_vm_pde = gmc_v9_0_get_vm_pde
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+index 5e9bea0..722f43b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+@@ -859,10 +859,9 @@ static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ * using sDMA (VI).
+ */
+ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for flush */
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+index 7278003..13c5168 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -1125,10 +1125,9 @@ static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ * using sDMA (VI).
+ */
+ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for flush */
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 4e4ca8f..961f3d1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1133,10 +1133,9 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ * using sDMA (VEGA10).
+ */
+ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+ }
+
+ static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+index 0275e6f..6e25d91 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+@@ -474,10 +474,9 @@ static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ * using sDMA (VI).
+ */
+ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for invalidate to complete */
+ amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+index 4213734..816d706 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+@@ -1084,10 +1084,9 @@ static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
+ }
+
+ static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+- amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+ amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
+@@ -1133,8 +1132,7 @@ static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
+ }
+
+ static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned int vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned int vmid, uint64_t pd_addr)
+ {
+ amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
+ amdgpu_ring_write(ring, vmid);
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+index b031fb9..d028a33 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+@@ -1292,13 +1292,12 @@ static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ }
+
+ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+ uint32_t data0, data1, mask;
+
+- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for reg writes */
+ data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
+@@ -1333,12 +1332,11 @@ static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
+ }
+
+ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned int vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned int vmid, uint64_t pd_addr)
+ {
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+
+- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for reg writes */
+ uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+index c6e9473..085f0ba 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+@@ -844,8 +844,7 @@ static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
+ }
+
+ static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned int vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned int vmid, uint64_t pd_addr)
+ {
+ amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
+ amdgpu_ring_write(ring, vmid);
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+index 22c2067..2329b31 100755
+--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+@@ -975,12 +975,11 @@ static void vce_v4_0_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ }
+
+ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned int vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned int vmid, uint64_t pd_addr)
+ {
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+
+- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for reg writes */
+ vce_v4_0_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+index 3626321..6200f14 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+@@ -896,13 +896,12 @@ static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
+ }
+
+ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned vmid, uint64_t pd_addr)
+ {
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+ uint32_t data0, data1, mask;
+
+- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for register write */
+ data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
+@@ -1034,12 +1033,11 @@ static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
+ }
+
+ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned int vmid, unsigned pasid,
+- uint64_t pd_addr)
++ unsigned int vmid, uint64_t pd_addr)
+ {
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+
+- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
++ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+ /* wait for reg writes */
+ vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 01:00:43 +0000